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  • 4 and 32 Bit Up - Down Counter

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    aniketmiskin8587
    4 views2 pages
    This document contains Verilog code for a 4-bit up-down counter and a 32-bit up-down counter. Each counter module contains code that increments or decrements the count value on each clock edge depending on the value of the control signal m. Test benches are provided to test each counter design by toggling the reset and control signals over time.

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    4 and 32 Bit Up _ Down Counter

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    This document contains Verilog code for a 4-bit up-down counter and a 32-bit up-down counter. Each counter module contains code that increments or decrements the count value on each clock edge depending on the value of the control signal m. Test benches are provided to test each counter design by toggling the reset and control signals over time.

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    4 views2 pages

    4 and 32 Bit Up - Down Counter

    Uploaded by

    aniketmiskin8587
    This document contains Verilog code for a 4-bit up-down counter and a 32-bit up-down counter. Each counter module contains code that increments or decrements the count value on each clock edge depending on the value of the control signal m. Test benches are provided to test each counter design by toggling the reset and control signals over time.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 2

    4 Bit Up - Down Counter

    Verilog Code (.v file)


    module counter(clk,m,rst,count);
    input clk,m,rst;
    output reg [3:0] count;
    always@(posedge clk or negedge rst)
    begin
    if(!rst)
    count=0;
    else if(m)
    count=count+1;
    else
    count=count-1;
    end
    endmodule

    Test Bench (.v file)


    module counter_test;
    reg clk, rst,m;
    wire [3:0] count;
    initial
    begin
    clk=0;
    rst=0;#35;
    rst=1;
    end
    initial
    begin
    m=1;
    #180 m=0;
    end
    initial $sdf_annotate ("delays.sdf" , counter_test.counter1, ,"sdf.log");
    counter counter1(clk,m,rst, count);
    always #5 clk=~clk;
    initial $monitor("Time=%t rst=%b clk=%b count=%b", $time,rst,clk,count);
    initial
    #330 $finish;
    // dumping waves
    initial begin
    $recordfile("test.trn");
    $recordvars;
    end
    endmodule
    32 Bit Up - Down Counter

    Verilog Code (.v file)


    module counter(clk,m,rst,count);
    input clk,m,rst;
    output reg [31:0] count;
    always@(posedge clk or negedge rst)
    begin
    if(!rst)
    count=0;
    else if(m)
    count=count+1;
    else
    count=count-1;
    end
    endmodule

    Test Bench (.v file)


    module counter_test;
    reg clk, rst,m;
    wire [31:0] count;
    initial
    begin
    clk=0;
    rst=0;#35;
    rst=1;
    end
    initial
    begin
    m=1;
    #180 m=0;
    end
    initial $sdf_annotate ("delays.sdf" , counter_test.counter1, ,"sdf.log");
    counter counter1(clk,m,rst, count);
    always #5 clk=~clk;
    initial $monitor("Time=%t rst=%b clk=%b count=%b", $time,rst,clk,count);
    initial
    #330 $finish;
    // dumping waves
    initial begin
    $recordfile("test.trn");
    $recordvars;
    end
    endmodule

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