1 gui_start

2 cd lab2_floorplan/
3 open_block ORCA_TOP.dlib : ORCA_TOP/floorplan
4 open_block
/proj/pd/venkatar/ICC2_BLI_2019.12-SP4/lab2_floorplan/ORCA_TOP.dlib:ORCA_TOP/
floorplan.design
5 link_block
6 link_block
7 read_verilog ./ref/ORCA_TOP_design_data/ORCA_TOP.v
8 pwd
9 cd ..
10 load_upf lab56_setup/ORCA_TOP_design_data/ORCA_TOP.upf
11 read_def ./ref/ORCA_TOP_design_data/ORCA_TOP.scandef
12 report_design_mismatch
13 check_mv_design
14 check_netlist
15 check_timing
16 check_scan_chain
17 initialize_floorplan -shape L -core_offset {10} -side_ratio {2 2} -
core_utilization 0.6
18 initialize_floorplan -shape L -core_offset {10} -side_ratio {2 1 1 1} -
core_utilization 0.6
19 initialize_floorplan -shape L -core_offset {10} -side_ratio {1 1 1 1} -
core_utilization 0.6
20 set_attribute [get_layers "M1 M3 M5 M7 M9"] routing_direction horizontal
21 set_attribute [get_layers "M2 M4 M6 M8 MRDL"] routing_direction vertical
22 set_block_pin_constraints -sides {3 4} -allowed_layers {M3 M4} -pin_spacing
5 -corner_keepout_distance 50 -self
23 place_pins -ports [get_ports *]
24 history
25 get_clocks
26 sizeof_collection [get_clocks]
27 sizeof_collection [get_ports]
28 get_flat_cells -filter "is_hard_macro == true "
29 sizeof_collection [get_flat_cells -filter "is_hard_macro == true "]
30 get_flat_cells
31 sizeof_collection [get_lib_cells]
32 sizeof_collection [get_flat_cells]
33 history
34 get_lib_cells
35 sizeof_collection [get_lib_cells]
36 set all_macros [get_cells -hierarchical -filter "is_hard_macro && !
is_physical_only"]
37 set_attribute [get_flat_cells -filter "is_hard_macro"] physical_status
fixed
38 create_keepout_margin -type hard -outer {2 2 2 2} $all_macros
39 get_keepout_margins
40 report_keepout_margins
41 get_keepout_margins
42 sizeof_collection [get_keepout_margins]
43 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_1}
44 remove_placement_blockages [get_selection]
45 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_0}
46 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_2}
47 remove_placement_blockages [get_selection]
48 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_0}
49 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_1}
50 remove_placement_blockages [get_selection]
51 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_0}
52 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_3}
53 remove_placement_blockages [get_selection]
54 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_0}
55 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_4}
56 load_upf
/proj/pd/venkatar/ICC2_BLI_2019.12-SP4/ref/ORCA_TOP_design_data/ORCA_TOP.upf
57 report_power_domains
58 gui_set_mouse_tool_option -tool CreatePlcBlkgTool -option {name} -value
{pb_5}
59 create_voltage_area -power_domains PD_RISC_CORE -region {{12.530 994.063}
{209.956 568.790}} -guard_band {{5 5}}
60 remove_placement_blockages [get_selection ]
61 set pre_place_cell "saed32_hvt|saed32_hvt_std/DCAP_HVT"
62 set_boundary_cell_rules -left_boundary_cell $pre_place_cell -
right_boundary_cell $pre_place_cell
63 compile_boundary_cells
64 check_boundary_cells
65 save_block -as blockLfp
66 pwd
67 source lab2_floorplan/scripts/pns.tcl
68 sizeof_collection [get_ports]
69 gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name ==
metal8} -quiet]
70 gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name ==
metal7} -quiet]
71 gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name ==
metal2} -quiet]
72 gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name ==
metal5} -quiet]
73 gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name ==
metal6} -quiet]
74 gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name ==
metal3} -quiet]
75 gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name ==
metal4} -quiet]
76 check_design -checks pre-placement_stage
77 check_design -checks pre_placement_stage
78 check_design -checks physical_constraints
79 create_tap_cells -lib_cell $pre_place_cell -distance 30 -pattern stagger
80 read_def ref/ORCA_TOP_design_data/ORCA_TOP.scandef
81 report_scan_chains
82 get_scan_chain_count
83 get_corners
84 get_modes
85 get_scenarios
86 check_mv_design
87 report_qor
88 check_pg_missing_vias
89 check_pg_drc
90 create_placement -congestion -congestion_effort high -incremental
 91 create_placement -incremental
92 create_placement -timing_driven
93 report_timing
94 report_congestion
95 legalize_placement -incremental
96 check_pg_drc
97 place_opt
98 report_timing
99 report_timing -delay_type min
100 report_constraints -all_violators
101 check_pg_drc
102 save_block -as blockLfptoplaceopt
103 source lab7_cts/scripts/cts_ex_ndr.tcl
104 pwd
105 cd lab7_cts/scripts/
106 cd ..
107 source lab7_cts/scripts/cts_ex_ndr.tcl
108 source scripts/ndr.tcl
109 pwd
110 source run.tcl
111 pew
112 pwd
113 source scripts/cts_ex_ndr.tcl
114 report_scenarios
115 set_app_options -name opt.dft.clock_aware_scan_reorder -value true
116 set_app_options -name time.remove_clock_reconvergence_pessimism -value true
117 foreach_in_collection mode [all_modes] {
current_mode $mode
set_latency_adjustment_options -exclude_clocks "*"
set_latency_adjustment_options -reference_clock PCI_CLK -clocks_to_update
v_PCI_CLK
}
118 set_app_options -name clock_opt.flow.enable_ccd -value false
119 set_app_options -name cts.compile.enable_local_skew -value true
120 set_app_options -name cts.optimize.enable_local_skew -value true
121 clock_opt -to route_clock
122 report_timing
123 report_timing -delay_type min
124 clock_opt -from final_opto
125 history
126 report_timing
127 report_timing -delay_type min
128 report_units
129 get_clocks
130 check_legality
131 check_lvs
132 save_block -as blockLfptoctsopt
133 report_constraints -all_violators
134 get_corners
135 set_app_options -name route.common.verbose_level -value 1
136 check_design -checks pre_route_stage
137 set_app_options -name route.common.verbose_level -value 0
138 pwd
139 cd ../lab11_route_signoff/
140 source ../ref/tech/saed32nm_ant_1p9m.tcl
141 set_app_options -name route.global.timing_driven -value true
142 set_app_options -name route.global.crosstalk_driven -value false
143 set_app_options -name route.track.timing_driven -value true
144 set_app_options -name route.track.crosstalk_driven -value true
 145 set_app_options -name route.detail.timing_driven -value true
146 set_app_options -name route.detail.force_max_number_iterations -value false
147 report_power_domains
148 set_app_options -name route.common.number_of_secondary_pg_pin_connections -
value 2
149 set_app_options -name route.common.separate_tie_off_from_secondary_pg -
value true
150 if {[get_routing_rules -quiet VDDwide] != ""} {remove_routing_rules VDDwide
}
151 create_routing_rule VDDwide -widths {M1 0.1 M2 0.1 M3 0.1} -taper_distance
0.2
152 set_routing_rule -rule VDDwide -min_routing_layer M2 -min_layer_mode
allow_pin_connection -max_routing_layer M3 [get_nets VDD]
153 route_group -nets {VDD}
154 route_auto
155 check_routes
156 set_starrc_in_design -config ./scripts/starrc_config.txt
157 set_app_options -name time.si_enable_analysis -value true
158 set_app_options -name time.enable_ccs_rcv_cap -value true
159 set_app_options -name time.delay_calc_waveform_analysis_mode -value
full_design
160 route_opt
161 set_app_options -name
route.detail.eco_route_use_soft_spacing_for_timing_optimization -value false
162 set_app_options -name route_opt.flow.enable_ccd -value false
163 route_opt
164 report_timing
165 report_timing -delay_type min
166 report_timing
167 check_lvs
168 report_congestion
169 report_utilization
170 update_timing
171 check_pg_drc
172 report_qor
173 report_constraints -all_violators
174 report_constraints -all_violators -max_capacitance
175 check_lvs
176 check_pg_drc
177 save_block -as blockLfptorouteopt
178 check_lvs