Advanced microprocessor Module I

MODULE 1
Features of Intel 8086
 It is a16 bit microprocessor. It can access 16 bit data at a time
 8086 has 20 bit address bus, so it can handle 220 = I MB or 1048576 memory locations
 8086 designed to operate in two modes, namely Minimum mode and maximum mode
 It consist of 9 flags and fourteen 16 bit registers
 It is a N channel HMOS microprocessor
 8086 built on a single semiconductor chip and packaged in a 40 pin DIP IC
 It supports two stage pipelining ie fetching and executing are in parallel
 Clock speed of 8086 – 5MHz,8MHz,10Mhz
 It consist of 29000 transistors
 It has a powerful instruction set

Internal architecture of 8086

The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU), and The
Execution Unit (EU).

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various
machine cycles such as memory read, I/O read, etc. to transfer data between memory and I/O devices.
BIU performs the following functions are :
 It generates the 20-bit physical address for memory access.

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Advanced microprocessor Module I
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction queue(supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and an Address
Generation Circuit.

Segment registers
8086 has 4 segment registers which are used to hold upper 16 bit starting address of memory segments
Code Segment register: (16 Bit register): CS holds the base address for the Code Segment. All programs are
stored in the Code Segment and accessed via the IP.
Data Segment register: (16 Bit register): DS holds the base address for the Data Segment.
Stack Segment register: (16 Bit register): SS holds the base address for the Stack Segment.
Extra Segment register: (16 Bit register): ES holds the base address for the Extra Segment.
Address Generation Circuit:
 The BIU has a Physical Address Generation Circuit.
 It generates the 20-bit physical address using Segment and Offset addresses using the formula:
 In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible for the calculation unit
which is used to calculate the physical address of an instruction in memory.

Six Byte Pre-fetch Queue:

It is a 6-byte queue (FIFO).
Fetching the next instruction (by BIU from CS) while executing the current instruction is called pipelining.

2. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers, the
Instruction Register and Instruction Decoder, and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic operations using
the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.(Control Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.

8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate values during
execution. Each of these has two 8-bit parts (higher and lower).
Arithmetic Logic Unit (16-bit): Performs 8 and 16-bit arithmetic and logic operations

Memory segmentation in 8086

 8086 has 20 bit address, so it can access 220 =1MB memory location having an address from 00000 to
FFFFFH
 Memory data is stored as bytes
 Total memory size 1MB is divided in to four segments having 64 kb size each and each having its own
base address
 Four segments are
1. Code segment:- it stores the executable program code in the memory

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Advanced microprocessor Module I
2. Data segment:- it stores data in memory
3. Extra segment:- it stores the additional data in memory
4. Stack segment:- it stores the stacked data in memory

BIU of 8086 microprocessor contains four 16 bit special purpose register called as segment register. That are
1. Code segment register :- holds the upper 16 bit base address of code segment in memory
2. Data segment register: - holds the upper 16 bit base address of data segment in memory.
3. Stack segment register: - holds the upper 16 bit base address of stack segment in memory.
4. Extra segment register:- holds the upper 16 bit base address of extra segment in memory.

Physical address (calculation) generation

 The 8086 addresses a segmented memory.

 The complete physical address which is 20-bits long is generated using segment and offset registers each of
the size 16-bit.
 The content of a segment register also called as segment address, and content of an offset register also called
as offset address.
 Segment register holds the upper 16 bit base address of corresponding segments
 Index and pointer register in 8086 microprocessor holds the offset value of each segment
That are:
CS : IP
DS : SI(DI/BX)

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 Advanced microprocessor Module I
SS : SP/BP
ES : DI
Base address: starting address of segments
Offset address: displacement from base address to the data stored actual address

Physical address = base address*10H+ offset address value

Ex: If CS holds 1634H and IP point out 0033H

Physical address =1634*10H+0033H
= 16463 H
Register set of 8086

A register is a very small amount of fast memory that is built in CPU in order to speed up the operation.
8086 registers are classified into following types
 General purpose registers
 Segment registers
 pointers and index registers
 flag registers

1) General Purpose Registers

The use of general-purpose registers is to store temporary data. While the instructions are executed in the control
unit, they may work on some numeric value or some operands. These need to be stored somewhere so that the
processor can operate on them easily. So, these registers are used in these cases. There are 4 general-purpose
registers of 16-bit length each. Each of them is further divided into two subparts of 8-bit length each: one high,
which stores the higher-order bits and another low which stores the lower order bits.

i. AX = [AH:AL]
ii. BX = [BH:BL]
iii. CX = [CH:CL]

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 Advanced microprocessor Module I
iv. DX = [DH:DL]

2) Segment Registers

There are 4 segment registers in 8086 Microprocessor and each of them is of 16 bit. The code and instructions
are stored inside these different segments.

1. Code Segment (CS) Register:

The user cannot modify the content of these registers. Only the microprocessor's compiler can do this.
2. Data Segment (DS) Register:
The user can modify the content of the data segment.
3. Stack Segment (SS) Registers:
The SS is used to store the information about the memory segment. The operations of the SS are mainly
Push and Pop.
4. Extra Segment (ES) Register:
By default, the control of the compiler remains in the DS where the user can add and modify the
instructions. If there is less space in that segment, then ES is used. ES is also used for copying purpose.

3) Pointers and Index Registers

The pointers will always store some address or memory location. In 8086 Microprocessor, they usually store the
offset through which the actual address is calculated.

1. Instruction Pointer (IP):

The instruction pointer usually stores the address of the next instruction that is to be executed. Apart from
this, it also acts as an offset for CS register.
2. Base Pointer (BP):
The Base pointer stores the base address of the memory. Also, it acts as an offset for Stack Segment (SS).
3. Stack Pointer (SP):
The Stack Pointer Points at the current top value of the Stack. Like the BP, it also acts as an offset to the
Stack Segment (SS).
The indexes are used with the extra segment and they usually are used for copying the contents of a
particular block of memory to a new location.
4. Source Index (SI):
It stores the offset address of the source.
5. Destination Index (DI):
It stores the offset address of the Destination.

4) Flag or Status Register

The Flag or Status register is a 16-bit register which contains 9 flags, and the remaining 7 bits are idle in this
register. These flags tell about the status of the processor after any arithmetic or logical operation. IF the flag
value is 1, the flag is set, and if it is 0, it is said to be reset

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Advanced microprocessor Module I
FLAG REGISTER
The flag register is one of the special purpose register. The flag bits are changed to 0 or 1 depending upon the
value of result after arithmetic or logical operations.
8086 has 16-bit flag register, and there are 9 valid flag bits. The format of flag register is like below.

Bits D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Flags O D I T S Z AC P CY

We can divide the flag bits into two sections. The Status Flags, and the Control Flags.

Status Flags
In 8086 there are 6 different flags which are set or reset after 8-bit or 16-bit operations. These flags and their
functions are listed below.

Flag Bit Function

S After any operation if the MSB is 1, then it indicates that the number is negative. And this flag is
set to 1

Z If the total register is zero, then only the Z flag is set

AC When some arithmetic operations generates carry after the lower half and sends it to upper half,
the AC will be 1

P This is even parity flag. When result has even number of 1, it will be set to 1, otherwise 0 for odd
number of 1s

CY This is carry bit. If some operations are generating carry after the operation this flag is set to 1

O The overflow flag is set to 1 when the result of a signed operation is too large to fit.

Control Flags
In 8086 there are 3 different flags which are used to enable or disable some basic operations of the
microprocessor. These flags and their functions are listed below.

Flag Bit Function

D This is directional flag. This is used in string related operations. D = 1, then the string will be
accessed from higher memory address to lower memory address, and if D = 0, it will do the
reverse.

I This is interrupt flag. If I = 1, then MPU will recognize the interrupts from peripherals. For I = 0,
the interrupts will be ignored

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 Advanced microprocessor Module I

Flag Bit Function

T This trap flag is used for on-chip debugging. When T = 1, it will work in a single step mode. After
each instruction, one internal interrupt is generated. It helps to execute some program instruction by
instruction.

PIN diagram of 8086

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply for its
operation. The 8086 uses a 20-line address bus. It has a 16-line data bus. The 20 lines of the address bus
operate in multiplexed mode. The 16-low order address bus lines have been multiplexed with data and 4 high-
order address bus lines have been multiplexed with status signals.
AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with data. When AD
lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When
data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-
D15.
A16-A19: High order address bus. These are multiplexed with status signals
S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1
during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for generating all the
memory and I/O operation) access control signals. Any change in S2, S1, S0 during T4 indicates the beginning
of a bus cycle.
S2 S1 S0 Characteristics

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S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding status
signals.
A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of
data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is
multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.
RD’: This is used for read operation. It is an output signal. It is active when low.
READY : This is the acknowledgement from the memory or slow device that they have completed the data
transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide
ready input to the microprocessor. The signal is active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each
instruction for determining the availability of the request. If any interrupt request is found pending, the
processor enters the interrupt acknowledge cycle. This can be internally masked after resulting the interrupt
enable flag. This signal is active high(1) and has been synchronized internally.

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 Advanced microprocessor Module I
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A
subroutine is then vectored through an interrupt vector lookup table which is located in the system memory.
NMI is non-maskable internally by software. A transition made from low(0) to high(1) initiates the interrupt at
the end of the current instruction. This input has been synchronized internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the
microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of the pin is
bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to gain control
of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the completion of the
next instruction.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else
the processor remains in an idle state. The input is internally synchronized during each of the clock cycle on
leading edge of the clock.
CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control
activity. Its an asymmetric square wave with a 33% duty cycle.
RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal must
be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according to
the table shown below:
QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or 8287
data bus transceiver. The direction of data flow is controlled through the transceiver.
DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system which
uses transceiver. DEN is active low(0) during each memory and input-output access and for INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an active
high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an acknowledgement in
the middle of a T4 or T1 clock cycle.
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282 or
8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never floated, is
always integer.

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 Advanced microprocessor Module I
Minimum mode configuration of 8086
 The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.
 In minimum mode,8086 is the only processor in the system which provides all the control signals which
are needed for memory operations and I/O interfacing.
 The other components which are transceivers, latches, 8284 clock generator, 74138 decoder, memory and
i/o devices are also present in the system.
20
 The address bus of 8086 is 20 bits long. By this we can access 2 byte memory i.e. 1MB . Out of 20 bits,
16 bits A0 to A15(or 16 lines) are multiplexed with a data bus. By multiplexing, it means they will act as
address lines during the first T state of the machine cycle and in the rest, they act as data lines. A 16 to
A19 are multiplexed S3 to S6 and BHE’ is multiplexed with S7.
Control signals provided by 8086 for memory operations and i/o interfacing :
They are used to identifying whether the bus is carrying a valid address or not , in which direction data is needed
to be transferred over the bus, when there is valid write data on the data bus and when to put read data on the
system bus. Therefore, their sequence pattern makes all the operations successful in a particular machine cycle.

Min mode circuit

8282 (8 bits) latch :

The latches are buffered D FF. They are used to separate the valid address from the multiplexed Address/data bus
by using the control signal ALE, which is connected to strobe(STB) of 8282. The ALE is active high signal. Here
three such latches are required because the address is 20 bits.
8286 (8 bits) transceivers :
They are bidirectional buffers and also known as data amplifiers. They are used to separate the valid data from

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 Advanced microprocessor Module I
multiplexed add/data bus. Two such transceivers are needed because the data bus is 16 bits long. 8286 is
connected to DT/R’ and DEN’ signals. They are enabled through the DEN signal .The direction of data on the
data bus is controlled by the DT/R’ signal. DT/R’ is connected to T and DEN’ is connected to OE’.

 8284 clock generator is used to provide the clock.

 M/IO’= 1,then I/O transfer is performed over the bus. and when M/IO’ = 0, then I/O operation is
performed.
 The signals RD’ and write WR’ are used to identify whether a read bus cycle or a write bus cycle is
performing. When WR’ = 0 ,then it indicates that valid output data on the data bus.
 RD’ indicates that the 8086 is performing a read data or instruction fetch process is occurring
.During read operations, one other control signal is also used, which is DEN ( data enable) and it
indicates the external devices when they should put data on the bus.
 Control signals for all operations are generated by decoding M/IO’, RD’, WR’. They are decoded
by 74138 3:8 decoder.

 INTR and INTA :

When INTR = 1,then there is an interrupt to 8086 by other devices for their service. When INTA’=
0,then it indicates that the processor is ready to service them.
 The bus request is made by other devices using the HOLD signal and the processor acknowledges
them using the HLDA output signal.
 For more details about the 8086 minimum mode pins please refer(this article).
Timing diagram :
The working of min mode can be easily understood by timing diagrams.
 All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is given by processor in
the T1 state. It is available on the bus for one T-state.
 In T2, the bus is tristated for changing the direction of the bus( in the case of a data read cycle.)
 The data transfer takes place between T3 and T4.
 If the addressed device is slower, then the wait state is inserted between T 3 and T4.

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Opcode fetch or read timing diagram

 At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus and also M /
IO’= 1, which indicates the memory operation is in progress.
 In T2, the address is removed from the local bus and is sent to the addressed device. Then the bus
is tristated.
 When RD’ = 0 , the valid data is present on the data bus.
 During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates that the data is
received.
 During T3, data is put on the data bus and the processor reads it.
 The output device makes the READY line high. This means the output device has performed the
data transfer process. When the processor makes the read signal to 1, then the output device will
again tristate its bus drivers.

Maximum mode configuration of 8086

 When MN/ MX’ = 0 , 8086 works in max mode.
 Clock is provided by 8284 clock generator.
8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three such latches are
required because address bus is 20 bit. The ALE(Address latch enable) is connected to STB(Strobe) of the
latch. The ALE for latch is given by 8288 bus controller

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 The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required, because data
bus is 16-bit. The transceivers are enabled the DEN signal, while the direction of data is controlled by
the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected to T. Both DEN and DT/ R’ are
given by 8288 bus controller.

 Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288 bus
controller.

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 Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ 0/GT0 has more priority than
RQ1/GT1.
 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
 In max mode, the advanced write signals get enabled one T-state in advance as compared to normal write
signals. This gives slower devices more time to get ready to accept the data, therefore it reduces the
number of cycles.

Max mode read cycle Timing diagram

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