Assessment 3

Real Time Time-Slice System

Submitted By:
Rijo Rajamony –c2058562
Sanjay Rajkumar-c2020381
A design of an innovative sign board for street vendors in
low cost.

INTRODUCTION
This REALTIME SYSTEM is focused on an innovative design for a digital
sign board In this case a CAFE. It is effectively designed to accomplish
the goal of having an effective and reliable advertisement system . By
using Interrupt service Routine codes and Time Slicing Method to make
Led Pattern.
 USER MANUAL

1. Execute the developed code.

2. Set the timer interrupt to 1000 ms , it can also be set to 500ms.

3. To start setting up the hardware set the address of the 7segment display to
F00000 .
 4. 8 high quality LED is integrated to the hardware ADDRESS = E00010.
5. 8 toggle switches is also provided, ADDRESS= E00012.
6. 8 push buttons are also provided onboard, ADDRESS = E00014.

CODE WORK PLAN

1. At first the data storage definitions and interrupt vector definitions are
defined.
2. Reset system is enabled to enable and clean TCB.
3. First level interrupt handler it executes the code is executed immediately
following an interrupt.
4. Interrupt Service Routines are large switching statements, it recognizes the
case variable by specific ID’s.
5. Scheduler checks the ready list in which rdytcb points to the first element.
when an interrupt hits the scheduler takes care of the TCB execution of
system.
6. Dispatcher restores register values of the selected task to the values that
were stored when the task was interrupted.
7. Data storage for a list of TCB’s is defined as
 tcblst ds.b tcblen*ntcb ;tcb list (length x no of tcbs)
rdytcb ds.l 1 ;^ ready tcb list
wttcb ds.l 1 ;^ waiting tcb list
a0sav ds.l 1 ;A0 temporary save
d0sav ds.l 1 ;D0 temporary save
id ds.l 1 ;function id

FINAL PROGRAM
;**********************************************************
**************************
data defenitions
;**********************************************************
**************************
system equ 0
starttask equ 1
systemend equ 2
systemwtim equ 3

ntcblst equ 8
tcb org 0 ;D register save
tcbd0 ds.l 1 ;tcb record
tcbd1 ds.l 1
tcbd2 ds.l 1
tcbd3 ds.l 1
tcbd4 ds.l 1
tcbd5 ds.l 1
tcbd6 ds.l 1
tcbd7 ds.l 1
tcba0 ds.l 1
tcba1 ds.l 1
tcba2 ds.l 1
tcba3 ds.l 1
tcba4 ds.l 1
tcba5 ds.l 1
tcba6 ds.l 1
tcba7 ds.l 1
tcbsr ds.l 1 ; SR (status reg) save
tcbpc ds.l 1 ; PC save
tcbnext ds.l 1 ; link to next record
tcbused ds.l 1 ; record in use flag
tcbwtim ds.l 1 ; timer wait expiry time
tcblen equ * ; length of tcb record in bytes

The above set of code holds the Declaration of Task Control Block of
data registers and address registers.
;***************************************************
*Interrupt Vectors
;***************************************************
rts
org 0
dc.l $3000 ; initial SP
dc.l res ; reset
ds.b $5C
dc.l fltmrint ; interrupt 1 (timer)
ds.b $18
dc.l fstlevsoftint ; trap 0 (system call)
The interrupt Vectors are the spine of an Real time System. The decision making
of wheather to move to next is performed by the Interrupt vectors.
*********************************************************************
First Level Interrupt handlers
*********************************************************************

fltmrint ;ENTRY FROM TIMER INTERRUPT

move.l d0,d0sav ;save D0
move.l #$0,d0 ;set id = 0
move.l d0,id

move.l d0sav,d0 ;restore D0

bra fl1
fstlevsoftint

or #%0000011100000000,sr
move.l d0,id
bra fl1

fl1 move.l a0,a0sav

move.l rdytcb,a0
move.l d0,tcbd0(a0)
move.l d1,tcbd1(a0)
move.l d2,tcbd2(a0)
move.l d3,tcbd3(a0)
move.l d4,tcbd4(a0)
move.l d5,tcbd5(a0)

move.l d6,tcbd6(a0)
move.l d7,tcbd7(a0)
move.l a0sav,d0
 move.l d0,tcba0(a0)
move.l a1,tcba1(a0)
move.l a2,tcba2(a0)

move.l a3,tcba3(a0)
move.l a4,tcba4(a0)
move.l a5,tcba5(a0)
move.l a6,tcba6(a0)

move (sp),d0 ;pop and store SR

add.l #2,sp
move.l d0,tcbsr(a0)
move.l (sp),d0 ;pop and store PC

add.l #4,sp
move.l d0,tcbpc(a0)
move.l a7,tcba7(a0) ;store SP

The first level interrupt handler (FLIH) is responsible for handling the interrupts, it it further
divided into timer or hardware interrupts and software interrupts.

*---------------------------------------------------------------------------------------------------

;SERVICE ROUTINE

*----------------------------------------------------------------------------------------------------

serv
service0: move.l id,d0
cmp.l #0,d0
bne service1

move.l time,d0
add.l #1,d0
move.l d0,time
bra sched

service1 cmp.l #starttask,d0

bne service2
move.l #tcblst,a2

service11 move.l tcbused(a2),d0

beq service12
add.l #tcblen,a2

bra service11

service12 move.l rdytcb,a0

move.l tcbd1(a0),d0

move.l d0,tcbpc(a2)
move.l #$00002000,d0
move.l d0,tcbsr(a2)
move.l tcbd2(a0),d0

move.l d0,tcba7(a2)
move.l #1,d0
 move.l d0,tcbused(a2)
move.l rdytcb,a0
move.l tcbnext(a0),d0

move.l d0,tcbnext(a2)
move.l a2,tcbnext(a0)
bra sched

service2 cmp.l #systemend,d0

bne service20
move.l rdytcb,a0
move.l a0,a1

service20 move.l tcbnext(a1),a2

cmp.l a2,a0
beq service21
move.l tcbnext(a1),a1
bra service20

service21 move.l tcbnext(a0),a2

move.l a2,tcbnext(a1)
 move.l #0,d0
move.l d0,tcbused(a0)
bra sched

*---------------------------------------------------------------------------------------------------

;SCHEDULER

*----------------------------------------------------------------------------------------------------

move.l rdytcb,a0
move.l tcbnext(a0),a0 ;ready tcb next tcb
move.l a0,rdytcb
Scheduler is responsible for scheduling the next task in queue,after
the queue is completely made by ISR , the scheduler schedules the next
in queue.
*---------------------------------------------------------------------------------------------
------
;DISPATCHER
*---------------------------------------------------------------------------------------------
-------

move.l rdytcb,a0 ;A0 ^ new running tcb

move.l tcbd1(a0),d1 ;restore registers
move.l tcbd2(a0),d2
move.l tcbd3(a0),d3
move.l tcbd4(a0),d4
move.l tcbd5(a0),d5
move.l tcbd6(a0),d6
move.l tcbd7(a0),d7
move.l tcba1(a0),a1
move.l tcba2(a0),a2
move.l tcba3(a0),a3
move.l tcba4(a0),a4
move.l tcba5(a0),a5
move.l tcba6(a0),a6
move.l tcba7(a0),a7
 sub.l #4,sp
move.l tcbpc(a0),d0
move.l d0,(sp)
sub.l #2,sp
move.l tcbsr(a0),d0
move d0,(sp)
move.l tcbd0(a0),d0
move.l tcba0(a0),a0
rte

tcblst ds.l tcblen*ntcblst ;tcb list (length x no of tcbs)

rdytcb ds.l 1 ;^ ready tcb list
wttcb ds.l 1 ;^ waiting tcb list
a0sav ds.l 1 ;A0 temporary save
d0sav ds.l 1 ;D0 temporary save
id ds.l 1 ;function id
time ds.l 1 ;system time

The value of the data registers and address registers are taken from the system
memory. The registers are set to hit the specific task assigned by scheduler with
the data.
;******************************************************************
**************
;USER APPLICATION TASKS

;******************************************************************
*************
org 2000
led equ $e00010

sw equ $e00014
emptyspa1 equ $f00000
emptyspa2 equ $f00002
emptyspa3 equ $f0000c
emptyspa4 equ $f0000e
sevseg equ $f00004
sevseg2 equ $f00006
sevseg3 equ $f00008
sevseg4 equ $f0000a

tsk0: ;TASK 0
 move.l #starttask,d0
move.l #tsk1,d1
move.l #$4000,d2
trap #system

;repeat

tsk00: move.l #$55,d1

move.b d1,led
move.b #$00,emptyspa1
move.b #$00,emptyspa2
move.b #$00,emptyspa3
move.b #$00,emptyspa4

move.b #$39,sevseg
move.b #$77,sevseg2
move.b #$71,sevseg3
move.b #$79,sevseg4

bra tsk00
tsk1: ;TASK 1

;repeat

tsk10: move.l #$AA,d0

move.b d0,led

move.b #$00,emptyspa1

move.b #$00,emptyspa2

move.b #$00,emptyspa3

move.b #$00,emptyspa4

move.b #$00,sevseg

move.b #$00,sevseg2

move.b #$00,sevseg3

move.b #$00,sevseg4
bra tsk10

;END res

end start