Verilog module of the prototype ALU:

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////
////////
// Company:
// Engineer:
//
// Create Date: 10/05/2023 02:46:57 PM
// Design Name:
// Module Name: y0006
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////
////////
module half_addr(a1,b1,s,c);
input a1,b1;
output s,c;
xor G1(s,a1,b1);
and G2(c,a1,b1);
endmodule

module full_addr(a2,b2,cin,s1,c1);
input a2,b2,cin;
output s1,c1;
wire w1,w2,w3;
half_addr G3(a2,b2,w1,w2);
half_addr G4(w1,cin,s1,w3);
or G5(c1,w3,w2);
endmodule

module four_bit_addr(a,b,cin2,sum,cout);
input [3:0]a,b;
input cin2;
output [3:0]sum;
output cout;
//wire [3:0] sum;
wire [2:0] cout1;
full_addr FA1(a[0],b[0],cin2,sum[0],cout1[0]);
full_addr FA2(a[1],b[1],cout1[0],sum[1],cout1[1]);
full_addr FA3(a[2],b[2],cout1[1],sum[2],cout1[2]);
full_addr FA4(a[3],b[3],cout1[2],sum[3],cout);
endmodule
module y0006(A,B,Cin3,S,CF,OF,SF,ZF /*, LED, disp */ );
input [3:0] A,B;
input Cin3;
output [3:0] S;
//output Cout1:
output CF,OF,SF,ZF;
//reg [3:0] S;
reg OF,SF,ZF;
//output [6:0] LED;
four_bit_addr A1(A,B,Cin3,S,CF);

always @(A or B or S)
begin

//{CF,S} <= A + B;
OF <= ((A[3]==B[3])&&(S[3]!=A[3])) ? 1:0;
SF <= S[3];
ZF <= (S==4'b0000) ? 1:0;
end

/* always @(S)
begin
disp <= 4'b1110;
case (S)
4'b0001 : LED = 7'b1111001; //1
4'b0010 : LED = 7'b0100100; //2
4'b0011 : LED = 7'b0110000; //3
4'b0100 : LED = 7'b0011001; //4
4'b0101 : LED = 7'b0010010; //5
4'b0110 : LED = 7'b0000010; //6
4'b0111 : LED = 7'b1111000; //7
4'b1000 : LED = 7'b0000000; //8
4'b1001 : LED = 7'b0010000; //9
4'b1010 : LED = 7'b0001000; //A
4'b1011 : LED = 7'b0000011; //b
4'b1100 : LED = 7'b1000110; //C
4'b1101 : LED = 7'b0100001; //d
4'b1110 : LED = 7'b0000110; //E
4'b1111 : LED = 7'b0001110; //F
default : LED = 7'b1000000; //0
endcase
end */

endmodule

Testbench:
timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////
////////
// Company:
// Engineer:
//
// Create Date: 10/05/2023 04:13:25 PM
// Design Name:
// Module Name: test_bench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
module y0006_y0006_TB2_v_tf();

integer i,j;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin3;

// Outputs
wire [3:0] S;
wire CF;
wire OF;
wire SF;
wire ZF;

// Instantiate the UUT

y0006 uut (
.A(A),
.B(B),
.Cin3(Cin3),
.S(S),
.CF(CF),
.OF(OF),
.SF(SF),
.ZF(ZF)
);

initial begin
$monitor("Time=%t, A=%b, B=%b, Cin3=%b, S=%b, CF=%b, OF=%b, SF=%b,
ZF=%b",
$realtime, A, B, Cin3, S, CF, OF, SF, ZF);
end

initial begin
 A = 0;
B = 0;
Cin3=0;
for (i=0; i<16; i=i+1)
begin
for (j=0; j<16; j=j+1)
begin
#50 A=i;
#50 B=j;
end
end
$finish;
$stop;
end
endmodule

structural simulation report:

Output:
 1100000, A=0000, B=1010, Cin3=0, S=1010, CF=0, OF=0, SF=1, ZF=0
Time= 1200000, A=0000, B=1011, Cin3=0, S=1011, CF=0, OF=0,
SF=1, ZF=0
Time= 1300000, A=0000, B=1100, Cin3=0, S=1100, CF=0, OF=0,
SF=1, ZF=0
Time= 1400000, A=0000, B=1101, Cin3=0, S=1101, CF=0, OF=0,
SF=1, ZF=0
Time= 1500000, A=0000, B=1110, Cin3=0, S=1110, CF=0, OF=0,
SF=1, ZF=0
Time= 1600000, A=0000, B=1111, Cin3=0, S=1111, CF=0, OF=0,
SF=1, ZF=0
Time= 1650000, A=0001, B=1111, Cin3=0, S=0000, CF=1, OF=0,
SF=0, ZF=1
Time= 1700000, A=0001, B=0000, Cin3=0, S=0001, CF=0, OF=0,
SF=0, ZF=0
Time= 1800000, A=0001, B=0001, Cin3=0, S=0010, CF=0, OF=0,
SF=0, ZF=0
Time= 1900000, A=0001, B=0010, Cin3=0, S=0011, CF=0, OF=0,
SF=0, ZF=0
Time= 2000000, A=0001, B=0011, Cin3=0, S=0100, CF=0, OF=0,
SF=0, ZF=0
Time= 2100000, A=0001, B=0100, Cin3=0, S=0101, CF=0, OF=0,
SF=0, ZF=0
Time= 3800000, A=0010, B=0101, Cin3=0, S=0111, CF=0, OF=0,
SF=0, ZF=0
Time= 3900000, A=0010, B=0110, Cin3=0, S=1000, CF=0, OF=1,
SF=1, ZF=0
Time= 4000000, A=0010, B=0111, Cin3=0, S=1001, CF=0, OF=1,
SF=1, ZF=0
Time= 4100000, A=0010, B=1000, Cin3=0, S=1010, CF=0, OF=0,
SF=1, ZF=0
Time= 4200000, A=0010, B=1001, Cin3=0, S=1011, CF=0, OF=0,
SF=1, ZF=0
Time= 4300000, A=0010, B=1010, Cin3=0, S=1100, CF=0, OF=0,
SF=1, ZF=0
Time= 4400000, A=0010, B=1011, Cin3=0, S=1101, CF=0, OF=0,
SF=1, ZF=0
Time= 4500000, A=0010, B=1100, Cin3=0, S=1110, CF=0, OF=0,
SF=1, ZF=0
Time= 4600000, A=0010, B=1101, Cin3=0, S=1111, CF=0, OF=0,
SF=1, ZF=0
Time= 4700000, A=0010, B=1110, Cin3=0, S=0000, CF=1, OF=0,
SF=0, ZF=1
Time= 4800000, A=0010, B=1111, Cin3=0, S=0001, CF=1, OF=0,
SF=0, ZF=0
Time= 4850000, A=0011, B=1111, Cin3=0, S=0010, CF=1, OF=0,
SF=0, ZF=0
Time= 4900000, A=0011, B=0000, Cin3=0, S=0011, CF=0, OF=0,
SF=0, ZF=0
Time= 5000000, A=0011, B=0001, Cin3=0, S=0100, CF=0, OF=0,
SF=0, ZF=0
Time= 5100000, A=0011, B=0010, Cin3=0, S=0101, CF=0, OF=0,
SF=0, ZF=0
Time= 5200000, A=0011, B=0011, Cin3=0, S=0110, CF=0, OF=0,
SF=0, ZF=0
13.

- Eight half adders have been used in the prototype.

- Six lookup tables have been used in the prototype.

- Pico second is the time unit in the simulation.

- There is a 50ps delay between two inputs. The purpose of the delay is to make sure the value of inputs
to the full adders comes one after another. After the first input, the second input is provided with a 50pc
delay.

- Overflow flag indicates that the result is more than the desired output bit. To calculate overflow, we
need to take 2’s complement of inputs and sum them. If it is more than desired output, it is an overflow.
Therefore, there is an overflow after the sum which can be seen in the simulation report. The overflow
flag(OF) shows one (1) when sum is 17 bit.

- The for loop runs from 0 to 15 bit with a nested for loop. Therefore, there is a 256 combination of
inputs.

- Monitor command performs monitoring of inputs(A,B) and other flags(S,CF,OF,ZF) as well as time of
simulation.

- Adder is sensitive to sum because it can generate carry from sum operation.

- Using If-else statement, the time for the simulation can be shortened.