Assignment-2

a) Write a Verilog model of the 4-bit 2-to-1 Multiplexer with the Enable input; if
Enable==1, then a selected input is connected to the output, otherwise the
Multiplexer is in the high-impedance state;
b) Write a Verilog test bench for the multiplexer and expected Simulation
Report.
Solve:
module prob_1(a, b, sel, en, f);
input [3: 0] a, b;
input [2:0] sel;
input en;
output reg f;
always @ (a, b, sel, en)
begin
If(en==1)
Case(sel)
3’b000 : f = a[0];
3’b001 : f = b[0];
3’b010 : f = a[1];
3’b011 : f = b[1];
3’b100 : f = a[2];
3’b101 : f = b[2];
3’b110 : f = a[3];
3’b111 : f = b[3];
endcase
else
f = z;
end
endmodule

Test-Bench:
module test_bench();
reg [3 : 0]a,b ;
reg [2 : 0]sel;
reg en;
wire f;
initial
begin
$monitor($time, a, b, sel, en, f,”simtime = %t, a=%b, b=%b, sel=%b, en=%b”);
#100 $finish
end
prob_1 uut (
.a(a),
.b(b),
.sel(sel),
.en(en),
.f(f));
initial
begin
a = 4’b1111; b = 4’b1111; sel= 3’b000; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b001; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b010; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b011; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b100; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b101; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b110; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b111; en = 1’b1;
a = 4’b1111; b = 4’b1111; sel= 3’b000; en = 1’bz;
end
endmodule

2. Write a Verilog model for the Logic Unit (LU) that performs the following
bitwise
logic operations: AND, OR, XOR, NAND, NOR, XNOR.
LU (operand1, operand2, opcode, result). The operands and result are 8-bit
numbers.
Solve:
module prob_2(a, b, sel, f);
input [7 : 0] a, b;
input [3 : 0] sel;
output reg f;
always @ (a, b, sel);
begin
case(sel)
3’b000 : f = a&b;
3’b001 : f = a|b;
3’b010 : f = a^b;
3’b011 : f = ~(a&b);
3’b100 : f = ~(a|b);
default : f = ~(a^b);
endcase
end
endmodule
Test-Bench:
module test_bench()
reg [7 : 0]a, b;
reg [3 : 0] sel;
wire f;
initial
begin
$monitor($time, a, b, sel, f, ”simtime=%t, a=%b, b=%b, sel=%b, f=%b”);
#100 $finish
end
prob_2 uut(
.a(a),
.b(b),
.sel(sel),
.f(f));
initial
begin
a = 8’b00001111; b = 8’b00011101; sel = 3’b000;
a = 8’b00001111; b = 8’b00011101; sel = 3’b001;
a = 8’b00001111; b = 8’b00011101; sel = 3’b010;
a = 8’b00001111; b = 8’b00011101; sel = 3’b011;
a = 8’b00001111; b = 8’b00011101; sel = 3’b100;
a = 8’b00001111; b = 8’b00011101; sel = 3’b101;
a = 8’b00001111; b = 8’b00011101; sel = 3’b111;
end
endmodule

3. Write a Verilog behavioral description of the following circuit:

1F(A,B,C,D) = m(1,12,15)
Solve:
module prob_3(a, b, c, d, f);
input a, b, c, d;
output f;
assign f = ((~a&b) & (~c&d)) + ((a&~b) & (~c&~d)) + ((a&~b) & (c&d));
endmodule

Test_Bench:
module test_bench();
reg a, b, c, d;
wire f;
initial
begin
$monitor($time, a, b, c, d, f, “simtime =%t, a=%a, b=%b, c=%b, d=%b, f=%b”);
#100 $finish
end
prob_3 uut(
.a(a),
.b(b),
.c(c),
.d(d),
.f(f));
initial
begin
a = 1’b1; b = 1’b1; c = 1’b1; d = 1’b1;
a = 1’b1; b = 1’b0; c = 1’b1; d = 1’b0;
end
endmodule