Nguyễn Trường Duy
Introduction
 An ADC inputs an analog electrical signal
such as voltage or current and outputs a
binary number. In block diagram form, it
can be represented as such:
 A DAC, on the other hand, inputs a
binary number and outputs an analog
voltage or current signal. In block
diagram form, it looks like this:
Introduction
 Together, they are often used in digital systems to provide complete interface with
analog sensors and output devices for control systems such as those used in
automotive engine controls:
 Introduction
 It is much easier to convert a digital signal into an analog signal than it is to do the
reverse. Therefore, we will begin with DAC circuitry and then move to ADC
circuitry.
DAC
 Giả sử DAC 4 bit
DAC
Các mức chuyển đổi như sau:
 Nếu DAC n bit thì
 Số mức chuyển đổi là: 2n
 Số bậc chuyển đổi là: (2n – 1)
𝑉𝐹𝑆 𝐼𝐹𝑆
 Vậy 𝐾 = hoặc 𝐾 =
2𝑛 −1 2𝑛 −1
 Phần trăm độ phân giải
𝐾 1
 𝑅% = 100% = 100%
𝑉𝐹𝑆 2𝑛 −1
DAC
Ví dụ 1: Cho DAC 5 bit ngõ ra điện áp có K = 0,5V. Tìm VFS và phần
trăm độ phân giải
 Solution
VFS =(2n – 1)K =(25 – 1)0,5V = 15,5V
 Phần trăm độ phân giải
1
𝑅% = 100% = 3.23%
25 −1
DAC
 Ví dụ 2: Cho DAC 6 bit ngõ ra điện áp có điện áp ngõ ra là 2V tương ứng
ngõ vào số là 001010B. Tìm ngõ ra Vo khi ngõ vào số là 100100B và VFS
 Solution
001010B = 1010 và 100100B = 3610
K = 2V/10 = 0,2V
Vo = 36.0,2V = 7,2V
VFS = (26 – 1)0,2V = 12,6V
DAC
 Ví dụ 3: Cho DAC n bit ngõ ra điện áp có K = 0,2V. Tìm số bit nhỏ nhất của
DAC để có điện áp ngõ ra Vo = 12V
 Solution
 Số bậc chuyển đổi của Vo là: 12V/0,2V = 60 bậc
 Vậy 2n – 1  60 và n phải là số nguyên
 Kết quả n  6. Vậy số bit nhỏ nhất là 6.
The n
R/2 R DAC
 For a simple inverting summer circuit,
all resistors must be of equal value.
 If any of the input resistors were
different, the input voltages would
have different degrees of effect on the
output, and the output voltage would
not be a true sum.
The n
R/2 R DAC
 Let's consider, however,
intentionally setting the input
resistors at different values.
 Suppose we were to set the
input resistor values at multiple
powers of two: R, 2R, and 4R,
instead of all the same value R
The R/2nR DAC
The n
R/2 R DAC
 If we chart the output voltages for Binary Output voltage
all eight combinations of binary bits 000 0.00 V
(000 through 111) input to this
circuit, we will get the following 001 -1.25 V
progression of voltages: 010 -2.50 V
011 -3.75V
100 -5.00 V
101 -6.25 V
110 -7.50 V
111 -8.75 V
The n
R/2 R DAC
 We can adjust resistors values in this Binary Output voltage
circuit to obtain output voltages directly 000 0.00 V
corresponding to the binary input. For
example, by making the feedback resistor 001 -1.00 V
800 Ω instead of 1 kΩ, the DAC will 010 -2.00V
output -1 volt for the binary input 001, -4
volts for the binary input 100, -7 volts for 011 -3.00V
the binary input 111, and so on. 100 -4.00 V
101 -5.00 V
110 -6.00 V
111 -7.00 V
 The n
R/2 R DAC
 If we wish to expand the resolution of this DAC (add more bits to the input), all we need
to do is add more input resistors, holding to the same power-of-two sequence of values:
The n
R/2 R DAC
 n bit binary-weighted DAC
The R/2nR DAC
 Tìm công thức tính Vo
 Sử dụng phương pháp xếp chồng
𝑅𝐹
 𝑉𝑜0 = − 𝑉 𝐷
2𝑛−1 𝑅 𝑟𝑒𝑓 0
𝑅𝐹
 𝑉𝑜1 = − 𝑛−2 𝑉 𝐷
2 𝑅 𝑟𝑒𝑓 1
 …..
𝑅𝐹
 𝑉𝑜𝑛−2 = − 𝑉 𝐷
21 𝑅 𝑟𝑒𝑓 𝑛−2
𝑅
 𝑉𝑜𝑛−1 = − 0𝐹 𝑉𝑟𝑒𝑓 𝐷𝑛−1
2 𝑅
𝑅𝐹 𝐷0 𝐷1 𝐷𝑛−2 𝐷𝑛−1
 𝑉0 = 𝑉𝑜0 + 𝑉𝑜1 + ⋯ + 𝑉𝑜𝑛−2 + 𝑉𝑜𝑛−1 = − 𝑉𝑟𝑒𝑓 𝑛−1 + + ⋯+ 1 + 0
𝑅 2 2𝑛−2 2 2
The R/2nR DAC
𝑅𝐹 𝐷0 𝐷1 𝐷𝑛−2 𝐷𝑛−1
 𝑉0 = − 𝑉𝑟𝑒𝑓 𝑛−1 + 𝑛−2 + ⋯ + 1 + 0
𝑅 2 2 2 2
𝑅𝐹
 𝑉0 = − 𝑛−1 𝑉𝑟𝑒𝑓 𝐷0 20 + 𝐷1 21 + ⋯ + 𝐷𝑛−2 2𝑛−2 + 𝐷𝑛−1 2𝑛−1
2 𝑅
 Gọi D là giá trị thập phân của ngõ vào số
𝑅𝐹
𝑉0 = − 𝑛−1
𝑉𝑟𝑒𝑓 D
2 𝑅
The R/2nR DAC
Ví dụ: Cho DAC R/2nR 5 bit có Vref = 6V, RF = 2K, R = 5K. Tìm K và VFS
 Solution
 Độ lớn bậc thang là điện áp chênh lệch giữa 2 bậc liền kề
𝑅𝐹 2𝑘
 𝐾 = 𝑉𝑜1 − 𝑉𝑜0 = 𝑛−1 𝑉𝑟𝑒𝑓 . 1 = 5−1 6 = 0,15𝑉
2 𝑅 2 .5𝑘
𝑅𝐹 2𝑘
 𝑉𝐹𝑆 = − 𝑛−1 𝑉𝑟𝑒𝑓 2 − 1 = − 5−1 . 6 25 − 1 =
𝑛
−4.65𝑉
2 𝑅 2 .5𝑘
The R/2R DAC
 An alternative to the binary-weighted-input DAC is the so-called R/2R DAC,
which uses fewer unique resistor values.
 A disadvantage of the former DAC design was its requirement of several
different precise input resistor values: one unique value per binary input bit.
 Manufacture may be simplified if there are fewer different resistor values to
purchase, stock, and sort prior to assembly.
 The R/2R DAC
 Of course, we could take our last DAC circuit and modify it to use a single input
resistance value, by connecting multiple resistors together in series:
The R/2R DAC
 This "ladder" network looks like this:
 The R/2R DAC
Binary Output voltage
 Either way, you should obtain
the following table of figures: 000 0.00 V
001 -1.25 V
010 -2.50 V
011 -3.75V
100 -5.00 V
101 -6.25 V
110 -7.50 V
111 -8.75 V
The R/2R DAC
 DAC R/2R 4 bit
The R/2R DAC

Phương trình nút tại A

1 1 1 𝑉𝐵 𝑉𝑟𝑒𝑓
𝑉𝐴 + + − − 𝐷0 = 0
2𝑅 2𝑅 𝑅 𝑅 2𝑅 Phương trình nút tại C
𝑉𝐵 𝑉𝑟𝑒𝑓 1 1 1 𝑉𝐵 𝑉𝑟𝑒𝑓 𝑉𝐷
𝑉𝐴 = + 𝐷0 𝑉𝐶 + + − − 𝐷2 − =0
2 4 𝑅 2𝑅 𝑅 𝑅 2𝑅 𝑅
Phương trình nút tại B 5 𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓 𝑉𝐶 𝑉𝑟𝑒𝑓
1 1 1 𝑉𝐴 𝑉𝑟𝑒𝑓 𝑉𝐶 𝑉𝐶 = 𝐷0 + 𝐷1 + + 𝐷2 + 𝑉𝐷
𝑉𝐵 + + − − 𝐷1 − =0 2 8 4 2 2
𝑅 2𝑅 𝑅 𝑅 2𝑅 𝑅 𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓 𝑉𝐷
5 𝑉𝐵 𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓 𝑉𝐶 = 𝐷0 + 𝐷1 + 𝐷2 +
𝑉𝐵 = + 𝐷0 + 𝐷1 + 𝑉𝐶 16 8 4 2
2 2 4 2
𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓 𝑉𝐶
𝑉𝐵 = 𝐷0 + 𝐷1 +
8 4 2
The R/2R DAC

1 1 1 𝑉𝐶 𝑉𝑟𝑒𝑓 𝑉𝑜
𝑉𝐷 + + − − 𝐷3 − =0
𝑅 2𝑅 𝑅𝐹 𝑅 2𝑅 𝑅𝐹
 Do: 𝑉𝐷 = 𝑉− = 𝑉+ = 0
𝑉𝑜 𝑉𝑐 𝑉𝑟𝑒𝑓
 Nên =− + 𝐷3
𝑅𝐹 𝑅 2𝑅
𝑉𝑜 𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓 𝑉𝑟𝑒𝑓
 =− 𝐷0 + 𝐷1 + 𝐷2 + 𝐷3
𝑅𝐹 16𝑅 8𝑅 4𝑅 2𝑅
𝑅𝐹 𝐷0 𝐷1 𝐷2 𝐷3
 𝑉𝑜 = − 𝑉𝑟𝑒𝑓 + + +
𝑅 16 8 4 2
The R/2R DAC
𝑅𝐹 𝐷0 𝐷1 𝐷2 𝐷3
 𝑉𝑜 = − 𝑉𝑟𝑒𝑓 + + +
𝑅 16 8 4 2
𝑅𝐹
 𝑉𝑜 = − 4 𝑉𝑟𝑒𝑓 𝐷0 20 + 𝐷1 21 + 𝐷2 22 + 𝐷3 23
2 𝑅
 Gọi D là giá trị thập phân của ngõ vào số
𝑅𝐹
 𝑉𝑜 = − 4 𝑉𝑟𝑒𝑓 D
2 𝑅
 The R/2R DAC
 DAC R/2R n bit

 Công thức tính Vo là:

𝑅𝐹
𝑉𝑜 = − 𝑛 𝑉𝑟𝑒𝑓 D
2 𝑅
DAC ngõ ra dòng điện
 ADC  Vin: điện áp ngõ vào analog
 Sơ đồ khối  Clock: xung nhịp cho hệ thống
 Start: xung lệnh bắt đầu chuyển đổi
 ALE: chốt ngõ vào Vin
 Vref+ và Vref-: điện áp chuẩn, sử dụng
để xác định độ lớn bậc thang và điện áp
ngõ vào Vin
𝑉𝑟𝑒𝑓 (+)−𝑉𝑟𝑒𝑓 (−)
𝐾= , với n là số bit của
2𝑛 −1
ADC
 OE: cho phép xuất dữ liệu ra
 EOC: tín hiệu thông báo chuyển đổi kết
thúc
 D0 ÷ Dn-1: ngõ ra dữ liệu số
ADC
 Sơ đồ cấu trúc bên trong ADC
 Digital ramp ADC
 Also known as the stairstep-ramp,
or simply counter A/D converter,
this is also fairly easy to understand
but unfortunately suffers from
several limitations.
 The basic idea is to connect the
output of a free-running binary
counter to the input of a DAC, then
compare the analog output of the
DAC with the analog input signal to
be digitized and use the
comparator's output to tell the
counter when to stop counting and
reset. The following schematic
shows the basic idea:
 Digital ramp ADC
 Also known as the stairstep-ramp,
or simply counter A/D converter,
this is also fairly easy to understand
but unfortunately suffers from
several limitations.
 The basic idea is to connect the
output of a free-running binary
counter to the input of a DAC, then
compare the analog output of the
DAC with the analog input signal to
be digitized and use the
comparator's output to tell the
counter when to stop counting and
reset. The following schematic
shows the basic idea:
Digital ramp ADC
 Digital ramp ADC
Chuyển đổi sẽ dừng lại khi điện áp ngõ ra DAC
lớn hơn hoặc bằng Vin + VT (với VT là điện áp
ngưỡng của Opamp)
 Thời gian chuyển đổi
𝑇𝐶 = 𝑠ố 𝑏ậ𝑐 𝑥 𝑇𝐶𝑘
 TCk là chu kỳ xung nhịp
 Thời gian chuyển đổi cực đại
𝑇𝐶𝑚𝑎𝑥 = 2𝑛 − 1 𝑥 𝑇𝐶𝑘
 Thời gian chuyển đổi trung bình
𝑇𝐶𝑚𝑎𝑥
𝑇𝐶𝑇𝐵 =
2
Digital ramp ADC
Nếu tín hiệu vào Vin là một tín hiệu AC thì phải lấy mẫu trước khi đưa
vào chuyển đổi

𝑇𝑠𝑎 ≥ 𝑇𝐶𝑚𝑎𝑥
Digital ramp ADC
Digital ramp ADC
 Note how the time between updates (new digital output values) changes depending
on how high the input voltage is. For low signal levels, the updates are rather close-
spaced. For higher signal levels, they are spaced further apart in time:
Digital ramp ADC
 Ví dụ: Cho R-ADC 10 bit có độ lớn bậc thang là 10mV, tần số xung nhịp là
fCk = 100KHz, VT = 8mV
a) Tìm ngõ ra số khi điện áp ngõ vào Vi = 3,487V
b) Tính thời gian chuyển đổi của Vi
c) Nếu cho tần số lấy mẫu tín hiệu fsa = 200KHz. Xác định tần số xung nhịp tối
thiểu cần thiết cho ADC
Digital ramp ADC
 Solution
3,487𝑉
a) Số bậc của Vi là: = 348,7 bậc
10𝑚𝑉
Và Vi + VT = 3,487V + 8mV = 3.495V
Xét bậc 349: VAX = 349 x 10mV = 3,49V < Vi + VT
Xét bậc 350: VAX = 350 x 10mV = 3,50V > Vi + VT
Chuyển đổi sẽ dừng lại tại bậc 350
Kết quả số là 01 0101 1110B
Digital ramp ADC
b) Thời gian chuyển đổi Vi
1 1
Với fCk = 100KHz  𝑇𝐶𝑘 = = = 10𝜇𝑠
𝑓𝐶𝑘 100𝐾𝐻𝑧
TC = 350 x 10s = 3,5ms
Tcmax = (2n – 1)TCk = (210 -1)10s = 10,23ms
1 1
c) fsa = 200KHz  𝑇𝑠𝑎 = = = 5𝜇𝑠
𝑓𝑠𝑎 200𝐾𝐻𝑧
1
Tsa  Tcmax  Tcmax ≤ 5s  2𝑛 −1 ≤ 5𝜇𝑠
𝑓𝐶𝑘
2𝑛 −1
Do đó: 𝑓𝐶𝑘 ≥  𝑓𝐶𝑘 ≥ 204,6𝑀𝐻𝑧
5𝜇𝑠
Vậy tần số xung nhịp nhỏ nhất là: 𝑓𝐶𝑘 = 204,6𝑀𝐻𝑧
Successive approximation ADC
 Without showing the inner
workings of the successive-
approximation register (SAR),
the circuit looks like this:
Successive approximation ADC
Successive approximation ADC
Successive approximation ADC
Ví dụ: Cho SADC 5 bit có kích thước bậc thang K = 0,5V. Hãy vẽ dạng
sóng chuyển đổi khi Vin = 11,2V và Vin = 3,8V
 Solution
- SADC 5 bit nên ta có 25 – 1 = 31 bậc
- K = 0,5V  Vinmax = 15,5V
- Tương ứng các điện áp Vin ta có dạng sóng chuyển đổi như sau:
 Flash ADC
 Also called the parallel A/D converter, this circuit is the simplest to
understand.
 It is formed of a series of comparators, each one comparing the input signal
to a unique reference voltage.
 The comparator outputs connect to the inputs of a priority encoder circuit,
which then produces a binary output.
 The following illustration shows a 3-bit flash ADC circuit:
 Flash ADC
 Vref is a stable reference voltage provided
by a precision voltage regulator as part of
the converter circuit, not shown in the
schematic.
 As the analog input voltage exceeds the
reference voltage at each comparator, the
comparator outputs will sequentially
saturate to a high state.
 The priority encoder generates a binary
number based on the highest-order active
input, ignoring all other active inputs.
 Flash ADC
 When operated, the flash ADC produces an output that looks something like this:
 Flash ADC
 For this particular application, a
regular priority encoder with all its
inherent complexity isn't necessary.
Due to the nature of the sequential
comparator output states (each
comparator saturating "high" in
sequence from lowest to highest),
the same "highest-order-input
selection" effect may be realized
through a set of Exclusive-OR
gates, allowing the use of a simpler,
non-priority encoder:
 Flash ADC
 And, of course, the encoder
circuit itself can be made from a
matrix of diodes, demonstrating
just how simply this converter
design may be constructed:
 Tracking ADC
 A third variation on the counter-DAC-based converter theme is, in my
estimation, the most elegant. Instead of a regular "up" counter driving the DAC,
this circuit uses an up/down counter.
 The counter is continuously clocked, and the up/down control line is driven by
the output of the comparator. So, when the analog input signal exceeds the DAC
output, the counter goes into the "count up" mode.
 When the DAC output exceeds the analog input, the counter switches into the
"count down" mode. Either way, the DAC output always counts in the proper
direction to track the input signal.
Tracking ADC
Tracking ADC
 Notice how no shift register is needed to buffer the binary count at the end of a
cycle. Since the counter's output continuously tracks the input (rather than
counting to meet the input and then resetting back to zero), the binary output is
legitimately updated with every clock pulse.
 An advantage of this converter circuit is speed, since the counter never has to
reset. Note the behavior of this circuit:
Tracking ADC
 Slope (integrating) ADC

 So far, we've only been able to escape the sheer volume of components in the flash
converter by using a DAC as part of our ADC circuitry. However, this is not our only
option. It is possible to avoid using a DAC if we substitute an analog ramping circuit
and a digital counter with precise timing.
 Slope (integrating) ADC
 The is the basic idea behind the so-called single-slope, or integrating ADC.
 Instead of using a DAC with a ramped output, we use an op-amp circuit called an
integrator to generate a sawtooth waveform which is then compared against the
analog input by a comparator.
 The time it takes for the sawtooth waveform to exceed the input signal voltage
level is measured by means of a digital counter clocked with a precise-frequency
square wave (usually from a crystal oscillator).
 Slope (integrating) ADC
 The basic schematic diagram is shown here:
 Slope (integrating) ADC
 The IGFET capacitor-discharging transistor scheme shown here is a bit
oversimplified.
 In reality, a latching circuit timed with the clock signal would most likely have to
be connected to the IGFET gate to ensure full discharge of the capacitor when the
comparator's output goes high.
 The basic idea, however, is evident in this diagram. When the comparator output
is low (input voltage greater than integrator output), the integrator is allowed to
charge the capacitor in a linear fashion.
 Meanwhile, the counter is counting up at a rate fixed by the precision clock
frequency.
 Slope (integrating) ADC
 The time it takes for the capacitor to charge up to the same voltage level as the
input depends on the input signal level and the combination of -Vref, R, and C.
 When the capacitor reaches that voltage level, the comparator output goes high,
loading the counter's output into the shift register for a final output.
 The IGFET is triggered "on" by the comparator's high output, discharging the
capacitor back to zero volts.
 When the integrator output voltage falls to zero, the comparator output switches
back to a low state, clearing the counter and enabling the integrator to ramp up
voltage again.
 Slope (integrating) ADC
 This ADC circuit behaves very much like the digital ramp ADC, except that the
comparator reference voltage is a smooth sawtooth waveform rather than a "stairstep:"