Lab2: MOSFET

This lab guides students in understanding the MOSFET Characteristic. Students will first
simulate and build the MOSFET in LTSpice to gain an understanding of the purpose of a MOSFET.
Then, students will conduct the experiment on the breadboard and testing it with Analog Discovery
II to analyze the Voltage and Current Graph. Finally, students need to design a PCB which is used to
control a DC Motor

I. Introduction
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a type of transistor that is
widely used in electronic devices and integrated circuits for switching and amplifying signals. It
belongs to the family of field-effect transistors (FETs) and is a fundamental building block in
modern electronic circuits. The MOSFET has several advantages, including high switching speeds,
compact size, and relatively low power consumption, making it an essential component in digital
and analog applications.

II. Learning Objective

In this section, students will learn:
• Understand the Transient and DC Sweep of the MOSFET
• Simulate the MOSFET in LTSpice with current graph Analysis
 • Building a MOFET on Breadboard
• Use Diligent Waveform and Analog Discovery II to view the graph of the mosfet
• Using Kicad to design a PCB
III. Equipment
The following equipment is required for the experiment
Hardware
• MOSFET
• Resistor
• Breadboard
• Analog Discovery II
• Jumper Wire
Software
• LTSpice
• Diligent Waveform
• Kicad
IV. Circuit Simulation
Using LTSpice to create a circuit as shown in the image below by using the MOSFET (IRF530)
and value of R1 is 1000 and R2 is 50.

• Transient Analysis
 1. Let V1 equals 3V and V2 is 10V, show the voltage and current graph across R2.
2. Let V1 equals 5V and V2 is 10V, show the voltage and current graph across R2.
3. Explain Both Graph above

• DC Sweep

4. Set V1 to the 1st source and the initial voltage is 0V and the stop value is 10V with the
increment of 0.1. Set V2 is the 2nd source and start the value from 0 to 10V with the
increment of 1. Show the Graph and Explain.
• Pulse

5. Generate pulse signal V1 with initial 0V and Von 5V with the frequency of 2kHz and
duty cycle 50%. Set V2 to 20V. Show the input and output graph of the voltage and
current. Explain the graph?
V. Building and Measure
Using the analog discovery II to determine the output current vs. Voltage (𝐼𝐷 𝑣𝑠 𝑉𝐷𝑆 ) curve of
the N-channel MOSFETS IRF840B

1. Using the Function Generator 1 to generates the stairs waveform, open up an Excel file
and insert the number 1, 2, 3, 4, 5, and 6 in six rows. The excel file should be saved with
file extension .csv or .txt. Open the Arbitrary Waveform Generator, AWG1. Go to
Custom →File → Select source file →Import data in source file with the extension.csv or
.txt → Frequency (set to 10 Hz, frequency is the buffer iteration frequency, and 10 Hz
means the whole stair sequence takes 100 ms) →Amplitude (set to 1.5 V) Offset (set to
2.5 V) → Symmetry (set to 50%)
 2. Function Generator 2 generates drain voltage, VDD. The triangular waveform is made to
range from 0 to 5 V. Each ramp generates an I–V curve for a specific value of the gate
voltage. The triangular waveform is generated through the following commands: Click on
the WaveGen in the main WaveForms screen. Go to Basic → Triangular → Frequency
(set to 50 Hz) → Amplitude (set to 2.5 V) → Offset (set to 2.5 V) → Symmetry (set to
50%).

3. Using Scope 1 to measure the 𝑉𝐷𝑆 and use scope 2 to measure the current across R1.
Show the output current vs. Voltage graph (𝐼𝐷 𝑣𝑠 𝑉𝐷𝑆 ) curve of the N-channel MOSFETS
IRF840B and explain

VI. PCB Design

Design the PCB using N-Channel Mosfet as shown in the image below

Group1: choose R=50Ω

Group2: choose R=100Ω
Group3: choose R=150Ω
Group4: choose R=200Ω
Group5: choose R= 300Ω
 IRF530
www.vishay.com
Vishay Siliconix
Power MOSFET
D
FEATURES
• Dynamic dV/dt rating
TO-220AB
• Repetitive avalanche rated Available

• 175 °C operating temperature Available

G • Fast switching
• Ease of paralleling Available

S
• Simple drive requirements
D • Material categorization: for definitions of compliance
G S
please see www.vishay.com/doc?99912
N-Channel MOSFET
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
PRODUCT SUMMARY example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
VDS (V) 100
RDS(on) (Ω) VGS = 10 V 0.16 DESCRIPTION
Qg max. (nC) 26 Third generation power MOSFETs from Vishay provide the
Qgs (nC) 5.5 designer with the best combination of fast switching,
Qgd (nC) 11 ruggedized device design, low on-resistance and
cost-effectiveness.
Configuration Single
The TO-220AB package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 W. The low thermal resistance
and low package cost of the TO-220AB contribute to its
wide acceptance throughout the industry.

ORDERING INFORMATION
Package TO-220AB
Lead (Pb)-free IRF530PbF
Lead (Pb)-free and halogen-free IRF530PbF-BE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 100
V
Gate-source voltage VGS ± 20
TC = 25 °C 14
Continuous drain current VGS at 10 V ID
TC = 100 °C 10 A
Pulsed drain current a IDM 56
Linear derating factor 0.59 W/°C
Single pulse avalanche energy b EAS 69 mJ
Repetitive avalanche current a IAR 14 A
Repetitive avalanche energy a EAR 8.8 mJ
Maximum power dissipation TC = 25 °C PD 88 W
Peak diode recovery dV/dt c dV/dt 5.5 V/ns
Operating junction and storage temperature range TJ, Tstg -55 to +175
°C
Soldering recommendations (peak temperature) d For 10 s 300
10 lbf · in
Mounting torque 6-32 or M3 screw
1.1 N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 528 μH, Rg = 25 Ω, IAS = 14 A (see fig. 12)
c. ISD ≤ 14 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
d. 1.6 mm from case

S21-0819-Rev. C, 02-Aug-2021 1 Document Number: 91019

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF530
www.vishay.com
Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient RthJA - 62
Case-to-sink, flat, greased surface RthCS 0.50 - °C/W
Maximum junction-to-case (drain) RthJC - 1.7

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 100 - - V
VDS temperature coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = 100 V, VGS = 0 V - - 25
Zero gate voltage drain current IDSS μA
VDS = 80 V, VGS = 0 V, TJ = 150 °C - - 250
Drain-source on-state resistance RDS(on) VGS = 10 V ID = 8.4 A b - - 0.16 Ω
Forward transconductance gfs VDS = 50 V, ID = 8.4 A b 5.1 - - S
Dynamic
Input capacitance Ciss - 670 -
VGS = 0 V,
Output capacitance Coss VDS = 25 V, - 250 - pF
f = 1.0 MHz, see fig. 5
Reverse transfer capacitance Crss - 60 -
Total gate charge Qg - - 26
ID = 14 A, VDS = 80 V,
Gate-source charge Qgs VGS = 10 V - - 5.5 nC
see fig. 6 and 13 b
Gate-drain charge Qgd - - 11
Turn-on delay time td(on) - 10 -
Rise time tr VDD = 50 V, ID = 14 A - 34 -
ns
Turn-off delay time td(off) Rg = 12 Ω, RD = 3.6 Ω, see fig. 10 b - 23 -
Fall time tf - 24 -
Gate input resistance Rg f = 1 MHz, open drain 1.0 - 4.7 Ω
Between lead, D
Internal drain inductance LD - 4.5 -
6 mm (0.25") from
package and center of G
nH
Internal source inductance LS die contact - 7.5 -
S

Drain-Source Body Diode Characteristics

MOSFET symbol
Continuous source-drain diode current IS D
- - 14
showing the
integral reverse G
A
Pulsed diode forward current a ISM p - n junction diode S
- - 56

Body diode voltage VSD TJ = 25 °C, IS = 14 A, VGS = 0 Vb - - 2.5 V

Body diode reverse recovery time trr - 150 280 ns
TJ = 25 °C, IF = 14 A, dI/dt = 100 A/μs b
Body diode reverse recovery charge Qrr - 0.85 1.7 μC
Forward turn-on time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %

S21-0819-Rev. C, 02-Aug-2021 2 Document Number: 91019

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF530
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

RDS(on), Drain-to-Source On Resistance

VGS 3.5
ID = 14 A
Top 15 V VGS = 10 V
10 V 3.0
8.0 V
7.0 V
ID, Drain Current (A)

6.0 V 2.5
5.5 V

(Normalized)
101 5.0 V
Bottom 4.5 V 2.0

1.5

4.5 V 1.0
100
20 µs Pulse Width 0.5
TC = 25 °C
0.0
10-1 100 101 - 60- 40 - 20 0 20 40 60 80 100 120 140 160 180
91019_01 VDS, Drain-to-Source Voltage (V) 91019_04 TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature

VGS 1400
VGS = 0 V, f = 1 MHz
Top 15 V Ciss = Cgs + Cgd, Cds Shorted
10 V 1200
Crss = Cgd
8.0 V Coss = Cds + Cgd
ID, Drain Current (A)

7.0 V 1000
Capacitance (pF)

101 6.0 V
5.5 V Ciss
5.0 V 800
Bottom 4.5 V
4.5 V 600
Coss
400
100
200 Crss
20 µs Pulse Width
TC = 175 °C
0
10-1 100 101 100 101
91019_02 VDS, Drain-to-Source Voltage (V) 91019_05 VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics, TC = 175 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

20
ID = 14 A
VGS, Gate-to-Source Voltage (V)

25 °C
VDS = 80 V
175 °C 16
ID, Drain Current (A)

101 VDS = 50 V

12 VDS = 20 V

8
100

4
20 µs Pulse Width For test circuit
VDS = 50 V see figure 13
0
4 5 6 7 8 9 10 0 5 10 15 20 25
91019_03 VGS, Gate-to-Source Voltage (V) 91019_06 QG, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S21-0819-Rev. C, 02-Aug-2021 3 Document Number: 91019

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF530
www.vishay.com
Vishay Siliconix

RD
VDS
ISD, Reverse Drain Current (A)

VGS
D.U.T.
RG
+
101 175 °C - VDD

25 °C 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

100

VGS = 0 V
VDS
0.4 0.8 1.2 1.6 2.0
90 %
91019_07 VSD, Source-to-Drain Voltage (V)

Fig. 7 - Typical Source-Drain Diode Forward Voltage

10 %
VGS
103 td(on) tr td(off) tf
5
Operation in this area limited
2 by RDS(on)
Fig. 10b - Switching Time Waveforms
102
ID, Drain Current (A)

5 10 µs
2
100 µs
10 1 ms
5
10 ms
2

1
5
TC = 25 °C
2
TJ = 175 °C
Single Pulse
0.1
2 5 2 5 2 5 2 5
0.1 1 10 102 103

91019_08 VDS, Drain-to-Source Voltage (V)

Fig. 8 - Maximum Safe Operating Area

14

12
ID, Drain Current (A)

10

0
25 50 75 100 125 150 175

91019_09 TC, Case Temperature (°C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

S21-0819-Rev. C, 02-Aug-2021 4 Document Number: 91019

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF530
www.vishay.com
Vishay Siliconix

Thermal Response (ZthJC) 10

1 0 - 0.5

0.2 PDM
0.1
0.1 0.05 t1
0.02 Single Pulse t2
0.01 (Thermal Response) Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1 10

91019_11 t1, Rectangular Pulse Duration (s)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

L VDS
VDS
Vary tp to obtain tp
required IAS VDD
RG D.U.T +
V DD
- VDS
IAS
10 V
tp 0.01 Ω
IAS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

200
ID
Top
EAS, Single Pulse Energy (mJ)

5.7 A
160 9.9 A
Bottom 14 A

120

80

40

VDD = 25 V
0
25 50 75 100 125 150 175

91019_12c Starting TJ, Junction Temperature (°C)

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

S21-0819-Rev. C, 02-Aug-2021 5 Document Number: 91019

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF530
www.vishay.com
Vishay Siliconix

Current regulator
Same type as D.U.T.

QG 50 kΩ
10 V 12 V 0.2 µF
0.3 µF

QGS QGD +
VDS
D.U.T. -

VG
VGS

3 mA

Charge
IG ID
Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91019.

S21-0819-Rev. C, 02-Aug-2021 6 Document Number: 91019

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.

Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

© 2023 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED

Revision: 01-Jan-2023 1 Document Number: 91000

 IRF840B/IRFS840B
November 2001

IRF840B/IRFS840B
500V N-Channel MOSFET

General Description Features

These N-Channel enhancement mode power field effect • 8.0A, 500V, RDS(on) = 0.8Ω @VGS = 10 V
transistors are produced using Fairchild’s proprietary, • Low gate charge ( typical 41 nC)
planar, DMOS technology. • Low Crss ( typical 35 pF)
This advanced technology has been especially tailored to • Fast switching
minimize on-state resistance, provide superior switching • 100% avalanche tested
performance, and withstand high energy pulse in the • Improved dv/dt capability
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies,
power factor correction and electronic lamp ballasts based
on half bridge.

G
TO-220 TO-220F
G DS GD S
IRF Series IRFS Series
S

Absolute Maximum Ratings TC = 25°C unless otherwise noted

Symbol Parameter IRF840B IRFS840B Units

VDSS Drain-Source Voltage 500 V
ID Drain Current - Continuous (TC = 25°C) 8.0 8.0 A
- Continuous (TC = 100°C) 5.1 5.1 A
IDM Drain Current - Pulsed (Note 1) 32 32 A
VGSS Gate-Source Voltage ± 30 V
EAS Single Pulsed Avalanche Energy (Note 2) 320 mJ
IAR Avalanche Current (Note 1) 8.0 A
EAR Repetitive Avalanche Energy (Note 1) 13.4 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 3.5 V/ns
PD Power Dissipation (TC = 25°C) 134 44 W
- Derate above 25°C 1.08 0.35 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
TL 300 °C
1/8" from case for 5 seconds
* Drain current limited by maximum junction temperature.

Thermal Characteristics
Symbol Parameter IRF840B IRFS840B Units
RθJC Thermal Resistance, Junction-to-Case Max. 0.93 2.86 °C/W
RθCS Thermal Resistance, Case-to-Sink Typ. 0.5 -- °C/W
RθJA Thermal Resistance, Junction-to-Ambient Max. 62.5 62.5 °C/W

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Electrical Characteristics TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 500 -- -- V
∆BVDSS Breakdown Voltage Temperature
ID = 250 µA, Referenced to 25°C -- 0.55 -- V/°C
/ ∆TJ Coefficient
IDSS VDS = 500 V, VGS = 0 V -- -- 10 µA
Zero Gate Voltage Drain Current
VDS = 400 V, TC = 125°C -- -- 100 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteristics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2.0 -- 4.0 V
RDS(on) Static Drain-Source
VGS = 10 V, ID = 4.0 A -- 0.65 0.8 Ω
On-Resistance
gFS Forward Transconductance VDS = 40 V, ID = 4.0 A (Note 4) -- 7.3 -- S

Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V, -- 1400 1800 pF
Coss Output Capacitance f = 1.0 MHz -- 145 190 pF
Crss Reverse Transfer Capacitance -- 35 45 pF

Switching Characteristics
td(on) Turn-On Delay Time -- 22 55 ns
VDD = 250 V, ID = 8.0 A,
tr Turn-On Rise Time -- 65 140 ns
RG = 25 Ω
td(off) Turn-Off Delay Time -- 125 260 ns
(Note 4, 5)
tf Turn-Off Fall Time -- 75 160 ns
Qg Total Gate Charge VDS = 400 V, ID = 8.0 A, -- 41 53 nC
Qgs Gate-Source Charge VGS = 10 V -- 6.5 -- nC
Qgd Gate-Drain Charge (Note 4, 5) -- 17 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain-Source Diode Forward Current -- -- 8.0 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 32 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 8.0 A -- -- 1.4 V
trr Reverse Recovery Time VGS = 0 V, IS = 8.0 A, -- 390 -- ns
Qrr Reverse Recovery Charge dIF / dt = 100 A/µs (Note 4)
-- 4.2 -- µC

Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 9.0mH, IAS = 8.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 8.0A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Typical Characteristics

VGS
Top : 15.0 V
10.0 V
8.0 V
1 7.0 V 1
10 10
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
ID, Drain Current [A]

ID, Drain Current [A]

o
150 C

0 0
10 10
o
25 C
o
※ Notes :
-55 C ※ Notes :
1. 250μ s Pulse Test 1. VDS = 40V
2. TC = 25℃ 2. 250μ s Pulse Test

-1 -1
10 10
10
-1
10
0
10
1 2 4 6 8 10

VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V]

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

3.0

1
2.5 10
Drain-Source On-Resistance

VGS = 10V
IDR, Reverse Drain Current [A]
RDS(ON) [Ω ],

2.0
VGS = 20V

0
1.5 10

150℃ 25℃
1.0 ※ Notes :
1. VGS = 0V
※ Note : TJ = 25℃ 2. 250μ s Pulse Test

-1
0.5 10
0 5 10 15 20 25 30 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
ID, Drain Current [A] VSD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs Figure 4. Body Diode Forward Voltage

Drain Current and Gate Voltage Variation with Source Current
and Temperature

3000 12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
VDS = 100V
2500 10
VDS = 250V
VGS, Gate-Source Voltage [V]

2000 8 VDS = 400V

Ciss
Capacitance [pF]

1500 6

1000
Coss 4
※ Notes :
1. VGS = 0 V
Crss 2. f = 1 MHz
500 2
※ Note : ID = 8.0 A

0 0
10
-1 0
10 10
1 0 5 10 15 20 25 30 35 40 45

VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC]

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Typical Characteristics (Continued)

1.2 3.0

2.5
Drain-Source Breakdown Voltage

1.1

Drain-Source On-Resistance
BV DSS , (Normalized)

RDS(ON) , (Normalized)
2.0

1.0 1.5

1.0

0.9 ※ Notes :
1. VGS = 0 V
※ Notes :
2. ID = 250 μ A 0.5 1. VGS = 10 V
2. ID = 4.0 A

0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
o o
TJ, Junction Temperature [ C] TJ, Junction Temperature [ C]

Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation

vs Temperature vs Temperature

2
10 Operation in This Area
2 Operation in This Area is Limited by R DS(on)
10 is Limited by R DS(on)

100 µs
10 µs 10
1

1
100 µs 1 ms
10
1 ms 10 ms
ID, Drain Current [A]

ID, Drain Current [A]

10 ms 100 ms
DC 0 DC
0
10
10

-1
-1
※ Notes : 10 ※ Notes :
10
o o
1. TC = 25 C 1. TC = 25 C
o o
2. TJ = 150 C 2. TJ = 150 C
3. Single Pulse 3. Single Pulse
-2 -2
10 10
0 1 2 3 0 1 2 3
10 10 10 10 10 10 10 10
VDS, Drain-Source Voltage [V]
VDS, Drain-Source Voltage [V]

Figure 9-1. Maximum Safe Operating Area Figure 9-2. Maximum Safe Operating Area
for IRF840B for IRFS840B

10

8
ID, Drain Current [A]

0
25 50 75 100 125 150
TC, Case Temperature [℃]

Figure 10. Maximum Drain Current

vs Case Temperature

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Typical Characteristics (Continued)

(t), T h e r m a l R e s p o n s e
0
10

D = 0 .5
※ N o te s :
1 . Z θ J C (t) = 0 .9 3 ℃ /W M a x .
0 .2 2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C (t)

10
-1
0 .1

0 .0 5

0 .0 2
PDM
θ JC

0 .0 1 t1
Z

s in g le p u ls e t2
-2
10

-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11-1. Transient Thermal Response Curve for IRF840B

(t), T h e r m a l R e s p o n s e

D = 0 .5
0
10

0 .2 ※ N o te s :
1 . Z θ J C (t) = 2 .8 6 ℃ /W M a x .
0 .1 2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C (t)

0 .0 5
-1
10
0 .0 2 PDM
θ JC

0 .0 1
t1
Z

t2
s in g le p u ls e
-2
10
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11-2. Transient Thermal Response Curve for IRFS840B

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Gate Charge Test Circuit & Waveform

VGS
Same Type
50KΩ
as DUT Qg
12V 200nF
300nF 10V
VDS
VGS Qgs Qgd

DUT
3mA

Charge

Resistive Switching Test Circuit & Waveforms

RL VDS
VDS 90%

VGS VDD
RG

10%
VGS
10V DUT
td(on) tr td(off)
tf
t on t off

Unclamped Inductive Switching Test Circuit & Waveforms

L BVDSS
1
VDS EAS = ---- L IAS2 --------------------
2 BVDSS - VDD
BVDSS
ID
IAS
RG
VDD ID (t)

10V DUT VDD VDS (t)

tp
tp Time

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT +

VDS

I SD
L

Driver
RG
Same Type
as DUT VDD

VGS • dv/dt controlled by RG

• ISD controlled by pulse period

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

IFM , Body Diode Forward Current

I SD
( DUT ) di/dt

IRM

Body Diode Reverse Current

VDS
( DUT ) Body Diode Recovery dv/dt

VSD VDD

Body Diode
Forward Voltage Drop

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Package Dimensions

TO-220
9.90 ±0.20 4.50 ±0.20
1.30 ±0.10

(8.70)

2.80 ±0.10
(1.70)

+0.10
ø3.60 ±0.10 1.30 –0.05

18.95MAX.
(3.70)

15.90 ±0.20
9.20 ±0.20

(1.46)

(3.00)
(45°
)
(1.00)
13.08 ±0.20

10.08 ±0.30

1.27 ±0.10 1.52 ±0.10

0.80 ±0.10 +0.10

0.50 –0.05 2.40 ±0.20
2.54TYP 2.54TYP
[2.54 ±0.20] [2.54 ±0.20]

10.00 ±0.20

Dimensions in Millimeters

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 IRF840B/IRFS840B
Package Dimensions (Continued)

3.30 ±0.10 TO-220F

10.16 ±0.20 ø3.18 ±0.10 2.54 ±0.20
(7.00) (0.70)

6.68 ±0.20

15.87 ±0.20
15.80 ±0.20

(1.00x45°)

MAX1.47
9.75 ±0.30

0.80 ±0.10
(3
0°
)

#1
0.35 ±0.10 +0.10
0.50 –0.05 2.76 ±0.20
2.54TYP 2.54TYP
[2.54 ±0.20] [2.54 ±0.20]
4.70 ±0.20

9.40 ±0.20

Dimensions in Millimeters

©2001 Fairchild Semiconductor Corporation Rev. A, November 2001

 TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.

ACEx™ FAST® OPTOLOGIC™ SMART START™ VCX™

Bottomless™ FASTr™ OPTOPLANAR™ STAR*POWER™
CoolFET™ FRFET™ PACMAN™ Stealth™
CROSSVOLT™ GlobalOptoisolator™ POP™ SuperSOT™-3
DenseTrench™ GTO™ Power247™ SuperSOT™-6
DOME™ HiSeC™ PowerTrench® SuperSOT™-8
EcoSPARK™ ISOPLANAR™ QFET™ SyncFET™
E2CMOS™ LittleFET™ QS™ TruTranslation™
EnSigna™ MicroFET™ QT Optoelectronics™ TinyLogic™
FACT™ MicroPak™ Quiet Series™ UHC™
FACT Quiet Series™ MICROWIRE™ SLIENT SWITCHER® UltraFET®

STAR*POWER is used under license

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

©2001 Fairchild Semiconductor Corporation Rev. H4