28nm

CMOS Mixed Design Kit

TWEPP 2020 – Micro-Electronics User Group meeting

22nd September 2020
Alessandra Fioriti
Alessandro Caratelli
Kostas Kloukinas
Gert Olesen
Wojciech Bialas
 28nm Design Kit: Overview

TSMC 28nm Mixed Signal Kit:

• Bare PDK
• Digital libraries
• Physical views available

Main advantages and novelties:

• Incremental PDK
• Workflow

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 28nm Common Design Platform
TSMC 28nm Mixed Signal Kit:
• PDK Foundry
• Digital libraries with physical view PDK Digital
Libraries
 Integration through ITDB method
• Mixed signal kit: support analog and digital designs ITDB
• Workflow: Mixed signal
kit
 Compatible across multiple design nodes
 Validated though Cadence EDA tools
Workflow
• Common Design Platform:
 Development “user-friendly” environment
 It supports collaborative work
compatibility within the design flow and the design itself Common Design
Platform

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 28 nm technology advantages
• Smaller, faster, more advanced technology
• Promising radiation results!
 Spacers impact on performance degradation under radiation is negligible in this technology

Courtesy of G. Borghello
EP-ESE-ME

Minimum size devices 1 Grad 1 Grad

https://asicsupport-community.web.cern.ch/t/ionizing-radiation-effects-on-28nm-cmos-technology/185
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 TSMC 28 PDK

PDK Technology Options:

Europractice mini@sic runs
28nm HPC, All FEOL technology options
Metal scheme: 1P8M_5X1Z1U + UTRDL

Prototyping through Europractice

https://europractice-ic.com/mpw-prototyping/asics/tsmc/
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 28nm Design Kit: Incremental PDK
Method for merging the PDK tech file with the digital libraries tech file
ITDB (Incremental Technology Database) method:
Digital libraries integration can be done easily and incrementally

No need to modify the PDK

tech file to be consistent with
digital libraries LEF

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 28nm Design Kit: digital libraries

142 libraries available!

Thanks to IMEC

Libraries in the PDK

Bond pad and I/O libraries

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 28nm Design Kit: digital libraries
tcbn28hpcbwp35p140
30 nm
35 nm Gate length
40 nm

Poly pitch
9 , 12 Tracks
140nm

140nm
I Z
SVT, LVT, HVT,
Voltage threshold
UHVT, ULVHT

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 28nm libraries corners

slow
typical Process Corners
fast -40 °C
0 °C Temperature
85 °C
0.88 V 125 °C
0.99 V Vnom + 10%
1.05 V
0.72 V Voltage
0.81 V Vnom - 10% Digital libraries for level
0.9 V Vnom translators available
1.0 V

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 28nm Design Platform

• Optimizations and improvements after testing the design kit with small analog
and digital design
 spice models included into a toplevel file to support corner and Montecarlo analog
simulations
• Front end and layout views added for the digital libraries
• Single/Dual port SRAMs available
• The design platform supports PVS tool
• DRC and LVS deck for Calibre added in the PDK

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 28nm Digital Workflow

Digital flow is under development:

• Based on the “Generic Flow” of other technologies (130nm, 65nm)

• Co-development with Cadence VCAD
• Use of GENUS/INNOVUS Cadence platforms
• Based on Cadence Stylus Flowkit
• New sign-off commands introduced to support advanced nodes technology
parasitic accuracy improvement, reserved space for multi-cut vias, DFM checks …
• Physical aware synthesis and other advanced features

Beta-testing: Design flow validation in small scale designs

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 28nm Design Kit

• Libraries integrated in the PDK: physical views available

• Workflow under development focused on advanced nodes requirements
• Continuous update of technology files

The Design Kit is in place for beta-testing

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