VLSI Design

Objective Type Questions

Chapter 1

Introduction to EDA tool and VHDL programming:

1 Std-logic is a …… valued logic system.
A) 2 B) 4
C) 8 D) 9
2 If A= ‘110’ , B = ‘111’ then A & Not B is ……….
A) 110111 B) 100111
C) 110000 D) None of the above
3 The block of the code which defines the input and output in VHDL design is the
A) Architecture B) Package
C) Entity D) Library
4 Process in VHDL becomes active, when
A) Change in clock statement B) There is change in value of signal in sensitivity
list
C) Change in reset signal D) None of the above
5 In an entity statement buffer is
A) Signal type B) Signal port
C) Signal mode D) concurrent
6 The symbol ………… is the signal assignment operator.
A) := B) <=
C) => D) None of the above
7 In std-logic forcing unknown is represented by ……….
A) Z B) U
C) W D) X
8 As per IEEE 1164 standard WE represents …………
A) Forcing unknown B) High Impedance
C) Weak unknown D) Weak ‘1’
9 Process statement itself is ……..
A) Concurrent B) Sequential
C) Mixed mode D) Generics
10 In VHDL module entity describes ………. Mode of signals.
A) Input B) Output
C) Bidirectional D) All of the above
11 In VHDL code ** represents a ………
A) MOD operator B) Reminder Operator
C) Exponentiation D) Absolute value
12 One dimensional array of bit signals is referred to as ………..
A) Bit B) Boolean-vector
C) Bit-vector D) None of the above
13 A process cannot have …………
A) Wait statement B) Sensitivity list
C) Wait statement & Sensitivity list D) None of the above
simultaneously
14 Variables in VHDL can be used in ……….
A) Process B) Procedure
C) Function D) All of above
15 Which of the following is not a VHDL object data?
A) Signal B) Variable
C) Wire D) Constant
16 The first character in a basic identifier is ……………..
A) Underscore B) Digit
C) Letter D) None of the above
17 In VHDL code, statements that are placed inside a/an ………….. are executed sequentially.
A) Entity B) Procedure
C) Process D) Function
18 Which VHDL data type can only have a value of ‘1’ or ‘0’?
A) Signal B) Bit
C) Std-logic D) Integar
19 Effect of logic propagation delays can be modelled as
A) Inertial delay model B) Transport delay model
C) Delta delay model D) Any one of the above would serve the purpose
20 VHDL provides some special statements such as ………….. to aid in the testing and validation
process.
A) Component statement B) Assert, report, severity
C) Generate statement D) None of the above
21 The use of the look ahead carry in parallel adder is that it …….. speed.
A) Delays B) Keep constant
C) Improves D) Reduces
22 The EX-ORing of even number is always ………….
A) One B) Ten
C) Zero D) Odd
23 A full adder circuit can be implemented by using ………….
A) One suitable Multiplexer B) Two suitable Multiplexers
C) Cannot be implemented using D) Only Decoders
Multiplexer
24 A 2:1 MUX is equivalent to a ………….
A) NAND gate B) NOR gate
C) AND gate D) OR gate
25 Implementation of full Subtractor circuit using decoder with active low outputs need ……..
A) 3:8 decoder along with NOR gate B) 1:8 decoder along with XOR gate
C) 3:8 decoder along with NAND gate D) 3:8 decoder along with AND gate
26 Which of the following input condition convert J-K flip/flop into D flip/flop.
A) J=0, K=1 B) J=1, K=1
C) J=0, K=0 D) J=1, K=0
27 The parallel data on shift register is 1000. After shifting the data to the right two times, the input
data will be …………
A) Divided by 4 B) Divided by 2
C) Multiplied by 4 D) Multiplied by 2
28 The output of a MOD-2 counter given as a clock input of a MOD-5 counter gives …………
A) MOD-5 counter B) MOD-10 Counter
C) MOD-25 Counter D) None of the above
29 The problem of a clock skew occurs in …………….
A) Gates B) Universal gate
C) Sequential circuits D) Combinational circuit
30 The D latch behaves as a ……..
A) Frequency Multiplier B) Frequency divider
C) Frequency adder D) None of the above
31 If a port is declared as buffer, then which p
roblem is generated in hierarchical design due to mapping with port of buffer mode
of other entities only?
A) Structural Modeling B) Functional Modeling
C) Behavioral Modeling D) Data Flow Modeling
32 Which among the following wait statement execution causes the enclosing process to
suspend and then wait for an event to occur on the signals?
A) Wait until Clk = '1' B) Wait on x,y,z
C) Wait on clock until answer > 80 D) Wait for 12 ns
33 In composite data type of VHDL, the record type comprises the elements of
_______data types.
A) Same B) Different
C) Both a and b D) None of the above
34 Which among the following is pre-defined in the standard package as one-
dimensional array type comprising each element of BIT type?
A) Bit type B) Bit_vector type
C) Boolean type D) All of the above
35 In VHDL, which class of scalar data type represents the values necessary for a
specific operation?
A) Integer types B) Real types
C) Physical types D) Enumerated types
36 Which among the following is an output generated by synthesis process?
A) Attributes & Library B) RTL VHDL description
C) Circuit constraints D) Gate-level net list
37 Which data type in VHDL is non synthesizable & allows the designer to model the
objects of dynamic nature?
A) Scalar B) Access
C) Composite D) File
38 In VHDL, which object/s is/are used to connect entities together for the model
formation?
A) Constant B) Variable
C) Signal D) All of the above
39 The RANGE keyword is associated with
A) Bit_vector B) Std _logic
C) Integer D) Buffer
40 Which of the following invalid identifier in VHDL?
A) Decoder_8 B) _What_0
C) Invalid D) All are valid
41
In std_Iogic forcing unknown is represented by
A) 'Z' B) 'U'
C) 'W' D) 'X'
42 The concurrent statement is
A) If-else B) Loop
C) When-else D) Case
43 The block of code which defines the relationship between input, output and internal
signals or variables in VHDL design is the
A) Architecture B) Package
C) Entity D) Library
44 In an entity statement buffer is
A) signal type B) signal port
C) signal mode D) concurrent statement
45 The symbol --------------- is the signal assignment operator.
A) := B) <=
C) => D) none of above
46 Multi-dimensional array types are known as
A) record B) Array
C) matrices D) None of above
47 VHDL provides some special statements such as…………..to aid in the testing and
Validationprocess.
A) component statement B) assert, report, severity
C) generate statement D) none of above
48 Process cannot have ………
A) wait statement B) wait statement & sensitivity list
C) sensitivity list D) none of above
 Chapter 2

VHDL modules for Sequential Logic and state machines

1 Timing analysis is more efficient with synchronous systems whose maximum
operating frequency is evaluated by the _________path delay between consecutive
flip-flops.
A) shortest B) Average
C) longest D) Unpredictable
2 An Assert is ______ command.
A) Sequential B) Concurrent
C) Both a and b D) None of the above
3 The 'next' statements skip the remaining statement in the ________ iteration of loop
and execution starts from first statement of next iteration of loop.
A) Previous B) Next
C) Current (present) D) None of the above
5 Which among the following is/are regarded as the function/s of translation step in
synthesis process?
A) Conversion of RTL description to B) Conversion of an unoptimized to optimized
booleanunoptimized description boolean description
C) Conversion of unoptimizedboolean D) All of the above
description to PLA format
6 Which functions are performed by static timing analysis in simulation?
A) Computation of delay for each timing B) Logic analysis in a static manner
path
C) Both a and b D) None of the above
7 An event is nothing but ______ target signal, which is to be updated.
A) Fixed B) Change on
C) Both a and b D) None of the above
8 After an initialization phase, the simulator enters the ______phase.
A) Compilation B) Elaboration
C) Execution D) None of the above
9 Register transfer level description specifies all of the registers in a design & ______
logic between them.
A) Sequential B) Combinational
C) Both a and b D) None of the above
10 ________ complementation is used performing BCD subtraction.
A) One's B) Eight's
C) Two's D) Nine's
11 Std-logic is a valued logic system.
A) 2 B) 8
C) 4 D) 9
12 Process in VHDL becomes active, when
A) change in clock statement B) there is change in value of signal in
sensitivity list
C) change in reset signal D) none of above
13 Process statement itself is …………………
A) Concurrent B) Sequential
C) Mixed mode D) Generics
14 In VHDL module entity describes………………..mode of signals
A) Input B) Bidirectional
C) Output D) All of above
15 When an iterative array of identical components is required, the
……….Statementprovides an easy way of instantiating these components.
A) Port map B) For loop
C) Generate D) None of above
16 In a VHDL code ** represents a (7-5-13)
A) MOD operator B) Reminder operator
C) Exponentiation D) Absolute value
17 One dimensional array of bit signals is referred to as
A) Bit B) Boolean-vector
C) Bit-vector D) None of the above
18 A process can-not have
A) Wait statement B) Sensitivity list
C) Wait statement & sensitivity list D) None of above
19 Variables in VHDL can be used in ……
A) Process B) Procedure
C) Function D) All of above
20 Which of the following is not a VHDL object data?
A) Signal B) Wire
C) Variable D) Constant
1 In Gray coding, when the state machine changes state, ______ bit/s in the state
vector changes the value.
A) one B) two
C) four D) eight
2 Which UART component/s divide/s the system clock to provide the bit clock with the
period equal to one bit time and Bclock x 8?
A) Baud Rate Generator B) Transmitter Section
C) Receiver Section D) All of the above
3 Which method/s is/are adopted for acquiring spike-free outputs?
A) Moore machine with clocked outputs B) Output-state machine
C) Mealy machine with clocked outputs D) All of the above
5 Which among the following constraint/s is/are involved in a state-machine
description?
A) State variable & clock B) State transitions & output specifications
C) Reset condition D) All of the above
6 Moore circuit, the outputs depend only on
A) Present state B) Present state, i/p
C) Input D) None of the above
7 The process in VHDL' becomes active, when
A) there is change in the value of signal in B) change in clock statement
sensitivity list
C) change in reset signal D) None of the above
8 Mealy circuit, the outputs depend only on
A) Present state B) Present state, i/p
C) Input D) None of the above
9 Multiplication can be done by _________ method
A) Shift and add B) Shift and subtract
C) Shift and multiply D) All of the above
10 A counter is an example of a state machine.
A) True B) False
C) In some cases D) Cannot be determined
11 The number of state variables is _____ , where n is the number of flip flops
A) 2n B) 2n-1
n+1
C) 2 D) 22n
12 How many flip flops are necessary to design a state machine with 25 states?
A) 2 B) 25
C) 5 D) 225
13 Which statement / clause in VHDL can be used to cover unused states in a state machine?
A) unused B) state
C) others D) dontcare
 Chapter 3

Testing of Logic Circuits

1 What is/are the necessity/ies of Simulation Process in VHDL?
A) Requirement to test designs before B) Reduction of development time
implementation & usage
C) Decrease the time to market D) All of the above
2 Which type/s of stuck at fault model exhibit/s the reduced complexity level of test
generation?
A) Single B) Multiple
C) Both a and b D) None of the above
3 Which among the following operation/s is/are executed in physical design or layout
synthesis stage?
A) Placement of logic functions in B) Interconnection of components in the chip
optimized circuit in target chip
C) Both a and b D) None of the above
4 Which among the following is/are taken into account for post-layout simulation?
A) Interconnect delays B) Propagation delays
C) Logic cells D) All of the above
5 Which level of system implementation includes the specific function oriented
registers, counters & multiplexers?
A) Module level B) Logical level
C) Physical level D) All of the above
6 In testability, which terminology is used to represent or indicate the formal
evidences of correctness?
A) Validation B) Simulation
C) Verification D) Integration
7 Among the VHDL features, which language statements are executed at the same
time in parallel flow?
A) Concurrent B) Sequential
C) Net-list D) Test-bench
8 In VLSI design, which process deals with the determination of resistance &
capacitance of interconnections?
A) Floorplanning B) Placement & Routing
C) Testing D) Extraction
9 Which among the following is a process of transforming design entry information of
the circuit into a set of logic equations?
A) Simulation B) Optimization
C) Synthesis D) Verification
10 If unequal amounts of combinational circuitry are used in the clock path to different
devices, that also could .result in unequal delays, making the clock reach different
devices at slightly different times. This problem is called ___________.
A) Glitch B) Clock skew
C) Transport delay D) None of above
11 Boundary scan technique consists of
A) Scan path testing port B) Test access port
C) Both a and b D) None of above
12 Build in Self Test is used for
A) Testing components B) Testing flipflops
C) Testing memory D) None of above
13 A test bench is used
A) Verify the functionality of a design B) To generate primitives
C) To generate netlist D) None of above
15 FLEX 10K contain
A) LABs B) EABs
C) Both a & b D) None of above
16 Boundary scan is an IEEE ________ standard
A) 1149 B) 1164
C) 1096 D) None of above
17 Manufacturer of XC 9500 is
A) Xilinx B) Xiomi
C) Altera D) None of above

Chapter 5

CMOS Logic Design:

1 In CMOS circuits, which type of power dissipation occurs due to switching of
transient current and charging & discharging of load capacitance?
A) Static dissipation B) Dynamic dissipation
C) Both a and b D) None of the above
2 In high noise margin (NMH), the difference in magnitude between the maximum
HIGH output voltage of driving gate and the maximum HIGH voltage is recognized
by the _________gate.
A) Driven B) Receiving
C) Both a and b D) None of the above
3 Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?
A) Load capacitance B) Supply voltage
C) Gain factor of MOS D) All of the above
4 The power consumption of static CMOS gates varies with the _____ of power supply
voltage.
A) square B) cube
C) fourth power D) 1/8 th power
5 In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin
count?
A) Input pad design B) Output pad design
C) Three state pad design D) All of the above
6 On the basis of an active load, which type of inverting CMOS amplifier represents
low gain with highly predictable small and large signal characteristics?
A) Active PMOS load inverter B) Current source load inverter
C) Push-pull inverter D) None of the above
7 In MOS devices, the current at any instant of time is ______of the voltage across
their terminals.
A) constant & dependent B) constant & independent
C) variable & dependent D) variable & independent
8 For complex gate design in CMOS, OR function needs to be implemented by
_______ connection/s of MOS.
A) Series B) Parallel
C) Both series and parallel D) None of the above
9 In pull-up network, PMOS transistors of CMOS are connected in parallel with the
provision of conducting path between output node &Vdd yielding _____ output.
A) 1 B) 0
C) Both a and b D)
None of the above
10 In CMOS inverter, the propagation delay of a gate is the/an _________ transition
delay time for the signal during propagation from input to output especially when
the signal changes its value.
A) Highest B) Average
C) Lowest D) None of the above
11 Which among the following is/are regarded as an/the active resistor/s?
A) MOS diode B) MOS transistor
C) MOS switch D) All of the above
12 In MOS switch, clock feedthrough effect is also known as __________.
A. charge injection
B. charge feedthrough
C. charge carrier
D. charge ejaculation
A) A&B B) B & C
C) C&D D) B & D
13 Which among the following can be regarded as an/the application/s of MOS switch
in an IC design?
A) Multiplexing & Modulation B) Transmission gate in digital circuits
C) Simulation of a resistor D) All of the above
14 As per IEEE 1164 standard ‘W’ represents
A) Forcing unknown B) Weak unknown
C) High impedance D) weak ‘1’
15 The ability to tolerate noise without affecting the correct operation of circuit is known as
A) Dynamic power dissipation B) Noise margin
C) Static power dissipation D) None of above
16 ____________ power dissipation occurs due to charging and discharging of load capacitance.
A) Static B) dynamic
C) noise D) None of above
17 ___________ power dissipation occurs due to leakage current
A) Static B) dynamic
C) noise D) None of above

Chapter 6

Architecture of Commercial Devices:

1 In spartan-3 family architecture, which programmable functional element accepts
two 18 bit binary numbers as inputs and computes the product?
A) Configurable Logic Blocks B) Input Output Blocks
C) Block RAM D) Multiplier Blocks
2 Which type of CPLD packaging comprises pins on all four sides that wrap around
the edges of chip?
A) Plastic-Leaded Chip Carrier B) Quad Flat Pack (QFP)
(PLCC)
C) Ceramic Pin Grid Array (PGA) D) Ball Grid Array (BGA)
3 Which among the following functions are performed by MSI category of IC
technology?
A) Gates, Op-amps B) Microprocessor/A/D
C) Filters D) Memory/DSP
4 In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area
and the interconnection density?
A) Placement B) Global Routing
C) Detailed Routing D) All of the above
5 In floorplanning, placement and routing are __________ tools.
A) Front end B) Back end
C) Both a and b D) None of the above
6 Which programming technology/ies is/are predominantly associated with SPLDs
and CPLDs?
A) EPROM B) EEPROM
C) FLASH D) All of the above
7 An Antifuse programming technology is predominantly associated with _____.
A) SPLDs B) FPGAs
C) CPLDs D) All of the above
8 Which attribute in synthesis process specify/ies the resistance by controlling the
quantity of current it can source?
A) Load attribute B) Drive attribute
C) Arrival time attribute D) All of the above
9 In synthesis process, the load attribute specify/ies the existing amount of
_________load on a particular output signal.
A) Inductive B) Resistive
C) Capacitive D) All of the above
10 _________ is the fundamental architecture block or element of a target PLD.
A) System Partitioning B) Pre-layout Simulation
C) Logic cell D) Post-layout Simulation
11 Sequential circuits are represented as
A) finite state machine B) infinite state machine
C) finite synchronous circuit D) infinite asynchronous circuit
12 Which constitutes the test vectors in sequential circuits?
A) feedback variables B) delay factors
C) test patterns D) all input combinations
13 Most Lookup tables in FPGAs use ______ inputs, resulting in ________ possible outputs.
A) 4,16 B) 8,16
C) 4,12 D) 6,12
14 Macro cells are available in __________.
A) CPLD B) FPGA
C) ASIC D) All of the above
15 Slices are available in _________.
A) CPLD B) FPGA
C) ASIC D) All of the above
16 CPLD features a __________ type of memory.
A) Volatile B) Non-volatile
C) EPROM D) None of the above
 Chapter 4
MOS Transistor Theory:

1.NMOSdevices areformedin
a) p-typesubstrate ofhigh dopinglevel
b)n-typesubstrate oflow dopinglevel
c) p-typesubstrate ofmoderate dopinglevel
d)n-typesubstrate ofhigh dopinglevel
2.Sourceand drain in nMOSdevice areisolatedby
a) asinglediode
b) two
diodesc)
threediodes d)
fourdiodes
3.Indepletion mode, source and drainare connected by
a)insulatingchannel
b)conducingchannel
c)Vdd
d)Vss
4.The condition fornon saturatedregion is
a) Vds =Vgs – Vt
b) Vgs lesser thanVt
c) Vds lesser than Vgs–
Vtd) Vdsgreater than Vgs–
Vt

5.Inenhancement mode, deviceis incondition a)conducting

b)nonconducting
c)partiallyconducting
d)insulating

6.The condition fornon conductingmodeis a)

Vds lesser thanVgs
b) Vgs lesser
thanVdsc) Vgs=Vds
=0
d) Vgs=Vds =Vs=0
7.nMOS is
a)donordoped
b)acceptor doped
c) allof thementioned
d)noneof thementioned
8.MOS transistor structure is
a)symmetrical
b)nonsymmetrical
c)semisymmetrical
d)pseudosymmetrical
 9..pMOS is
a)donordoped
b)acceptor doped
c) allof thementioned
d)noneof thementioned
10.Inversion layer in enhancement mode consistsof excessof
a)positivecarriers
b)negativecarriers
c)bothin equal quantity
d)neutralcarriers
11. The condition forlinear region is
a) Vgs lesser than Vt
b) Vgsgreater thanVt
c)Vds lesser thanVgs
d) Vdsgreater thanVgs
12. As sourcedrain voltageincreases, channel depth
a)increases
b)decreases
c)logarithmicallyincreases
d)exponentiallyincreses

13. Speed power product ismeasuredas the productof

a)gateswitchingdelayandgatepowerdissipation
b)gateswitchingdelayandgatepowerabsorption
c)gateswitchingdelayandnet gatepower
d)gatepower dissipation andabsorption
14. In CPTL, CMOS transmission gates consist of NMOS and PMOS transistor connected in
A. series
B. parallel
C. point to point
D. random

15. PTL with single NMOS transistor has

A. large node capacitance
B. small node capacitance
C. large node resistances
D. small node resistances

16. Pass transistor logic often uses fewer transistors, runs faster, and requires
A. more power
B. less power
C. zero power
D. infinite power
17. Implementing switches in PTL circuit with single NMOS resistor results a circuit with
A. large area
B. small area
C. zero area
D. infinite area

18. CPTL contains

A. amplifying element
B. load element
C. no amplifying element
D. ADC element

19. Complementary pass transistor logics are also called

A. differential stop transistor logic
B. integral stop transistor logic
C. differential pass transistor logic
D. integral pass transistor logic

20. PTL reduces number of

A. passive elements
B. active elements
C. load elements
D. input elements

21. In PTL, each transistor in series is less saturated at its output than at its
A. input
B. supply
C. ground
D. load

22. Pass transistor is driven by a periodic clock signal and acts as an access switch to either
charge up or charge down the
A. parasitic resistance
B. parasitic capacitance
C. parasitic source
D. parasitic inductance

23. In PTL, every circuit node has all times a low-resistance path to
A. Vth
B. vi
C. vo
D. VDD

24. When clock signal is active, parasitic capacitance will

A. charge
B. discharge
 C. not change
D. random

25. In CPL, for any logic function, there exist

A. one control variable
B. two control variables
C. three control variables
D. four control variables

26. Logic reduces count of transistors used to make different logic gates, by eliminating
redundant transistors is called
A. PTL
B. TTL
C. DTL
D. RTL

27. Logic in which switches are not connected directly to supply voltages is
A. PTL
B. TTL
C. DTL
D. RTL

28. Logic gates that uses transmission gates composed of both NMOS and PMOS pass
transistors are called
A. Complementary PTL
B. Pseudo-NMOS
C. DTL
D. RTL

29. Logic family which needs all input is true as well as in complement form is called
A. PTL
B. CPTL
C. DTL
D. RTL

30. When clock signal is active (CK = 1), logic will be

A. 0
B. 1
C. −∞
D. ∞

31. Each signal in complementary pass transistor logic is carried out by

A. one wire
B. two wires
C. three wires
D. four wires
32. Transistors are used as switches between nodes of a circuit to pass
A. logic levels
B. positive supply
C. negative supply
D. output level

33. When clock signal is zero i.e. CK=0 than parasitic capacitance will
A. charge
B. discharge
C. not change
D. random

34. Multiple logic stages can't be cascaded in

A. PTL
B. CPTL
C. DTL
D. RTL

35. Complementary pass logic family is based on

A. multiplier logic
B. multiplexer logic
C. additior logic
D. subtractor logic

36. To implement complementary pass logic family, we need input x and its
A. output
B. supply voltage
C. noise signal
D. complement
A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)

A) B)
C) D)