GENERAL REGISTER ORGANIZATION

A set of flip-flops forms a register. A register is a unique high-speed

storage area in the CPU. They include combinational circuits that
implement data processing. The information is always defined in a
register before processing. The registers speed up the implementation
of programs.

Registers implement two important functions in the CPU operation are

as follows −

 It can support a temporary storage location for data. This

supports the directly implementing programs to have fast access
to the data if required.
 It can save the status of the CPU and data about the directly
implementing program.

Example − Address of the next program instruction, signals get from

the external devices and error messages, and including different data
is saved in the registers.

If a CPU includes some registers, therefore a common bus can link

these registers. A general organization of seven CPU registers is
displayed in the figure.
The CPU bus system is managed by the control unit. The control unit
explicit the data flow through the ALU by choosing the function of the
ALU and components of the system.

Consider R1 ← R2 + R3, the following are the functions implemented

within the CPU −

MUX A Selector (SELA) − It can place R2 into bus A.

MUX B Selector (SELB) − It can place R3 into bus B.

ALU Operation Selector (OPR) − It can select the arithmetic
addition (ADD).

Decoder Destination Selector (SELD) − It can transfers the result

into R1.

The multiplexers of 3-state gates are performed with the buses. The
state of 14 binary selection inputs determines the control word. The
14-bit control word defines a micro-operation.

The encoding of register selection fields is specified in the table.

Encoding of Register Selection Field

Binary Code SELA SELB SELD

000 Input Input None

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7

There are several micro-operations are implemented by the ALU. Few

of the operations implemented by the ALU are displayed in the table.

Encoding of ALU Operations

 OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 ADD A and B AND

01010 OR A and B OR

01100 XOR A and B XOR

01110 Complement A COMA

10000 Shift right A SHRA

11000 Shift left A SHLA

There are some ALU micro-operations are shown in the table.

ALU Micro-Operations

Micro-operation SELA SELB SELD OPR Control Word

R1 ← R2 – R3 R2 R3 R1 SUB 010 011 001 00101

R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010

R6 ← R6 + R1 - R6 R1 INCA 110 000 110 00001

R7 ← R1 R1 - R7 TSFA 001 000 111 00000

Output ← R2 R2 – None TSFA 010 000 000 00000

Output ← Input Input - None TSFA 000 000 000 00000

R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000

R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

STACK ORGANIZATION:

Stack is also known as the Last In First Out (LIFO) list. It is the most
important feature in the CPU. It saves data such that the element
stored last is retrieved first. A stack is a memory unit with an address
register. This register influence the address for the stack, which is
known as Stack Pointer (SP). The stack pointer continually influences
the address of the element that is located at the top of the stack.

It can insert an element into or delete an element from the stack. The
insertion operation is known as push operation and the deletion
operation is known as pop operation. In a computer stack, these
operations are simulated by incrementing or decrementing the SP
register.

Register Stack

The stack can be arranged as a set of memory words or registers.

Consider a 64-word register stack arranged as displayed in the figure.
The stack pointer register includes a binary number, which is the
address of the element present at the top of the stack. The three-
element A, B, and C are located in the stack.

The element C is at the top of the stack and the stack pointer holds
the address of C that is 3. The top element is popped from the stack
through reading memory word at address 3 and decrementing the
stack pointer by 1. Then, B is at the top of the stack and the SP holds
the address of B that is 2. It can insert a new word, the stack is
pushed by incrementing the stack pointer by 1 and inserting a word in
that incremented location.
The stack pointer includes 6 bits, because 2 6 = 64, and the SP cannot
exceed 63 (111111 in binary). After all, if 63 is incremented by 1,
therefore the result is 0(111111 + 1 = 1000000). SP holds only the six
least significant bits. If 000000 is decremented by 1 thus the result is
111111.

Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1.
If the stack is null, then the one-bit register ‘EMTY’ is set to 1. The
data register DR holds the binary information which is composed into
or readout of the stack.

First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as

the stack is not full (FULL = 0), a new element is inserted using the
push operation.

The push operation is executed as follows −

SP←SP + 1 It can increment stack pointer

K[SP] ← DR It can write element on top of the stack

If (SP = 0) then (FULL ← 1) Check if stack is full

EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next

higher word is saved in the SP. The word from DR is inserted into the
stack using the memory write operation. The first element is saved at
address 1 and the final element is saved at address 0. If the stack
pointer is at 0, then the stack is full and ‘FULL’ is set to 1. This is the
condition when the SP was in location 63 and after incrementing SP,
the final element is saved at address 0. During an element is saved at
address 0, there are no more empty registers in the stack. The stack is
full and the ‘EMTY’ is set to 0.

A new element is deleted from the stack if the stack is not empty (if
EMTY = 0). The pop operation includes the following sequence of
micro-operations −

DR←K[SP] It can read an element from the top of the

stack

SP ← SP – 1 It can decrement the stack pointer

If (SP = 0) then (EMTY ← Check if stack is empty

1)

FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus
the stack pointer is decremented. If the stack pointer reaches 0, then
the stack is empty and ‘EMTY’ is set to 1. This is the condition when
the element in location 1 is read out and the SP is decremented by 1.

INSTRUCTION FORMATS
Instruction includes a set of operation codes and operands that manage with
the operation codes. Instruction format supports the design of bits in
an instruction. It contains fields including opcode, operands, and
addressing mode.

The instruction length is generally preserved in multiples of the

character length, which is 8 bits. When the instruction length is
permanent, several bits are assigned to opcode, operands, and
addressing modes.

The function of allocating bits in the instruction can be interpreted by

considering the following elements −

 Number of addressing modes

 Number of operands
 Number of CPU registers
 Number of register sets
 Number of address lines
The figure displayed the general IA-32 (Intel Architecture- 32 bits)
instruction format. IA-32 is the instruction format that can Intel’s most
outstanding microprocessors. This instruction format includes four
fields, such as opcode field, addressing mode field, displacement field,
and immediate field.

The opcode field has 1 or 2 bytes. The addressing mode field also
includes 1 or 2 bytes. In the addressing mode field, an instruction
needs only one byte if it uses only one register to generate the
effective address of an operand.

The field that directly follows the addressing mode field is the
displacement field. If an effective address for a memory operand is
computed using the displacement value, then it uses either one or four
bytes to encode. If an operand is an immediate value, then it is
located in the immediate field and it appears either one or four bytes.

ADDRESSING MODES :

The operands of the instructions can be located either in the main

memory or in the CPU registers. If the operand is placed in the main
memory, then the instruction provides the location address in the
operand field. Many methods are followed to specify the operand
address. The different methods/modes for specifying the operand
address in the instructions are known as addressing modes.

Types of Addressing Modes:

There are various types of Addressing Modes which are as follows −

Implied Mode − In this mode, the operands are specified implicitly in

the definition of the instruction. For example, the instruction
"complement accumulator" is an implied-mode instruction because the
operand in the accumulator register is implied in the definition of the
instruction. All register reference instructions that use an accumulator
are implied-mode instructions.

Instruction format with mode field

Opcode Mode Address

Immediate Mode − In this mode, the operand is specified in the

instruction itself. In other words, an immediate-mode instruction has
an operand field instead of an address field. The operand field includes
the actual operand to be used in conjunction with the operation
determined in the instruction. Immediate-mode instructions are
beneficial for initializing registers to a constant value.

Register Mode − In this mode, the operands are in registers that

reside within the CPU. The specific register is selected from a register
field in the instruction. A k-bit field can determine any one of the
2k registers.

Register Indirect Mode − In this mode, the instruction defines a

register in the CPU whose contents provide the address of the operand
in memory. In other words, the selected register includes the address
of the operand rather than the operand itself.

A reference to the register is then equivalent to specifying a memory

address. The advantage of a register indirect mode instruction is that
the address field of the instruction uses fewer bits to select a register
than would have been required to specify a memory address directly.

Autoincrement or Autodecrement Mode &minuend; This is similar

to the register indirect mode except that the register is incremented or
decremented after (or before) its value is used to access memory.
When the address stored in the register defines a table of data in
memory, it is necessary to increment or decrement the register after
every access to the table. This can be obtained by using the increment
or decrement instruction.

Direct Address Mode − In this mode, the effective address is equal

to the address part of the instruction. The operand resides in memory
and its address is given directly by the address field of the instruction.
In a branch-type instruction, the address field specifies the actual
branch address.

Indirect Address Mode − In this mode, the address field of the

instruction gives the address where the effective address is stored in
memory. Control fetches the instruction from memory and uses its
address part to access memory again to read the effective address.
Indexed Addressing Mode − In this mode, the content of an index
register is added to the address part of the instruction to obtain the
effective address. The index register is a special CPU register that
contains an index value. The address field of the instruction defines
the beginning address of a data array in memory.

DATA TRANSFER AND MANIPULATION:

Data transfer instructions move data from one place in the computer
to another without changing the data content. The most common
transfers are between memory and processor registers, between
processor registers and input or output, and between the processor
registers themselves.

The load instruction is used to transfer for memory to a processor

register, usually an accumulator. The store instruction is used to
transfer data to memory. The move instruction is used to transfer data
from one register to other. It has also been used for data transfers
between CPU registers and memory or between two memory words.
The exchange instruction swaps information between two registers or
a register and a memory word. The input and output instructions
transfer data among processor registers and input or output terminals.
The push and pop instructions transfer data between processor
registers and a memory stack.

DATA MANIPULATION INSTRUCTIONS:

Data manipulation instructions perform operations on data and provide
the computational capabilities for the computer. The data manipulation
instructions in a typical computer are usually divided into three basic
types:

a. Arithmetic instructions
b. Logical and bit manipulation
instructions
c. Shift instructions
Arithmetic Instructions

The four basic arithmetic operations are addition, subtraction,

multiplication, and division. Most computers provide instructions for all
four operations. Some small computers have only addition and
possibly subtraction instructions. The multiplication and division must
then be generated by means of software subroutines. The increment
instruction adds 1 to the value stored in a register or memory word.
The decrement instruction subtracts 1 from a value stored in a register
or memory word. The instruction "add with carry" performs the
addition on two operands plus the value of the carry from the previous
computation. Similarly, the "subtract with borrow" instruction
subtracts two words and a borrow which may have resulted from a
previous subtract operation.The negate instruction forms the 2' s
complement of a number, effectively reversing the sign of an integer
when represented in the signed-2's complement form.
Logical and Bit Manipulation Instructions

Logical instructions perform binary operations on strings of bits stored

in registers. They are useful for manipulating individual bits or a group
of bits that represent binary-coded information. The AND instruction is
used to clear a bit or a selected group of bits of an operand. The OR
instruction is used to set a bit or a selected group of bits of an
operand. Similarly, the XOR instruction is used to selectively
complement bits of an operand. Individual bits such as a carry can be
cleared, set, or complemented with appropriate instructions.

Shift Instructions

Instructions to shift the content of an operand are quite useful and are
often provided in several variations. Shifts are operations in which the
bits of a word are moved to the left or right. The bit shifted in at the
end of the word determines the type of shift used. Shift instructions
may specify either logical shifts, arithmetic shifts, or rotate-type
operations. In either case the shift may be to the right or to the left.

The logical shift inserts 0 to the end bit position. The end position is
the leftmost bit for shift right and the rightmost bit position for the
shift left.

The arithmetic shift-right instruction must preserve the sign bit in the
leftmost position. The sign bit is shifted to the right together with the
rest of the number, but the sign bit itself remains unchanged. This is a
shift-right operation with the end bit remaining the same. The
arithmetic shift-left instruction inserts 0 to the end position and is
identical to the logical shift-left instruction.

The rotate instructions produce a circular shift. Bits shifted out at one
end of the word are not lost as in a logical shift but are circulated back
into the other end.

PROGRAM-CONTROL
Instructions of the computer are always stored in consecutive memory
locations. These instructions are fetched from successive memory
locations for processing and executing.

When an instruction is fetched from the memory, the program counter

is incremented by 1 so that it points to the address of the next
consecutive instruction in the memory. Once a data transfer and data
manipulation instruction are executed, the program control along with
the program counter, which holds the address of the next instruction
to be fetched, is returned to the fetch cycle.

Data transfer and manipulation instructions specify the conditions for

data processing operations, whereas the program control instructions
specify the conditions that can alter the content of the program
counter.
The change in the content of the program counter can cause an
interrupt/break in the instruction execution. However, the program
control instructions control the flow of program execution and are
capable of branching to different program segments.

Some of the program control instructions are listed in the table.

Program Control Instructions

Name Mnemonics

Branch BR

Jump JMP

Skip SKP

Call Call

Return RET

Compare (by Subtraction) CMP

Test (by ANDing) TST

The branch is a one-address instruction. It is represented as BR ADR,

where ADR is a mnemonic for an address. The branch instruction
transfers the value of ADR into the program counter. The branch and
jump instructions are interchangeably used to mean the same.
However, sometimes they denote different addressing modes.

The conditional branch instructions such as ‘branch if positive’, or

‘branch if zero’ specifies the condition to transfer the flow of execution.
When the condition is met, the branch address is loaded in the
program counter.
The figure depicts the conditional branch instructions.

The compare instruction performs an arithmetic subtraction. Here, the

result of the operation is not saved; instead, the status bit conditions
are set. The test instruction performs the logical AND operation on two
operands and updates the status bits.

REDUCED INSTRUCTION SET COMPUTER:

RISC stands for Reduced Instruction Set Computer. In Reduced

Instruction Set Computer (RISC) architecture, the instruction set of
the computer is simplified to reduce the execution time. RISC has a
small set of instructions, which generally include register-to-register
operations.

Thus, data is stored in processor registers for computations, and

results of the computations are transferred to the memory using store
instructions. All operations are performed within the registers of the
CPU. In RISC, all instructions have simple register addressing and
hence use less number of addressing modes.

RISC uses relatively a simple instruction format and is easy to decode.

Here, the instruction length can be fixed and aligned on word
boundaries. The RISC processors can execute one instruction per clock
cycle.

This is done using pipelining, which involves overlapping the fetch,

decode, and execute phases of two or three instructions. As RISC
takes relatively a large number of registers in the processor unit, it
takes less time to execute its program when compared to CISC.

Features of RISC Processor:

There are various features of CISC Processor that are as follows −

 It can relatively few instructions.

 It can relatively few addressing modes.
 It is used for memory access limited to load and store
instructions.
 All operations are done within the registers of the CPU.
 It can fixed-length, easily decoded instruction format.
 It is used for single-cycle instruction execution.
 It can be hardwired rather than micro-programmed control.
ARCHITECTURE OF MICROPROCESSOR -8085:

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-

bit microprocessor designed by Intel in 1977 using NMOS technology.

It has the following configuration −

 8-bit data bus

 16-bit address bus, which can address upto 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock

It is used in washing machines, microwave ovens, mobile phones, etc.

8085 Microprocessor – Functional Units

8085 consists of the following functional units −

Accumulator

It is an 8-bit register used to perform arithmetic, logical, I/O &

LOAD/STORE operations. It is connected to internal data bus & ALU.

Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations

like Addition, Subtraction, AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D,

E, H & L. Each register can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing
combination is like B-C, D-E & H-L.

Program counter

It is a 16-bit register used to store the memory address location of the

next instruction to be executed. Microprocessor increments the
program whenever an instruction is being executed, so that the
program counter points to the memory address of the next instruction
that is going to be executed.

Stack pointer

It is also a 16-bit register works like stack, which is always

incremented/decremented by 2 during push & pop operations.

Temporary register

It is an 8-bit register, which holds the temporary data of arithmetic

and logical operations.

Flag register

It is an 8-bit register having five 1-bit flip-flops, which holds either 0

or 1 depending upon the result stored in the accumulator.

These are the set of 5 flip-flops −

  Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)

Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory

then it is stored in the Instruction register. Instruction decoder
decodes the information present in the Instruction register.

Timing and control unit

It provides timing and control signal to the microprocessor to perform

operations. Following are the timing and control signals, which control
external and internal circuits −

Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT
Interrupt control

As the name suggests it controls the interrupts during a process. When

a microprocessor is executing a main program and whenever an
interrupt occurs, the microprocessor shifts the control from the main
program to process the incoming request. After the request is
completed, the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5,

RST 6.5, RST 5.5, TRAP.
Serial Input/output control

It controls the serial data communication by using these two

instructions: SID (Serial input data) and SOD (Serial output data).

Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded
into the address buffer and address-data buffer to communicate with
the CPU. The memory and I/O chips are connected to these buses; the
CPU can exchange the desired data with the memory and I/O chips.

Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas

address bus carries the location to where it should be stored and it is
unidirectional. It is used to transfer the data & Address I/O devices.

8085 Architecture

We have tried to depict the architecture of 8085 with this following

image −