THE UNIVERSITY OF DA NANG

UNIVERSITY OF SCIENCE AND TECHNOLOGY

FACULTY OF ADVANCED SCIENCE AND TECHNOLOGY

LABORATORY REPORT
MULTISTAGE AMPLIFIER

PBL2
Instructor: Le Quoc Huy
Member : Phan Dinh Khanh - 123210085 (Leader)
Truong Phuoc Thinh - 123210126
Dang Van Minh - 123210119
Phung Do Anh Khoa - 123210116
Class : 21ES
Group : 5
 I. Introduction:
Multistage Amplifier is an important part of the field of electronics. It
involves making electrical signals stronger and more stable in
technological devices and applications. In this project we study how to
create a multistage amplifier including Common source, common emitter
and common collector configurations were selected for stages 1, 2 and 3
respectively. The amplifier was then simulated in Proteus software for
finalizing the values of the components and verification of the theoretical
design.
II. Process:
1. Theoretical basis of circuit:

Figure 1: Schematic Diagram of the Three-Stage Amplifier

The selected three-stage amplifier configuration depicted in Figure 1 features input and
output connections coupled through capacitors C1 and C6. Additionally, bypass
capacitors C2 and C4 have been employed to optimize the voltage gain of the two
inverting amplifiers without affecting their operating points. Furthermore, coupling
capacitors C3 and C5 have been utilized to facilitate the transfer of AC signals between
the amplifiers while providing DC isolation, thereby safeguarding the Q-points of the
transistors in each individual stage from any interference.
+ Common source: MOSFET 2N7000: This configuration is best for the first
stage, since it gives us a high input resistance and an average gain.The input
resistance is used to draw a more sufficient current from the input signal.The
high input resistance here is in the order of Mega Ohm.
+ Common emitter: BJT 2N2222: This configuration is best for the second stage
since we need to provide a high gain for the load. In order to do this, a by-pass
 capacitor was connected across the RE to get the highest gain without affecting
the Q point of the BJT 1.
+ Common collector: BJT 2N2222: This configuration is suited to be used in the
last stage for its low output resistance and to buffer the high gain stage for a low
value of load resistance.
2. DC analysis:
● For stability and better performance at the expected gain, a DC analysis was
performed to decide on Q-points for each stage. For DC consideration, all
capacitors act as open circuits due to high impedance. Therefore, each stage is
analyzed below.
a) Common-Source:
- Hand Calculation.
 - Simulation:

• From the result of both hand calculation and simulation from proteus , we can
easily conclude that the 2N7000 is working in the saturation region since Id > 0
but not too small and Vds > 0.
- Real circuit:
b) Common-Emitter
- Hand Calculation
 - Simulation

● From the result of both hand calculation and simulation from proteus, we
can easily conclude that the 2N2222 is working in the forward-active
region since Ic>0 but not too small and Vce>0.
- Real circuit:
c) Common collector
- Hand Calculation
 - Simulation

● From the result of both hand calculation and simulation from proteus, we
can easily conclude that the 2N2222 is working in the forward-active
region since Ic>0 but not too small and Vce>0.
- Real circuit:
3. AC analysis:
a) Common-Source
- Hand calculation
 - Simulation

We can conclude from these result from proteus simulation that:

- Input voltage and output voltage are out of phase
- The voltage gain of the stage 1:
Av = Vout / Vin (peak to peak) = 5.65 (mV) / 300 (mV) = 1.8(abs)
b) Common-emitter
- Hand calculation:

- Simulation:
 We
can

conclude from these result from proteus simulation that:

- Input voltage and output voltage are out of phase
- The voltage gain of the stage 2:
Vin (peak to peak) = 5.65 (mV)
162.50−(−180.00)
Vout (peak to peak) = 2
= 171.25 (mV)
𝑉𝑜𝑢𝑡 171.25
Av = 𝑉𝑖𝑛
= 5.65
= 30.31 (abs)
c) Common collector
- Hand calculation
 - Simulation

We can conclude from these result from proteus simulation that:

- Input voltage and output voltage are out of phase
- The voltage gain of the stage 2:
162.50−(−180.00)
Vin (peak to peak) = 2
= 171.25 (mV)
156.29−(−168.90)
Vout (peak to peak) = 2
= 162.595 (mV)
𝑉𝑜𝑢𝑡 162.595
Av = 𝑉𝑖𝑛
= 171.25
= 0.949 (abs)
4. Voltage Gain:
a) Hand calculate:

b) Simulation:
𝑅𝑖𝑛 50
𝐴𝑣Σ= Av1*Av2*Av3 𝑅𝐼 + 𝑅𝑖𝑛 = (1.8)(30.31)(0.949)( 51 ) = 50.760

III. Conclusion:
- We can see that all values of the circuit when calculated manually,
simulated as well as actually measured have errors of no more than 10%.
This shows that the hand calculation is reliable.

⚫ Analyze result:
IV. Frequency multistage amplifier:
⚫ Analyze result: