Professional Documents
Culture Documents
Shweta DTE Micro
Shweta DTE Micro
REPORT ON
“Circuit For 4 Bit Adder”
SUBMITTED TO THE
SHIVAJI POLYTECHNIC, ATPADI
IN THE PARTIAL FULFILLMENT OF THE REQUIREMENTS
OF
DIPLOMA IN
COMPUTER TECNOLOGY
SUBMITTED BY
Name: Shweta Sunil Randive Exam seat No:-
(2023-2024)
1
SHIVAJI POLYTECHNIC, ATPADI
CERTIFICATE
Date:
Place: Atpadi
2
2
Acknowledgments
3
Table of Contents
SR CONTENTS PAGE
NO. NO.
1. CIRCUIT FOR BIT ADDER 5
AND TESTING
AND TESTING
4. CONCLUSION 14
5. REFERENCES 15
4
CIRCUIT FOR 4-BIT ADDER
Circuit Configuration
PG Block
Pi = Ai
Bi Gi =
Ai Bi
The schematic simulation and the final simulation after the layout
extraction are shown in Figure 3 and Figure 4. The layout of c-chain is
shown in Appendix 1.
5
Figure 2. Circuit of C-Chain
6
2 SUM Block
In above two simulations, we can see that their functions are the same and the
waveforms are consistent.
7
Appendix 2 shows the layout of XNOR and the schematic simulation as
well as the simulation after the layout extraction is shown in Figure 7
and Figure 8.
8
Figure 9: Circuit of 1-Bit Adder Schematic
9
Noise Margin Testing
The circuit below (Figure 12) is used to test noise margin of 1-bit adder.
Cin connects to Vss, A connects to Vdd. B is input signal, which is used to test
and analysis DC characteristics. Its DC character is shown in Appendix 3.
10
The structure of 4-bit adder is composed of four 1-bit adder as shown
in Figure 13.
The worst case testing circuit and the simulation results of schematic and
layout are shown in Figure 15 and Figure 16 respectively. In layout
simulation in Figure 17(also in Appendix 7, 8). The longest propagate
delay occur on Cin to Cout
11
because of the line delay in layout. We can get the longest propagate delay
from the waveform in Appendix 7.
The longest rise and fall time happened on SUM out and can be obtained
from Appendix 8.
tr = 0.588 ns , tf = 0.688 ns
The rise time and fall time is less than 1.5ns, which satisfy design
requirement.
12
Figure 17. Layout simulation of Worse Case
13
CONCLUSION
The Half Adder and Full Adder are the elementary unit of different computerized
circuits, for example, PCs, Calculators, advanced digital systems. The benefit of
utilizing Adders is that it is the piece of the advanced circuit. What's more, logic gates
shape the foundation of the advanced circuit, and they process the input extremely fast. The
swiftness by logic gates is in microseconds, and we require quick calculation of results in
relatively every application, and in this way, we utilize adders.
14
REFERENCES
15