TI簡介模擬電子培訓資料

Agenda
• TI Overview
• Precision Signal Chain Selection Guide
• Precision Signal Chain Example
• High Speed Signal Chain Selection Guide
• High Speed Signal Chain Example
• TI Power & Power Reference Designs
• Switching Power PCB Design
Complete Signal Chain Portfolio
Precision Audio Interface High

& & Low-Power
Analog Imaging Speed RF
Clocks
ØA/D Converters ØAudio Amps ØRS-422/485 ØA/D Converters ØSystem-on-Chip
ØD/A Converters ØAudio Converters ØIsolation, CAN ØD/A Converters ØTransceivers
ØOp Amps ØCodecs ØDisplay, LVDS, Serdes ØOp Amps ØRange Extenders
ØInstrumentation Amps ØSample Rate ØUSB, UART, RS232 ØMod/Demodulators ØZigBee®
ØDifferential Amps Converters Ø1394, DVI, Switches ØUp/Down Converters ØRemote Control
ØLog Amps ØMic Preamps ØPCIe, ESD, I2C ØSynthesizers Ø Wireless Audio
ØTemperature Sensors ØVolume Controls ØLevel Translation ØVariable Gain Amps ØZigBee RF4CE
ØVoltage References ØLine Drivers ØLine Circuits, Opto ØVideo Muxes Ø6LowPAN
ØShunt Monitors ØLine Receivers ØClock Distribution ØANT
ØComparators ØCCD AFEs ØClock Generation ØBluetooth® low energy

ØTouch Screen Control ØMemory Clocks
ØGamma Buffers
ØMotor Drivers
ØDigital Potentiometers
• More than 16,000 products – adding over 200/year
Ø4-20mA Transmitters
• 10-15 year typical product lifetime with no obsolescence
放大器
什么是运算放大器？
• 运算放大器是线性系统中最常见的器件
• 运放的高集成度允许你基于它们设计一些复杂的功
能，而不需要知道运放的内部发生了什么
• 运算放大器的标识：简单的外观，众多的指标
VCC
_
+ VOUT
运算放大器在电子系统中的位置
电源电源监视显示存储
电源分配数据传输
模拟输出
传感器 ADC DSP/µC DAC
/激励
信号调理信号调理
运放的功能
ZFB
VCC
ZIN _
运放+外部分立元件 =
放大器 : 改变信号的幅度
缓冲器: 隔离输入和输出，阻抗匹配（高输入阻抗，低输出阻抗）
滤波器: 滤除不想要的频率分量：噪声和干扰
各种运算功能: 积分，微分，乘法，对数，等等
放大器
• 基础: 运算放大器 Operational Amplifier (OPA)
• 运算放大器的延伸：
- 仪表放大器 Instrumentation Amp (INA)
- 程控放大器 Programmable Gain Amp (PGA)
- 对数放大器 Log Amp
- 积分放大器 Integrator Amp
- 采样保持放大器 Sample Hold Amp
- 跨阻放大器 Transimpedance Amp
- 跨导放大器 Transconductance Amp (OTA)
……
TI放大器的命名规律
运算放大器
• OPAxxx：Operational Amplifiers 包括精密运放，高速运放；
• THSxxx： High-Speed Amplifiers 与OPA中的高速运放的差别：电压范围更宽
• TLV/TLC/TLE：运放： TLV(2.7-16V, CMOS)，TLC(5-16V, CMOS)，TLE(宽电压)；
通用/高速比较器，以及ADC/DAC
• BUFxxx：缓冲器
仪表放大器
• INAxxx： Instrumentation, Difference, and Current Sensing Amplifiers
增益可控放大器
• PGAxxx：Digital Programmable Gain Amplifier, 10MHz以下
• VCAxxx：Voltage Controlled Amplifier, IF 宽带放大衰减
音频放大器
• TPA/TASxxx：音频功放/处理，class AB & class D
特殊功能放大器
• XTRxxx： 4-20mA 发射器； RCVxx: 4-20mA 接收器
• LOGxxx：对数放大器
• IVCxxx：积分放大器
• DRVxxx：驱动放大器（PWM，线路驱动等）
理想放大器和实际放大器
理想的运算放大器
速度 • 无穷大的带宽
• 无穷大的压摆率
Vcc
+
• 无穷大的增益
• 无穷大的输入阻抗
v2 • 零输出阻抗
- VOUT =A(v2-v1) • 零噪声
VIN A
• 零失调电压及其温漂
+
v1
精度 • 零偏置电流及其温漂
- • 无穷大的CMRR和PSRR
Vcc • 零功耗
• 无穷大的输入输出摆幅
• 无穷大的输出功率
功耗和驱动能力
更重要的：免费
10
一个不完美运放的例子：滤波器设计
滤波器设计软件 – FilterPro 3.1
Spice仿真软件 – TINA-TI 9.1
http://focus.ti.com/docs/toolsw/folders/print/filterpro.html
免费！
http://focus.ti.com/docs/toolsw/folders/print/tina-ti.html
有源滤波器设计和仿真：
基于 FilterPro & TINA-TI
2nd Order LPF with Fc = 1MHz

C2 298.4p
-
Vout
R1 953 R2 953 U1 OPA340
+
+
Cbypass 10n
+
Vin 0
C1 100p
V+ 5
Voffset 2.5 5.5MHz的OPA340

有源滤波器设计和仿真：
基于 FilterPro & TINA-TI
2nd Order LPF with Fc = 1MHz

C2 298.4p
-
V out
R1 953 R2 953 U1 OPA 354
+
+
Cbypass 10n
+
V in 0
C1 100p
V+ 5
V of f set 2.5 200MHz的OPA354

实际的运算放大器
Ÿ 带宽： kHz to GHz
Ÿ 压摆率： 0.1-8000 V/µs
Vcc + 速度
Ÿ 有限的增益：80 to 167 dB
Ib Is Ÿ 输出阻抗： 1-1k Ω
v2 Ÿ 输入阻抗： 106−1012Ω, 0.2-20pF
- - VOUT =AVIN+Ve Ÿ 噪声：1-1000 nV/√Hz
VIN A Ÿ 失调电压：5 µV- 10mV
+ + 精度 Ÿ 偏置电流：10 fA-250nA
v1 + Vos - Is Ÿ 共模抑制比 CMRR：50-130 dB
Ib Ÿ 电源纹波抑制比 PSRR：50-145 dB
Vcc - Ÿ 静态电流： 1µΑ−10mA
Ÿ 输入输出电压摆幅： Vcc+ to Vcc-
功耗和驱动能力 Ÿ 输出功率：0.1-500W
RMB!
选择精密放大器
输入失调电压（Input Offset Voltage）和
输入偏置电流（Input Bias Current）
• 直流指标，对运放直流精度的影响最为直观
• 失调电压 – 因同相端和反相端失配而产生的输入级固有电压差，越小
越好
• 偏置电流 – 输入级为了能正常工作而对输入晶体管进行偏置所需要的
基极电流（BJT）或栅极电流（JFET），可能流入（npn BJT或p沟道
JFET）或流出（pnp BJT或n沟道JFET）运放的输入引脚，越小越好
R2
VIN set 失调电压VOS是针对V+和V-之间的固有电压差；
to 0 V
R1 偏置电流IB针对V+和V-单个引脚而言，IB+和IB-；
VS- ib-
- 失调电流IOS是等于IB+-IB-；
DVOS
+ 对于一些没有内部偏置电流调零电路的运放来说，
VS + R ib+
3 IOS可以比IB小10倍以上；
对于有调零电路的运放来说，两者几乎相等。
Ve=Vos*Gain+Ib*Rs*Gain
运算放大器的工艺决定Vos 和 Ib
Ø 运放的设计工艺对其各种指标有非常重要的影响
Ø 常常有三种基本工艺:
* Bipolar：低输入阻抗, Ib =1-100nA；Vos=10-100uV, 低至0.1uV/OC; 低电压噪声，如1nV/√Hz
* JFET：高输入阻抗, Ib=10-100pA, 但温漂大，每10摄氏度翻倍；Vos=0.1-5mV;
* CMOS：高输入阻抗; 低失调; 轨到轨输出能力; 低功耗，Iq可低至700nA
Ø TI独有的领先工艺：
* DiFET: 极高的输入阻抗, Ib低至3fA; 低失调; 极低的电流和电压噪声; 最好的直流精度
Ø 这些工艺也可以结合：
BiFET: Bipolar + JFET：FET输入，Bipolar输出
BiCMOS: Bipolar + CMOS：常见于模数混合电路，如电源芯片
Ø 因此，对于我们这里描述的Vos和Ib来说，关心OPA输入级的工艺
TI 精密放大器家族
运放的直流精度通常由其输入级工艺决定
精密运算放大器：
• OPAy2xx: Bipolar，精密，微输入失调电压, 低噪声, GBW<=80MHz; OPA209, OPA211, OPA1611
• OPAy1xx: FET, Difet，精密，高输入阻抗，微偏置电流(但温漂较高); GBW<=20MHz; OPA140, OPA827
• OPA16xy: 音频专用高性能运放；OPA161y: Biploar；OPA164y, JFET; OPA1632, 全差分；
• OPA637,OPA627: Difet，精密，优秀的直流交流特性，GBW<=80MHz；
• OPAy3xx: CMOS, <=5.5V,精密, 直流特性出众, 低功耗, 轨到轨, 自归零，零交越失真……
GBW<=250MHz; OPA347, OPA374, OPA333, OPA365, OPA354, OPA300
• OPAy7xx: CMOS, <=24V; GBW<=20MHz; OPA727, OPA735
• TLV/TLCxxxy： CMOS, <=16V; GBW<=10MHz; 针对低成本，低频应用；TLV246y，TLC08y
* 上面型号中的y 表示通道数
运放的开环增益(Aol)和环路增益(Aolβ)与运放的精度
a Ao l
同相放大器的 A c l = V O U T / V IN = =
1+ aβ 1 + Ao l β
VOUT V IN
误差E = =
Aol 1 + Ao l β
只有当 A o l β 远大于 1时， A c l 才等于理想的 1 / β 。
为保证 1％倍 V I N 的误差精度，应使 1 + A o l β 大于 1 0 0
放大器的电压噪声
常见的噪声源：
传感器输出噪声
电阻热噪声
数据转换器噪声
射频干扰
电源纹波
…
运算放大器也有噪声:
电流噪声和电压噪声
电流噪声通常可以忽略不计
1/f噪声：和频率成反比，频率越低，噪声的功率谱密度越大；
数据手册通常会给出0.01-10Hz之间的峰峰值噪声大小。
宽带白噪声：平坦的噪声功率谱密度，总噪声大小与信号的带宽密切相关
几个名词解释
• 轨到轨输入/输出 Rail-Rail Input/Output
- 窄供电电压系统中非常有用。
- 比如在电池供电系统中，如何从3.3V供电的运放里获得3V的动态范围？
• 自归零，零温漂 Auto Zero & Zero Drift

• 零交越失真 Zero Crossover
输出信号幅度被供电电压所限制
在最大输出幅度和供电电源轨间必须有一定的裕量或净空，保
证输出不被削顶/底。对输入也是一样。
根据运放输出结构不同，这个裕量从数mV到数V不等。
轨到轨输入输出运放示例
OPA365: Vdd+ = 5V, Vdd- = GND
轨到轨输入和输出运放： 5V
如OPA365，输入和输出摆幅都能非常
接近供电电源轨. 但也不能完全达到。
GND
Input Signal Output Signal
Range Range
轨到轨输出运放： OPA335: Vdd+ = 5V, Vdd- = GND
如OPA335，输出摆幅可以非常接近供 5V
电电源轨. 但不能完全达到。输入在高 3.5V
电平处需要1.5V的净空。
GND
Range Range
非轨到轨运放： uA741
如uA741, LM324, OP27等，输入和输 Vdd+
出在高电平和低电平处都需要一定的净
空才能保证不发生削顶/底
Vdd-
Range Range
几个名词解释

- Vos非常讨厌，特别是我有10万个产品都需要调零的时候，有没有
运放不需要调零也能达到非常好的直流精度？
- 当我的产品在非常宽的温度范围内工作的时候，如何保证在整个温
度范围内误差控制在很小的范围内，从而减少我对调零的需求？

OPA333, OPA2333
Very Low Power Zero-Drift / Auto-Zero OPA
• Ultra-Low Quiescent Current: 25µA (max) • Lowest Power Increases Battery Life
• Low Offset Voltage: 10µV (max) • Low Offset and Drift Removes Need for
• Offset Voltage Drift: 0.05µV/˚C (max) Calibration in Application
• Low Voltage Noise: 1.1 µVP-P • RRIO Increases Dynamic Range
• Bandwidth: 350kHz • 1.8V Supply Excellent for Battery Devices
• Rail-to-Rail Input and Output • Micro SC70 Package Saves Board Space
• 1.8V to 5.5V Supply Voltage
• Specified Temperature Range:
• -40°C to +125°C
• OPA333: SC70-5, SOT23-5, SO-8
• OPA2333: QFN-8, SO-8
• Battery-Powered Instruments
• Temperature Measurement
• Precision Strain Gages
• Precision Sensor Applications
• Handheld Test Equipment
低失调电压运放的两种结构：
自归零 Auto-Zero 和斩波调零 Chopper
Auto-Zero Chopper
几个名词解释


- 我们常听到说反相输入比同相输入的失真表现更好，特别是对于轨
到轨输入运放而言，为什么？
- 当我们需要高输入阻抗的同相跟随器来缓冲一个大信号时，如何维
持一个很好总谐波失真 THD？
OPA365
Zero-Crossover, RRIO, 50MHz Single Supply Amplifier
• Zero-Crossover Input Topology • Excellent signal linearity over entire input

•Excellent THD+N: 0.0006% common mode range
•Excellent CMRR: 100dB
•Rail-to-rail input/output: • RRIO maximizes input dynamic range and
Input 100mV Beyond Supply Rails enables true 2.2V single supply data
•Low noise: 4.5nV/√Hz acquisition
• Speed:
• Speed and THD specs optimized for up to
•Gain bandwidth: 50MHz
250ksps unity gain buffer data acquisition
•Settling time: 300ns to 0.01%
• Low offset: 200µV
• 2.2V to 5.5V operation
• Single Supply Data Acquisition

• Security & Surveillance
• Handheld Test and Measurement
• Active Filters 1k Price:
• Audio Preamplifiers & Filters OPA365 Salley-Key Low Pass Filter
$0.95
• Precision signal conditioning
传统2级输入的轨到轨输入结构和零交越失真结构
Standard Two-Stage Input VSS
VSS-1.1V
VSS -
-IN
Q1 Q2
VSS-1.5V VCM
VOUT
Second
Stage
+IN
Q3 传统的轨到轨输入结构需要2级
Q4
VOUT
结构来使电压达到正电压和负
电压轨。而此2级输入结构会带
0V -
来过渡区附近的失调电压漂移，
Zero-Crossover Input Stage 从而导致电压锯齿
VSS+0.5V
Charge
Pump
VSS+0.1V 零交越失真的输入结构通过内
VSS
置一个充电泵来提升输入级的
偏置电压，因此只需要一级结
VSS -
-IN 构。从而消除了过渡区和其带
Q1 Q2
来的时域锯齿 VCM
VOUT
Second
+IN
Stage VOUT
0V -
GND-0.1V
传统2级输入的轨到轨输入运放的谐波失真
Frequency Spectrum (16384 Point FFT)

Fs = 262.1440 kHz Fin = 10.448000 kHz
20
-20
时域上的锯齿会带来频域上的高次谐波
-40
-60
dB
-80
-100
-120
-140
-160
SNR = 89.817 SINAD = 86.838 SFDR = 95.384 THD ( 9 ) = -89.879 ARL = 84.288
OPA365 零交越失真运放的谐波失真表现
Frequency Spectrum (16384 Point FFT)
Fs = 262.1440 kHz Fin = 10.448000 kHz
20
0
零交越失真结构不带来高次谐波，
-20
从而达到一个很好的THD指标
-40
-60
dB
-80
-100
-120
-140
-160
SNR = 90.143 SINAD = 89.905 SFDR = 103.068 THD ( 9 ) = -102.634 ARL = 84.288
精密运放的选型指南
供电电压设计要求典型应用推荐运放工艺推荐TI产品家族

R-R，低功耗，
Vs<=5V 便携，电池供电 CMOS OPA3xx, TLVxxxx
精密，小封装
R-R，低噪声，精密， OPA3xx, OPA7xx,

Vs<=16V 工业 CMOS
低偏置电压，小封装 TLCxxxx
低输入偏置电流，工业，测试设备，
Vs<=36V FET, Difet OPA1xx, OPA627
高输入阻抗光网络，高端音频
低输入失调电压，工业，测试设备，
Vs<=44V Bipolar OPA2xx, TLExxxx
低温漂光网络，高端音频
±5V to
XDSL，视频， Difet, BiCOM OPA6xx, OPA8xx,
±15V 双电双电源电压，高速应用
驱动ADC High Speed Bipolar, THSxxxx
源供电
1.8 V to 5.6V 消费电子，视频， OPA35x, OPA6xx,

单电源电压，高速应用 High Speed CMOS
单电源供电驱动ADC，医疗 THSxxxx, OPA8xx
差动放大器和仪表放大器
认识共模电压和差模电压
共模电压Common-Mode Voltage (CMV) – 运放V-和V+包含的相同的信号成分
差模电压Differential Voltage (VDIFF) – 运放V-和V+包含的不同的信号成分
(1.5V) VCM = (VIN++ VIN-) / 2

VDIFF/2 VIN+ = +6.5V VCM = [(+6.5V) + (+3.5V)] / 2 = +5V
+ _
-
VOUT
+ _ + VDIFF = VIN+- VIN-
VDIFF = (+6.5V) – (+3.5V) = +3.0V
+
VCM - VDIFF/2
VIN- = +3.5V
(5V) (1.5V)
差动放大器：抑制共模信号，提取差模信号
When R2=R1 = R4=R3 => Vout = (V1-V2) x Gain

共模抑制比 CMRR
共模抑制比 Common-Mode Rejection Ratio (CMRR) – 衡量差动放大器放大差模
信号（VDIFF）的同时抑制共模电压（CMV）的能力。通常用dB来表示，常介于
80dB和120dB之间. 越高越好. 如CMRR=Gdif/GCM, 一般是放大差模信号，Gdif为正
(dB)，共模信号是衰减，GCM为负(dB)，CMRR就会得到一个比较大的正数。
CMV Gdif
CMRR = 20 ∗ log CMRR =
∆Vos Gcm
我们希望所有的差动放大器:
► 仅仅放大差模信号
► 将共模信号完全抑制
但是所有的差动放大器都不能完美的抑制共模信号，会有CMRR这个指标：
► CMRR越小，共模信号引起的输出失调就会越大
差动放大器的CMRR由什么决定？
• 决定因素：外部电阻网络的匹配精度
• 如果R1,R2,R3,R4中的任意一只R有0.1%的误差, 差动放大器
的CMRR将降至2000:1, 或66dB
• 我们在零售市场最多可以买到1%精度的电阻，一个电阻的
1%误差将降低CMRR到46dB
• 而实验室里随手拿来的电阻可能是5%精度的...
R4 10k
V- 15
R3 10k
-
+
V2 R1 10k Vout
+
+ U1 OPA277
+
V1 V+ 15
R2 10k
TI的INA系列放大器家族
Instrumentation Amplifiers (INA)
Difference Amplifiers Instrumentation Amp Current Sense Amp

差动放大器仪表放大器电流检测放大器
INA：
差分输入的放大器家族
提供优异的共模抑制性能（High CMRR）
差动放大器 Difference Amplifiers
R1 R2
VOUT = (Vninv - Vinv)R2/R1
Vinv
R1 = R2 = R3 = R4
VIN+ -
VIN- VOUT
+
Vninv
R3 R4
CMRR = 20 ∗ log(x) ► 1% 的电阻精度 = 40dB

x = R4/(R3 + R4) * (R1 + R2)/R1 - R2/R1
► 0.1% 的电阻精度 = 60dB
优势: 高共模抑制比，宽输入共模电压范围
缺点: 降低的输入阻抗，低固定增益 ► TI提供的硅片级电阻匹配 = 100dB
三运放结构的仪表放大器 INA
VDIFF/2 VA1 = VCM - (VDIFF/2)(1+2RF/RG)
VIN-
+
+
_
RD RD
A1
-
RF
- VOUT = VDIFF(1+2RF/RG)
RG A3
RF
+ VOUT
+
VCM - -
+ _
A2 RD RD
VIN+ +
VDIFF/2
VA2 = VCM + (VDIFF/2)(1+2RF/RG)
优势: 极高的输入阻抗，高增益范围，高CMRR

缺点: 输入共模电压范围窄，和差动放大器相比增加的功耗、尺寸和成本
两运放结构的仪表放大器 INA
RG
RREF R1
RF
- R1 RF
A1
+
_
VIN-
+
VDIFF/2
-
A2
VIN+
+ _
+ VOUT
+
-
VCM
VDIFF/2
VOUT = VDIFF(1+2RF/RG + RF/R1) + VREF
VA1 = VCM(1+R1/RF) - (VDIFF/2)(1+2R1/RG + R1/RF) – VREF(R1/RF)
优点: 和三运放INA相比，低的成本，尺寸和功耗
缺点: 输入共模电压范围窄，随频率升高CMRR急剧降低，最小增益为2
两运放结构INA和三运放结构INA的比较
CMRR VS Frequency CMRR VS Frequency

两运放结构的INA 三运放结构的INA
差动放大器和电流检测放大器
Low Side Current Sensing
• Low side current sensing
– Current sensor element between the load and ground.
• Advantages
– Straightforward
• Rarely requires more than an op-amp to implement
– Inexpensive and precise
• Disadvantages
– Adds undesirable resistance in the ground path
– May require an additional wire to the load that could otherwise be
omitted
• When to choose low side current sensing

– When you CAN!
• Choosing low side current sensing is almost always the best option if your
application can tolerate the extra disturbance in the ground path.
High Side Current Sensing
• High side current sensing
– Current sensor element between the supply and load.
• Advantages
– Current sensor connected directly to the power source and can detect
any downstream failure and trigger appropriate corrective action
– Won’t create an extra ground disturbance that comes with a low side
current sensing design
• Disadvantages
– Requires very careful resistor matching in order to obtain an
acceptable common-mode rejection ratio (CMMR).
– Must withstand very high common-mode voltages
• When to choose high side current sensing

– When low side sensing is not an option due to the added ground
disturbance
– When cost is saved by eliminating wiring
Current Shunt Monitors
Current Shunt Monitors
– Special difference amplifier for the specific use of high side current
measurement.
– Measures the voltage drop across a resistor placed in the current path
between the supply and the load.
– Outputs a voltage, current or digital signal that is proportional to the
current through the measured path.
VCC 10V
5mOhm
Sense
DMV:10mV Current
+
CMV:10V to be RSHUNT V voltmeter
I=2A measured
-
Load 5Ohm
GND
Difference & Current Shunt Amplifiers
• A current shunt monitors are a unique class of high common-mode voltage
difference amplifiers which can be operated on single, low voltage supplies
• Compare with normal resistor difference amplifiers:
Strength: Common-mode range not related to supply voltage

Limitation: Different ranges of operation performance
Limitation: Few uses outside current measurement
TI INA选型指南
高共模抑制比放大器
INAy13x/10x: 差动放大器，电阻网络内置，无输入缓冲，
供电<=36V， BW up to 5MHz, 输入CMV up to ±200V
INAy2xx/19x/16x: 电流并联监视器，供电<=36V，
BW up to 34MHz, 输入CMV from -60V to 80V
INAy11x/12x: 仪表放大器，高输入阻抗，高放大倍数
供电<=36V， BW up to 800KHz (Gain = 100)
INAy3xx: 仪表放大器，CMOS，供电<= 5.5V，轨到轨，自归零，
低噪低功耗，BW up to 800KHz (Gain = 100)
推荐型号：
差动放大器： INA133, INA137(DIP)
仪表放大器： INA333, INA128(DIP)
电流检测放大器：INA271, INA282
TI 其他的精密放大器
功率放大器：
• OPA4xx: 宽供电范围， up to 100V，输出电流至50mA, BW <= 10MHz
• OPA5xx: 高输出电流， up to 10A，供电 up to 80V, BW <= 20MHz
增益可控放大器：
• PGA11x：数字程控增益放大器, BW up to 10MHz, 放大倍数2进制或10进制可调
其他放大器
• XTRxxx： 4-20mA 发射器； RCVxx: 4-20mA 接收器
• LOGxxx：对数放大器
• IVCxxx：积分放大器
• DRVxxx：驱动放大器（PWM，线路驱动等）
• ISOxxx：隔离放大器
• VFCxxx：电压到频率，频率到电压转换器
• TLC04： 4阶butterworth开关电容滤波器，截止频率fc＝clk/50，fc高至40KHz
• UAF42：通用滤波器
Agenda
• TI Overview
精密信号链举例与 ADC
2009 TI Winter Camps Topic 1
• Resistor Bridge Excitation and Condition
• Requirements:
- Using Resistor Bridge to detect un-known Resistor: Range from 5k to 20k
- Build 100uA Constant Current Source to drive the Bridge
- Condition the Bridge’s output
- Data Acquisition and Analysis
IS1 200u
• Precision Current Source

R1 10k R3 10k • CMV Rejection and DMV pick up
+
• Bipolar Signal to Unipolar ADC
V
R4 9k VM1
R2 10k
Howland Current Source using INA137
Right!
Right!
Wrong! Always use a Buffer to drive
INA’s VREF Pin!
CMV Rejection and DMV Amplify
Resistor Range from 5k to 20k:

Bridge Output CMV from 285mV to 600mV
CMV contains no useful information and waste our dynamic range, Reject it!
Bridge Output DMV from -143mV to 200mV

ADC12 with LSB=1mV only give counts of 343, far away from 2500
DMV contains useful information but too small, Amplify it by 10x!
Level Shift to Satisfy unipolar ADC
INA128 Output = (INAV+－INAV-)*(1+50k/R8) + VREF,

= (INAV+－INAV-)*2 + 2.5
Opa335 Output = (INAV+－INAV-)*(1+50k/R8)*(-R10/R9)+VREF,
= -(INAV+－INAV-)*2*5 + 2.5
* Always Drive INA’s VREF Pin with Low impedance source, such as a Buffer
* Never exceed INA128’s Output Range
Amplifier Solutions:
(Vout − 2.5)
R I G1 −
2
× 3R
R 2= 10
(Vout − 2.5)
RI G1 +
10
(Vout − 2.5)
Bridge Output DMV =
10
AD Conversion and Analysis
Required Accuracy
• Unknown Resistor Range: 5k – 20k ohm
• Required Accuracy: 6 ohm (2500 counts, 11.28bits)
Theoretical Resolution
• Amplifier Final Output: 500mV to 3.93V
• ADC12 with a 4.096V VREF has a LSB = 1mV
• ADC12 can give a counts of (3.93V-0.5V)/1mV = 3430, 11.74bits
When theoretical Resolution > Required Accuracy,

Theoretically, we meet the Requirements.
We need to control the system noise < ADC12’s LSB to turn the Theoretical
Resolution to Achieved Accuracy!
12 bit ADC: let’s use MSP430’s internal ADC12 (200ksps)!

ADC Architectures
• ADCs
– Delta Sigma: DC or Audio Apps
– SAR: DC and KHz Signal Apps
– Pipeline: Wideband Apps, like CI and Video
– Flash: Ultra-High Speed, like Oscilloscope
32
24 ~ MSP430
DS
Converter Resolution (bits)
20
Delta Sigma
MSP430
16 DS
C2000
12
SAR SAR
MSP430 Stellaris
SAR SAR Pipeline
8
10 100 1K 10K 100K 1M 10M 100M 1G
Texas Instruments
Conversion Rate (SPS)
Successive Approximation ADC
VIN S/H + FS: Full Scale

- FS
fS
SAR and
Clock
Control Logic
FS
Data Out
MSB
2
LSB
0
D/A Converter Ref
MSB LSB
Advantages: Disadvantages:
•General purpose •Requires N sequential comparisons
•Cost effective •Low to moderate speed
14-13
Successive Approximation ADC
TI Analog Overview: SAR ADC
•16-Bit, 1MSPS,
•Serial SPI
ADS8400/03
•16-Bit, 1MSPS
•ADC+OPA MUX ADS8254/55
AMC1203R:
•18-Bit, 1MSPS
•ADC+OPA MUX ADS8284/85
•16-Bit, 6kV
Higher Resolution & Higher Speed
•16-Bit, 500kSPS, Serial ADS8318/19

SPI ADS8556/7/8
•16-14-/12-Bit Family
ADS788x • ±10V Input, 1x6 SS, SPI
•12-Bit, 3MSPS, Parallel
ADS7863/65:
•12-Bit, 3x2 SS
•1.5MSPS, SPI/Parallel ADS8500:
•16-Bit, SPI, Small
•±10V
ADS8517/14
•16-Bit
• HPA07HV
•±10V / ±12V
SAR
ADC
Product ADS795X: ADS8331/32
Portfolio •12-/10-/8-Bit Family •16-Bit Family
•1MSPS, 4-/8-/12-/16-Ch, SPI •250kSPS, 4-/8-Ch
Increasing Performance, Improved INL and Lower

Power
Successive Approximation ADC Portfolio
Simultaneous
Economic Highest Precision
Sampling
8 - 16 bit 12 - 18 bit 12 - 16 bit
ADS7229 ADS8422 ADS786x

ADS795x ADS8284/5 ADS836x
ADS8317 ADS788x ADS85xx
ADS833x
Motor control
General Purpose High resolution data 3 phase Power Control
low power acquisition Multi Axis positioning
small size Fast high resolution control Power Quality
Multichannel loop
up to 1MSPS up to 4MSPS up to 1MSPS

Using Delta-Sigma ADC to simplify your Design
INA & OPA functions
CMV Rejection + DMV Amplify + Level Shift
Is there a kind of ADC to achieve all these three functions?

CMV Rejection
• Determined by Input Types:
- Single Ended Input : Low Resolution SAR
- Pseudo-Differential: High Resolution SAR
- Differential: Delta-Sigma, a few SAR
Single-Ended Inputs
+V
ADC
-V
(optional)
Pseudo-Differential Inputs
• More like a single-ended input than
differential, but with some advantages. +5V
• IN- pin can move, but in a limited
VIN+
range (typically -0.2V to 0.2V, +
sometimes up to a volt or two). ADS7869
• Good for removing common-mode -
Common VIN-
voltages, offsets, etc. Mode
• Provides a “clean” signal reference Voltage VREF
(CMV)
point.
AIN(+)
ADC DAC
AIN(-)
+/- 200mV Maximum

Differential Inputs
(VIN+)-(VIN-)=+VREF
+5V
VCM+VREF/2 VIN+ VIN-
VIN+
+
Common
ADS7869 VCM
Mode -
Voltage VIN- VCM-VREF/2
(CMV) |VREF|
VREF (VIN+)-(VIN-)=-VREF
0V
• With Differential inputs, Delta-Sigma ADC can reach CMRR up to 100dB at DC, even can reach up to 130dB
at 50/60Hz by the help of Digital Filter (at dedicate Sample Speed and Filter Response).
• VIN+ Can be either greater or smaller than

VIN-. ADC’s output will give positive and
negative numbers
How Delta Sigma ADC achieve 24 bits?
∆∑ Digital filter and
Modulator decimator
Analog Input Multibit output
1 bit Fdata
Fmod
•The single bit output from the modulator is simply a PWM signal who’s duty cycle
represents the analog input signal
•The digital filter changes this single bit, high speed signal into a multi bit, slower speed
signal
The Frequency Domain
Signal amplitude
Power
SNR = 6.02N + 1.76dB ; (for an N-bit ADC

Sine wave input)
Quantization Noise
Average noise floor (flat)
FS / 2 FS
Frequency
Oversampling by K Times
Power
Oversampling by K times
SNR = 6.02N + 1.76dB ; (for an N-bit ADC
Sine wave input)
Same total noise, but spread over more frequencies
Average noise floor
k FS / 2 k FS
Frequency
The Digital Filter
Ideal digital filter response
Oversampling by K times
Power
SNR = 6.02N + 1.76dB + 10 log(Fs/2*BW)
Noise removed by filter
BW k FS / 2 k FS
Frequency
Noise-Shaped Spectrum
Signal Amplitude
SNR = 6.02N + 1.76dB

Power
The integrator serves as a

highpass filter to the noise.
The result is noise shaping
k FS / 2 k FS
Frequency
Filtering the Shaped Noise
Signal amplitude
Digital filter response

Power
HF noise removed
by the digital filter
k FS / 2 k FS
Frequency
Delta-Sigma ADC Portfolio
Economic Highest Precision Integration Wide Bandwidth
12 - 16 bit 16 - 31 bit 16 - 24 bit 16 - 24 bit
ADS111x ADS128x ADS124x ADS16xx

ADS101x ADS1259 ADS123x
ADS120x ADS1278 Integration for sensor
application
AMC12xx (iso)
Low Power Integration for
Small Package 130 dB SNR motorcontrol Vibration analysis
MultiChannel up to 8 ch. simult. application Test & Measurement
Modulator only Low Latency (42μs/ch)
up to 3.3kSPS up to 128kSPS up to 2kSPS Up to 10 MSPS

High Resolution eliminated Amplifier
• Aims: 10 ohm Resolution in a 25k ohm Full Range, that is 2,500 steps
• The Sensor Output: 343mV full scale
• The step size without amplify: 343mV/2500 = 137.2uV
A 16bits ADC (ADS1146/1147) with 2.048V VREF: 1ku / $2.70
when works at 20SPS, PGA=1, ADS1148’s ENOB = 16bits (65536)

LSB = 4.096V/65536 = 62.5uV < 137.2uV, or
Effective Resolution: 343mV/ 62.5uV = 5488 !
And, we can further use the internal PGA of the ADC to get more resolution.
ADS1146
16-Bit, Single-Channel Temperature Measurement ADC
Device Features: • High Performance Capabilities Coupled with On-

• 1 Differential or 1 Single-Ended Chip Integration
• True Bipolar ± 2.5V or Unipolar 5V
• Max Data Rate – 2kSPS • Cost Effective Temperature Sensor Measurement
Solution
• Low Noise PGA: 40nV @ G = 128
• 50/60Hz Simultaneous Rejection Mode (20SPS) • TRUE Bipolar Inputs Reducing Front End Signal
Conditioning Circuitry
On-Chip Integration:
• Oscillator • Family options for scalable channels/integration
• Temp Sensor
• Burnout Detect
• Pin compatible to the 24 Bit ADS1246
• Temperature Management
– RTDs, Thermocouples, Thermistors
• Flow/Pressure Measurement
• Industrial Process Control
1ku / $2.70
16-Pin TSSOP
ADS1147/48
16-Bit, Complete Temperature Measurement ADC
Device Features: • Ultimate Temperature Sensor Measurement

Solution
• 2/4 Differential or 3/7 Single-Ended
• True Bipolar ± 2.5V or Unipolar 5V • Most Flexible Front End for a Wide Range of
• Max Data Rate – 2kSPS Industrial Sensors
• 50/60Hz Simultaneous Rejection Mode (20SPS) • High Integration Without Compromising
Performance
On-Chip Integration:
• Family options for scalable channels/integration
• Low Drift Internal Reference (10 ppm/℃ Max)
• Dual Matched Current DACs (50 – 1500 μA)
• Oscillator, Temp Sensor, Burnout Detect
• 4/8 GPIO’s
• Pin compatible to the 24 Bit ADS1247/8
ADS1147 1ku / $3.45
ADS1148 1ku / $3.95
20/28-Pin TSSOP
Solution Using Delta Sigma ADS1147
ADS1147 Integrated IREF
R1 10k R3 10k
+5V
VIN+
+
R2 5k R4 10k ADS1147
-
VIN-
ADS1247 and ADS1248
24-Bit, Complete Temperature Measurement ADC
Device Features: • Ultimate Temperature Sensor Measurement

• 2/4 Differential or 3/7 Single-Ended Solution
• Most Flexible Front End for a Wide Range of
• Max Data Rate – 2kSPS Industrial Sensors
• 50/60Hz Simultaneous Rejection Mode (20SPS)
• High Integration Without Compromising
On-Chip Integration: Performance
• Low Drift Internal Reference (10 ppm/℃ Max) • Family options for scalable
• Dual Matched Current DACs (50 – 1500 μA) channels/integration
• Oscillator, Temp Sensor, Burnout Detect
• 4/8 GPIO’s
• 16-Bit version: ADS1147/48
ADS1247 1ku / $4.45
EVM
ADS1248 1ku / $4.95
ADS1248EVM 20/28-Pin TSSOP
ADS1246
24-Bit, Single-Channel Temperature Measurement ADC
Device Features: • High Performance Capabilities Coupled with

• 1 Differential or 1 Single-Ended On-Chip Integration
• Max Data Rate – 2kSPS • Cost Effective Temperature Sensor
• Low Noise PGA: 40nV @ G = 128 Measurement Solution
• 50/60Hz Simultaneous Rejection Mode (20SPS)
• TRUE Bipolar Inputs Reducing Front End
On-Chip Integration: Signal Conditioning Circuitry
• Oscillator
• Family options for scalable
• Temp Sensor
channels/integration
• Burnout Detect
• 16-Bit version: ADS1146
1ku / $3.45
16-Pin TSSOP
ADC Checklist
1) SPEED (Sample Rate)_______ and RESOLUTION____ bits
Which one is more important? S or R
Is there a preferred Architecture? D-S, S, P
Analog Supply Voltage AVDD ____
Reference Voltage VRef ____ Digital Supply Voltage DVDD ____
111
2) Analog Input AiN 110
101
3) Digital Output DOUT
Output Code
100
011 Interface:
Number of Channels _____ 010 Serial/SPI
Muxed or Simultaneous 001 I²C
Single Ended or Differential 000 Parallel
Unipolar or Bipolar 0 1 2 3 4 5 6 7 LVDS: Serialized or Parallel
Input Voltage Range _____
Input Voltage
Notes:
Power Budget: Is Size a Concern: Processor/FPGA:
Sample Need Date: Production Need Date: Cost Goal: Volume:
10
Understand ADC Analog Inputs
• Number of Channels _____
* Muxed or Simultaneous
• Single Ended or Differential
• Unipolar or Bipolar
* Input Voltage Range _____
• Band-Limiting your Analog Input
Number of Input Channels
– What is meant by 4 SE or 4 Diff?
Multiplexer
ADC
– What is meant by 3x2 Diff?

Multiplexer
ADC
Multiplexer
ADC
ADS795X Family 12-/10-/8-Bit, 1MSPS
Multi-Channel, Low Power, Serial ADC Family
• Precision SAR ADC Performance Ø Excellent Linearity and AC performance for high-
- 1MSPS - 12-Bit Resolution density multi-channel applications in a small form
- ±1 LSB MAX INL factor
- ±1 LSB MAX DNL
- 70dB MIN SNR @ 100kHz Input
Ø Designed to deliver maximum performance in
• Flexible Supply Ranges battery and low voltage applications
- Digital Supply – 1.8V to 5.25V
- Analog Supply – 2.7V to 5.25V Ø Designed for a glue-less connection to modern
day processors and DSPs with low voltage IO
• Flexible Muxed Inputs PGA11x
- ADS7950 – 4 channel
- ADS7951 – 8 Channel
PGA
• Hand Held Medical Instruments

• Programmable Logic Controllers
• Digital Power Supplies
EVM
ADS795X EVMs
Available Soon
PGA112/PGA113
RRIO, Single Supply, Single Ended, PGA w/2 ch Mux
§ Zero Drift and RRIO § Best for low offset, RRIO, wide BW, single supply apps
§ PGA112 (Binary gain): 1, 2, 4, 8, 16, 32, 64, 128 § Allows for optimum A/D range matching for a wide
§ PGA113 (Scope gain): 1, 2, 5, 10, 20, 50, 100, 200 variety of input signal amplitudes
§ 4 internal calibration channels § Allows easy system calibration for gain and offset
§ Software shutdown (Iq < 4µA) § Ideal for power sensitive applications
§ AVDD and DVDD supply in 2.2V to 5.5V range § Perfect for mixed voltage systems
§ VCLAMP pin to clamp output § Prevents downstream latchup in mixed voltage systems
§ Low noise, low Ib, low offset, low Iq
§ Extended -40°C to +125°C Temp Range
§ 10-MSOP Package w/ SPI interface
§ Portable Data Acquisition

§ PC Based Signal Acquisition 1ku Price:
§ Test and Measurement $0.97
§ Programmable Logic Controllers
§ Handheld or Battery apps MSOP-10 Package
12 bit SAR with gain
ADS7951,12-bit SAR with OPA350
MXO
+ SDO
CH0
CH1 100 Ω
Converter SDI
CH2 OPA350
CH3 AINP SCLK
Multiplexer
CH4 -
15R 1n
CH5 CS
CH6
CH7
R
VREF
REF
ADS7951
12 bit SAR with gain
ADS7951,12-bit SAR with OPA350
MXO
SDO
CH0
CH1 100 Ω
Converter SDI
CH2 PGA11x
CH3 AINP SCLK
Multiplexer
CH4 1n
CH5 CS
CH6
CH7 Digital Controlled Gain
Rail to Rail I/O
Auto Zero, Zero Drift
REF
ADS7951
同时采样保存了相位信息
• 在时点 t1，两个信号均进行
信号 1
采样，因而保存了相位信息，
在电动机控制和 I/Q 调制等
应用中，这是至关重要
信号 2 • 相位差等于一个频率偏移或
一个时间延迟
t1
ADS7863
2-MSPS, 12-bit, 2/3x2 channel simultaneous ADC
• Four Fully- or Six Pseudo- Differential • Configurable input modes

Inputs • Easy upgrade option for existing
• Pin Compatible with ADS7861 and designs
ADS8361 (SSOP) • Simple connectivity to any host
• Flexible digital supply (2.7V – 5.5V) processor or DSP
• Programmable reference output • Low power consumption
• Low Power Operation: 40mW at 5V • Excellent measurement repeatability
• Excellent drift performance over Operating Temperature range
• Gain drift 1ppm/°C
• Offset drift 0.6ppm/°C
• Motor Control
• Multi Axis Positioning System
• Three Phase Power Control
EVM
EVM PART #: 1ku / $4.90
Available Soon
Single-Ended Inputs
+V
ADC
-V
(optional)
Pseudo-Differential Inputs
• More like a single-ended input than
differential, but with some advantages. +5V
• IN- pin can move, but in a limited
VIN+
range (typically -0.2V to 0.2V, +
sometimes up to a volt or two). ADS7869
• Good for removing common-mode -
Common VIN-
voltages, offsets, etc. Mode
• Provides a “clean” signal reference Voltage VREF
(CMV)
point.
AIN(+)
ADC DAC
AIN(-)
+/- 200mV Maximum

Differential Inputs
(VIN+)-(VIN-)=+VREF
+5V
VCM+VREF/2 VIN+ VIN-
VIN+
+
Common
ADS7869 VCM
Mode -
Voltage VIN- VCM-VREF/2
(CMV) |VREF|
VREF (VIN+)-(VIN-)=-VREF
0V
• With Differential inputs, Delta-Sigma ADC can reach CMRR up to 100dB at DC, even can reach up to 130dB
at 50/60Hz by the help of Digital Filter (at dedicate Sample Speed and Filter Response).
• VIN+ Can be either greater or smaller than

VIN-. ADC’s output will give positive and
negative numbers
Unipolar
• Signal stays above 0V 2.5

2
32768
24576
(ground) at all times. 1.5
1
16384
• Output code has only 0.5

0
8192
0
AINP
BTC
positive values. -0.5 0 36 72 108 144 180 216 252 288 324 360
-8192
-1
-16384
-1.5
-2 -24576
-2.5 -32768
Bipolar
• Signals swings above 2.5

2
32768
24576
and below ground (0V). 1.5
1
16384
• Output code has both 0.5

0
8192
0
AINP
BTC
positive and negative -0.5 0
-1
36 72 108 144 180 216 252 288 324 360
-8192
values. -1.5
-16384
-24576
-2
-2.5 -32768
ADS850X Family ±10V HV Bipolar Rtn
SAR
Drop-in Upgrade for The ADS780X Family
• Drop In Upgrade to The ADS780X Ø Improved Performance For Existing Systems

• Designed in Cutting Edge HPA07 Process Without Costly Redesigns
• Excellent AC Performance (THD) Ø Improved Resolution For High Dynamic

- ADS8504 – 6dB better than ADS7804 Range Signals When Upgrading
- ADS8505 – 2dB better than ADS7805 Ø Best In Class Performance For New Designs
- ADS8508 – 6dB better than ADS7808
• Best In Class Stability (ADS8507) Ø Excellent Measurement Repeatability Over

- Full Scale Error Drift 5ppm/°C Operating Temperature
- Bipolar Zero Error Drift 0.5ppm/°C
Ø No Probe In-Package Trim That Results In
• Latest Generation E-Trim Technology Better Initial Accuracy and Long Term Stability
ADS8507

• Data Acquisition Systems
• Test Equipment
EVM
ADS850X EVMs
Available Soon
Low-Pass Filter Missing
2nd order
Low-Pass Filter
C1
R6
TMS320C6713
+
R5
C2 OPA340 ADC
−
Noise Reduction with Low-Pass Filter
0 dB Noise
Bandwidth
Sallen-Key
of IA
20 dB C1
2nd Order, R2
VIN
+
VOUT
40 dB 10 Hz Filter R1 C2 -
60 dB
74 dB
80 dB
10 Hz 1 kHz 10 MHz
Sampling Frequency of
A/D Converter
Analog Section Schematic Final
Wall Wart
VDD
Two-op amp 9V DC out
A6 Instrumentation Amplifier
R3 RG uLM
REF2925
78
2.5V R4
Reference A5
R3 2nd order VDD = 5V
VDD Low-Pass Filter
VDD C1
- R4
to TMS320C6713 DSK
R1 R2 - R8 A4
+ A1 +
R2 R1 R7
+ A2 C2 OPA340 ADS7829
LCL- -
816G A3
1/2 of
OPA2335
Carefully Treat Your Ref Input
Treat Reference Voltage VRef

as an important Analog Input!
1. Filter Vref Input

2. Use Amplifier Buffer to improve setting time
Designing Mixed Signal Systems with
Noise Reduction Techniques in Mind
Author: Bonnie Baker

The Analog Signal Chain
Power
Supply SVS
Power
Distribution
AMP
SENSOR ADC DSP/µC
Analog Section Schematic #1
Wall Wart
9V DC out
VDD Two-op amp
A6 Instrumentation Amplifier uLM
78
REF2925
R3 RG
A5
2.5V R4 VDD = 5V
Reference
VDD R3
VDD
- R4
to TMS320C6713 DSK
A4
R1 R2 - DCLOCK
DOUT
+ A1 ADS7829
CS/SHDN
R2 R1 + A2
LCL-
816G 1/2 of
OPA2337
Component Values
• Resistors around Instrumentation Amplifier
– R3 = 400 kΩ
– R4 = 100 kΩ
– RG = 5.33 kΩ
• OPA2337 = Single Supply, CMOS, dual OPA
• ADS7829 = 12-bit, A/D SAR Converter

Analog Layout #1
ADC
Op Amp
Circuit
Sensor
Board #1 Bottom
1st Pass Test Results
90
80
Number of Occurrences
70
60 Code Width
50 of Noise = 44
40
30 (total samples = 1024)
20
10
0 How many bits?
2960 2970 2980 2990 6.54-bits

Output Code of 12-bit A/D Converter
Proactive Design Approach
• Define Required Accuracy up Front
– Maximum weight – 32kg
– Resolution – 10g (~11.65-bits)
– Accuracy – 20g (~10.65-bits)
• Where Did all the Noise Come From?
– Devices?
– Emission or Radiation?
– Poor PCB Layout?
Where to Look - Overview
• Device Noise - Created by the devices
• Emitted Noise - Externally Injected
• Conducted Noise –
In the Circuit Traces
Where to Look – Device Noise
• Passive Devices
– Resistor
– Capacitors
– Inductors
– Ferrite Beads
• Active Devices
– Operational Amplifiers
– A/D and D/A Converters
– Voltage References
– Voltage Regulators
– Switching Power Supply
Resistors and OpAMP Noise
• Resistors
– All Resistors Generate Noise
– Resistor Noise Called Johnson or Thermal Noise
– Ideal Noise = VRN = 4KTR(BW) {Vrms}
• Ideal 1 kΩ ⇒ 4 nV / √ Hz
Resistors and OpAMP Noise
• Amplifiers
– OPA2337 Specification
6 µVP-P (f = 0.1 Hz to 10 Hz)
– OPA2335 Specification
1.4 µVP-P (f = 0.01 Hz to 10 Hz)
1 / f noise
nV/ Hz
(log)
Broadband
Noise
Frequency (log)
Schematic #2 Device Changes
• Resistors around Instrumentation Amplifier
R3 = 400kΩ ⇒ 40 kΩ
R4 = 100kΩ ⇒ 10 kΩ
RG = 5330 Ω ⇒ 533 Ω
• OPA2337 ⇒ OPA2335
6 µVP-P ⇒ 1.4 µVP-P (f = 0.01 Hz to 10 Hz)
• ADS7829 = 12-bit, A/D SAR Converter

Radiated Noise: B-Field
• Sources (Transmitters)
– On Board Transformers
– Switching Regulators
– External Noise
• Victims (Receivers)
– Single-ended, High Impedance Inputs
– Traces that a Form Circle
• Classic Example : Ground Loop
• Signal Loop
– Long Traces (acts like an antenna)
Traces That Form a Loop
Signal Path
Incorrect Ground
Connection
Ground
Radiated Noise: Long Traces
• Trace going into 10-bit or 12-bit ADC input is
longer than a few inches
Emitted Noise
PCB Capacitance : E-Field
PCB Trace
w • L • eo • er
C = pF
d
d
L
dV
I = C amps
dt w
(typ 0.003mm) PCB
Cross-Section
w = thickness of PCB trace
L = length of PCB trace
d = distance between the two PCB traces
eo = dielectric constant of air = 8.85 X 10-12 F/m
er = dielectric constant of substrate coating relative to air
PCB Coupling Noise Reduction
w • L • eo • er
• Decrease “L” or Increase “d” C =
d
pF
• Put Ground Guard Between Traces

Guard Trace
Voltage IN PCB Trace
Coupled
Current
d
L
dV
I = C (amps)
dt
Analog Section Schematic #2
Wall Wart
9V DC out
VDD Two-op amp
A6 Instrumentation Amplifier uLM
78
REF2925
R3 RG
A5
2.5V R4 VDD = 5V
Reference
VDD R3
VDD
to TMS320C6713 DSK
- R4 A4
R1 R2 - DCLOCK
DOUT
+ A1 ADS7829
CS/SHDN
R2 R1 + A2
LCL- 1/2 of
816G OPA2335
Analog Layout #2
REF
OPA
ADC
Sensor
System #2 Changes
• Device issues
– Reduced resistors by 10 X
– Replaced amplifier with lower noise version, OPA2335
• Radiation issues
– Extra Circuits Removed
– Loops Removed
– Eliminated digital to analog trace coupling
– Traces shorter
Board #2 Test Results
Code Width
of Noise = 6
(total samples = 1024)
Where to Look – Conducted Noise
• Conducted Noise is in the Circuit Traces
– Ground and Power
• 50 Hz or 60 Hz
• Ground and Supply Current Return Paths
– Signal Path
• Digital Switching
• Noise generated by previous device
• Solutions to Conducted Noise
– Replace noisy devices
– Reorient emitters
– Use a Continuous Ground Plane
– Filter Signal traces
– Filter Supply traces
Discontinuous Ground Plane
• Example of an Interrupted Ground Plane on the
Back Side of the Board
bottom top
Bypass Capacitor Types
ESR
• Filters Noise at High Frequency
– Ceramic - Small Case size, Inexpensive, ESL
– Good Stability, Low Inductance
C
• C0G
• X7R
• Acts as a Charge Reservoir for Fast Changes

– Tantalum Electrolytic - Small size,
– Large Values,
– Medium Inductance
Bypass Capacitors for Analog
12-bit A/D Converter Capacitor Response

0
Impedance (Ω)
1M 1nf
-20 100k Ceramic
PSR (dB)
10k 0.01µf
-40 Ceramic
1k
-60 100
0.1µf
10 Ceramic
-80
1
1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
Assume: Supply = 5V ± 20 mV (all white noise)

– To bring the noise to ± 1/4 LSB (± 0.61 mV)
– PSR < - 30.3 dB
Low-Pass Filter Missing
2nd order
Low-Pass Filter
C1
R6
TMS320C6713
+
R5
C2 OPA340 ADC
−
Noise Reduction with Low-Pass Filter
0 dB Noise
Bandwidth
Sallen-Key
of IA
20 dB C1
2nd Order, R2
VIN
+
VOUT
40 dB 10 Hz Filter R1 C2 -
60 dB
74 dB
80 dB
10 Hz 1 kHz 10 MHz
Sampling Frequency of
A/D Converter
Analog Section Schematic Final
Wall Wart
VDD
Two-op amp 9V DC out
A6 Instrumentation Amplifier
R3 RG uLM
REF2925
78
2.5V R4
Reference A5
R3 2nd order VDD = 5V
VDD Low-Pass Filter
VDD C1
- R4
to TMS320C6713 DSK
R1 R2 - R8 A4
+ A1 +
R2 R1 R7
+ A2 C2 OPA340 ADS7829
LCL- -
816G A3
1/2 of
OPA2335
Analog Layout Final
REF
Sensor
OPA ADC
System #3 Changes
• 2nd Order Analog Filter Added
• Bypass capacitors included
• Has a Ground Plane
• Signal Path more Stream-lined
• Length of traces further reduced
Board #3 Test Results
Code Width
of Noise = 1
(total samples = 1024)

Noise in the Analog World
• The Noise will NEVER be Equal to Zero
– Wise Layout Implementation
– Devices Selection
– Analysis of Environment
• Noise Reduction Rules of Thumb
– Bypass all Components
– Always use a Ground Plane
– Current Return Path Evaluation
DACs
DAC Technologies
20
DS
16
R-2R
String Current
12 Steering
~
~
8
10000 10 8 6 4 2 0.1 0.01
Settling Time- µs
Precision D/A converter portfolio
8 – 16-bit 8 – 16-bit 14 – 18-bit
General Purpose
Bipolar Output High Accuracy
Single supply Multiplying
Low power
DAC76xx DAC88xx
DAC75xx DAC77xx DAC9881
DAC85xx DAC78xx
DACx311/DAC8411 DAC88xx
TLVxxxx TLCxxxx
• Closed loop servo control
• Industrial process control • Industrial control PLC
• Data acquisition systems
• Automatic test equipment • Digitally controlled calibration
• Portable test equipment
6 – 10 us settling time 0.1 – 10 us settling time 0.5 – 5 us settling time

SPI I2C I2C SPI PAR SPI
dual quad octal dual quad dual quad

TI Analog Overview: Precision DAC R2R
DAC883x
Low Power
Special Function Components MDAC

Analog Monitoring and Control (AMC) DAC78/88xx
Higher Resolution & Higher Speed
String
DAC751x/853x
DAC754x/854x
DAC755x/757x
DAC855x/856x
TLV5636/5638
R2R
DAC77xx
DAC76xx
DAC
Product MDAC
Portfolio DAC78/88xx
Increasing Performance, Improved INL and Lower Power

BACK
MDAC Example: Signal Attenuator
±18V, 10MHz
±18V, 10MHz
VREF Code Vout

× =−
R 4096 RFB
RFB = R
Code
Vout = −VREF ×
4096
MDAC Example:
Digital Programmable Gain Amplifier
MDAC Example, Digital Multiply:
AM Signal Generator or Digital Mixer
Sine Wave up to MHz

DC Signal
Digital Sine Wace

Control Words
Update Rate up to 20MSPS
AM Signal or
Mixed Sine Wace
Digital Square/Sine Wace

Control Words
Update Rate up to 20MSPS
Agenda
• TI Overview
高速放大器
The Real Op Amp RMB!
Ÿ Bandwidth = 1 kHz to 1 GHz
Specifications: Ÿ Slew Rate = 0.1-800 V/ms
Vcc +
Speed Ÿ Gain = 25,000 to 167 dB
Ÿ Output Impedance = 1-1kohm
Ib Is Ÿ Input impedance = 106 ohm ,2-20pF
v2 Ÿ Noise =1-1000 nV/ÖHz
- - Ÿ Offset Voltage = .5 uV-
VIN Ÿ Offset Current = 30 pA-50nA
A
Ÿ Bias Current = 10 fA-250nA
+ + Precision Ÿ Supply Current 1mA-100mA
v1 + Vos - Is Ÿ CMRR = 50-130 dB
Ib Ÿ PSRR = 50-145 dB
Ÿ Voltage Swing = Vcc+ - Vcc-
Vcc - Ÿ Output Power = 0.1-500W
Drive
Capacity
11
Bandwidth – Small Signal Frequency Response
GBP (Gain Bandwidth Product)
• VFB Amp usable bandwidth depends on the gain configuration
• Gain * Bandwidth = GBW product
• For example
a) If an amplifier has a 1MHz GBW product
b) It only has a bandwidth of 10KHz in a gain of 100x
• Note: GBP is not quite true for current feedback amplifiers

Never use an Amplifier near GBP
Slew Rate: Determined Large Signal Bandwidth
• Slew Rate Determines the Limit of Large Signal Bandwidth

Bandwidth & Slew Rate
Buffer for a 10MHz Sinewave with 500mVpp Amplitude => SR needs 30V/uS
SlewRate 5Vpp Amplitude => SR needs 300V/uS
Bandwidth =
2π V pp
SlewRate = 2π V pp ⋅ BandWidth
500mVpp
GBW = 280MHz
SR = 240V/uS 5Vpp
Types of High Speed OPA – VFB & CFB
Simplified VFB Model
Simplified CFB Model
VFB vs. CFB: Bandwidth-Gain Relationship
Voltage Feedback (VFB) Circuit Current Feedback (CFB) Circuit
 
 
Vo  R1 + R2   1 
≅ 
Vi  R1   R1 + R2   j2πfCc  
1+   
16   R1   gm  
Gain (V/V)
Gain (V/V)
8
1
6.3M
25M
50M
12.5M
100M
-3dB BW = 100MHz / Gain
100M
Bandwidth is Dictated by gm (fixed by design) Bandwidth is Dictated by R2
and Gain – Hence Gain Bandwidth Product (Feedback Resistor)
VFB vs. CFB: Slew Rate
Buffer for a 10MHz Sinewave with 5Vpp Amplitude => SR needs 300V/uS
SlewRate
Bandwidth =
2π V pp
SlewRate = 2π V pp ⋅ BandWidth
Small Signal BW
@ G=1: 280MHz
GBW = 280MHz Large Signal BW
CFB @ G=1: 200MHz
VFB SR = 240V/uS
SR = 2100V/uS
VFB vs. CFB: Slew Rate
VFB CFB
Most High Speed VFB have a Slew Rate < 500V/us
Most Precision VFB have a Slew Rate < 30V/us
Some TI Leading Technology VFB (OPA690) can reach Slew Rate near 2000V/uS
Selecting Feedback Resistor for CFB
CFB With a Feedback C
Compensate CFB with a Lager RF
High Speed Apps:
VFB vs. CFB: What to Use and When
Ø Gain <=3 : VFB is typically better
– VFB has lower noise in low gains due to low inverting current noise
– VFB has Gain Bandwidth Product limits to high frequency operation
– VFB typically has better distortion at lower gains
VFB CFB
G=1 G=3 G=4 G=∞
Ø Gain =>4 : CFB is typically better

– CFB has lower noise due to lower Rg resistor value in high gain
– CFB does not have Gain Bandwidth Product limitation
– CFB typically has better distortion at higher gains
Caveat: De-compensated VFB Amps may be an alternative

High Speed Apps:
VFB vs. CFB: What to Use and When
Ø Frequency of Interest <= 10MHz
– VFB has better distortion at lower frequency
– VFB can be used for all filters and as integrators
– VFB has Better DC accuracy – Better Vio, Iib, matching, and drifts
VFB CFB
DC f = 10MHz f =∞
Ø Frequency of Interest >10MHz

– CFB typically has much higher Slew Rates
• Better 3rd-Order Harmonics at higher frequency
• Higher output Voltage Swing is achievable at higher frequencies
– CFB allows higher bandwidth at higher gains
Caveat: De-compensated VFB Amps may be an alternative

High speed amps by Application
VFB CFB JFET FDA
Pulse Amplifier x x x x
Buffer x x x
Line Driver (e.g. DSL) x
Active Filter x x x
Integrator x x
ADC driver x x x
High Frequency x x
Low Frequency x x x
DC Precision x x
High Gain/Low THD x
High Gain/Low Noise x
High Gain x
Low Gain/Low THD x x
Low Gain/Low Noise x x
Low Gain x x x
TI High Speed Amplifiers
Apps Specific General Purpose

THS
THS73xx OPA
Op Amps
Video Amps VFB & CFB
Fixed Gain
Filter
Gain Rail to Rail in/out
MUX
1/3--Ch
1/3
Special Functions
FDA
Line Drivers FET
THS VCA
DSL OPA Transconductance
PLC THS6xxx VCA Multiplexer
General Purpose High speed amps
Voltage Feedback Current Feedback
u Low gain operation (G<3) u High gain and high bandwidth
u Good DC performance u Slew rates >1000V/us
u Lower noise u Low distortion @ high gains
u Dynamic range u High O/P currents
Amplifiers
JFET Input Fully Differential

u High input impedance u Differential signal – A/D drivers
u Low bias current u Common mode rejection
u Data acquisition buffering u Minimized HD2 distortion

u Ease of use & flexibility
Agenda
• TI Overview
2009 NUEDC Topic C Review
• Topic: Wideband Amplifier System
• Baseline Requirements:
- input signal: 10MHz SineWave, <=20mVrms
- Gain: 0dB - 40dB, 6dB adjustable
- Output Power: 2Vrms Max
- No obvious Distortion
• Extend Requirements:
- input signal: 10MHz SineWave, <=10mVrms
- Gain: 0dB - 60dB, Any dB adjustable
- Output Power: 10Vrms (28Vpp) Max into 50 Ohm
Blue: High Slew Rate

Red: Multi-Stage easy control Gains
Green:Ultra High Output Power!
Solution Diagram
DAC: MSP430 internal DAC12 or

TLV5636/5638:12bits Serial DAC
Amplifier Signal Chain
Input Buffer and 1st Gain Stage: Variable Gain Power Stage: +20dB fixed Gain
+20dB fixed Gain -40dB to 40dB
Adjustable Gain
Total Gain Range: 0 – 80dB

When 28Vpp Output, Accept Input Signal 2.8mVpp – 480mVpp
Amplifier Signal Chain Without Power Stage
R2 500 R4 750
R6 1k
-5 R8 1k
R1 500 -5
- R3 150 -5
-
-5
R5 100
+
+ U1 OPA656 - R7 100
+
++
P1 5k
VG1 - VF1
+5 U3 OPA843 ++
U2 OPA684
+5 ++
+5 U4 OPA684
+5
-5
+5
V1 5
V2 5
V3 1
Offset Adjust
Input Gain 6dB Gain 14dB
Input 2.8mVpp
Two OPA684 Simulate VCA810 @ +40dB Gain
10MHz SineWave
Output 2.8Vpp 10MHz SineWave
Signal Conditioning Amplifiers
General Purpose
Device Supply Bandwidth Slew Rate Input Noise Distortion Comment
THS4304 5V 3000 MHz 830 V/μs 2.4 nV/√Hz -95 dBc (10MHz) Unity Gain VFB
OPA842 10 V 400 MHz 400 V/μs 2.6 nV/√Hz -93 dBc (5MHz) Unity Gain VFB
OPA690 10 V 500 MHz 1700 V/μs 4.5 nV/√Hz -83 dBc (5MHz) Unity Gain VFB
OPA691 10 V 400 MHz 2100 V/μs 2.5 nV/√Hz -80 dBc (5MHz) CFB
THS4271 15 V 1400 MHz 1000 V/μs 3.0 nV/√Hz -92 dBc (30MHz) Unity Gain VFB
THS4031 30 V 100 MHz 100 V/μs 1.6 nV/√Hz -96 dBc (1MHz) Unity Gain VFB
Low Power
Device Supply Supply Current Bandwidth Slew Rate Input Noise Comment
OPA2889 10 V 460 µA/ch 115 MHz 250 V/μs 8.4 nV/√Hz Dual Unity Gain VFB
OPA890 10 V 1100 µA/ch 260 MHz 500 V/μs 8.0 nV/√Hz Unity Gain VFB
OPA683 10 V 940 µA/ch 200 MHz 540 V/μs 4.4 nV/√Hz CFB
OPA684 10 V 1700 µA/ch 210 MHz 820 V/μs 3.7 nV/√Hz CFB
THS4281 15 V 750 µA/ch 90 MHz 35 V/μs 12.5 nV/√Hz Unity Gain VFB, RRIO
AD603? Not so convenient…
Dynamic Range Only 42dB

At least 2 pcs of AD603!
Typical Offset:±30mV!
VCA810: easy to use and powerful
• -40 to 40dB adjustable gain range, Total Dynamic Range: 80dB
• Gain Independent 35MHz Constant Bandwidth
• Only 1 pcs VCA810 is required
• Typical Offset: ±4mV
Variable Gain Amplifiers
Variable Gain
Device Supply Bandwidth Slew Rate Input Noise Gain Range Comment
VCA810 10 V 35 MHz 350 V/μs 2.4 nV/√Hz 80 dB (±40dB) Gain law dB/V
VCA820 10 V 150 MHz 1700 V/μs 8.2 nV/√Hz >40 dB (±20dB) Gain law dB/V
VCA821 10 V 710 MHz 2500 V/μs 6 nV/√Hz >40 dB (±20dB) Gain law dB/V
VCA822 10 V 150 MHz 1700 V/μs 8.2 nV/√Hz >40 dB (±20dB) Gain law V/V
VCA824 10 V 710 MHz 2500 V/μs 6 nV/√Hz >40 dB (±20dB) Gain law V/V
THS7001 32 V 70MHz 175V/uS 1.7 nV/√Hz 42 dB ( -22dB to 20dB) with 6dB Step
Power Stage:
THS3001/THS3091/BUF634 ease your design
Output Power Requirements:

1. Amplitude: 28Vpp => Output Wideband Amplifier have VCC = 36V;
2. Current: 0.6A! A single BUF634/THS3091 can afford ±250mA;
-18V
R2 100 R1 900
U4 BUF634
+ +
R1 900 -18V
V2 18 V1 18
+18V
V2 18 V1 18
-18V
+18V
+18V - U1 THS3091
-18V
-18V
-18V +
R2 90 +
VG1 - U1 THS3091 U2 BUF634
VF1
+
+ + +18V
+ VF1
R3 50
+
R4 100 R3 900
R5 50
VG1
+
+18V
+18V
-18V -18V
THS3001HV or U3 BUF634 - U2 THS3091
THS3001/3091 + +
+
+
+18V
+18V
3 Parallel BUF634 2 Parallel THS3091
THS3001: 420MHz CFB Amplifier
Ø High Speed Imaging
• High Speed Imaging ØCommunication
• – 420 MHz Bandwidth (G = 1, -3 dB) ØHigh Quality Video
• – 6500 V/µs Slew Rate ØWireless Communications
ØBasestations
• – 40-ns Settling Time (0.1%)
• High Output Drive, IO = 100 mA
• Excellent Video Performance ØExcellent THD and low distortion
• 115 MHz Bandwidth (0.1 dB, G = 2) specification
• 0.01% Differential Gain ØExcellent Video Performance
• 0.02° Differential Phase
• Low 3-mV (max) Input Offset Voltage
• Very Low Distortion
• – THD = -96 dBc at f = 1 MHz
• – THD = -80 dBc at f = 10 MHz
• MSOP, SOIC Packages
1ku @ $3.05
EVM
EVM Available Video Distribution Amplifier Applciation

BUF634: ±250 mA High-Speed Buffer
• 2000V/µs slew rate • Useful for high frequency open-loop applications

• Pin selected BW: 30MHz to 180MHz • Adaptable for application needs
• Low quiescent current: 1.5mA (30MHz BW) • Ideal for maximum power efficiency
• Internal current limit • No external protection required
• Thermal shutdown protection • Prevents damage during abnormal conditions
1k Price:
• Valve driver $4.05
• Solenoid driver
• Op amp current booster
• Line driver
• Headphone driver
• Video driver
• Motor driver
• Test equipment
• ATE pin driver
THS3091, THS3095: Single,
Low-Distortion, Current-Feedback Amp
• Low Distortion : -67dB THD @ 10MHz, • Wide Supply Voltage Range:

Gain = +5, Vo = 2Vpp, RL = 100 ohms ±5 V to ±16 V
• High Slew Rate: 7300 V/us (G=+5, 20Vpp)
Key Differentiators
• High Bandwidth: 210MHz (-3dB, G=+2)
• High Bandwidth and Very High Slew Rate
• High Output Current: +/- 250mA • Very Good Distortion Even w/High Gains
• Only 9.5mA Quiescent Current • High Output Current Drive
• THS3095 Offers Powerdown – 500µA • Wide Power Supply Range
• Arbitrary Waveform Generators Related Products

• Test and Measurement Systems • THS3092 (Prelim) – Dual of THS3091
• Pin Driver • THS3110 – Slower but w/260mA Drive
• Video Distribution • THS3120 – Slower but w/475mA Drive
• THS3061 – Good for Low Speed Apps.
• Power FET Driver
• OPAx691 – 12V 190mA, 225MHz family
• Wired Communications Driver
• OPA2674 – 12V 500mA, 225MHz dual
Suggested Resale – 1ku Package Options Temperature Ranges Options
8 pin SOIC,
$3.59 -40 ~ 85°C
SOIC Power-PAD
Output Driver
Device Supply Bandwidth Slew Rate Input Noise Distortion Comment
THS3001HV 36 V 420 MHz 6500 V/μs 1.6 nV/√Hz -80 dBc (10MHz) CFB, ±100mA Output
THS3091 32 V 210 MHz 7300 V/μs 2 nV/√Hz -69 dBc (10MHz) CFB, ±250mA Output
OPA2674 10 V 250 MHz 2000 V/μs 2 nV/√Hz -82 dBc (5MHz) CFB, ±500mA Output
BUF634 36 V 180 MHz 2000 V/μs 4 nV/√Hz N/A Buffer, ±250mA Output
BUF602 缓冲器，10V， BW=1200MHz，SR=8000V/uS， ±80mA连续输出
OPA693 缓冲器，G=1 or 2， 10V， GBW=1400MHz， SR=2500V/uS， ±120mA连续输出
OPA692 缓冲器， G=1 or 2，10V， GBW=280MHz， SR=2000V/uS， ±190mA连续输出
TI High Speed Amplifier Summary
• High Speed Amplifiers (OPA69x, OPA8xx, THS3xxx, THS4xxx):
- Precision Amplifiers are surely Voltage Feedback
- HS Amplifiers can be Voltage Feedback or Current Feedback
- HS Amplifiers most are Bipolar input stage
- CMOS ones are slower, can be used in low power and R-R under
1.8-5.5v single supply
- FET/CMOS input ones are used in high speed transimpedance
applications which require a high input impedance Amp
高速运算放大器：
• OPAy8xx: 电压反馈（含去补偿）, GBW up to 4G, SR up to 500V/uS, <=12V
• OPAy6xx: 高压摆率，电流反馈, 少量电压反馈, ；<=12V, SR up to 4KV/uS, BW up to 1.5G
• THS4xxx: 电压反馈，<=36V, SR up to 1KV/uS, GBW up to 1G
其中：THS45xx: 电压反馈, 全差分, <=5V, SR up to 6KV/uS, GBW up to 3G
• THS3xxx: 电流反馈, <=36V, SR up to 6KV/uS, BW up to 1.8G，大输出电流
• THS73xx: 带滤波器的视频运放, <=5.5V, 三通道, SR up to 1300V/uS, BW up to 500MHz
Good PCB layout:
Minimize your Input (-) & Output Stray C
Input (-) Capacitance
VOUT  R F 
= 1 + (1 + 2π CSTRAY R G )
VIN  R G 
RF + RG
f ZERO =
2π CSTRAY R F R G
Inverting Node
Ø Inverting node (-) of an op amp is sensitive to stray capacitance (CSTRAY)
ØRF,RG and CSTRAY create a zero to in the feedback which can lead to instability
Ø As Little as 1pF of CSTRAY can cause stability problems
ØNode includes the entire trace up to the placement of RF, RG, and any other component
on the inverting node
(-) Input Capacitance is Bad
Bode Plot
Stability is determined by rate of
closure between open loop gain and
Open Loop Gain feedback factor
in dB
a Aol -20dB/dec
Acl = vo / vi = =
1 + a β 1 + Aol β
Inverse of
Feedback Factor Rate of closure = 40dB/dec = Not Stable
with capacitance on
inverting input
Rate of closure = 20dB/dec = Stable
Inverse of
Ideal Resistive Frequency in Hz 1
Feedback Factor f ZERO ≈
2π CSTRAY R O
Minimizing Stray C at (-) Input
Solutions:
1. Eliminate Ground Planes and Power Planes under and near the inverting input (-)
2. Shorten trace by moving components closer to the inverting input (-)
3. Reduce RF and RG values
4. Increase Gain of System
5. Use Inverting Configuration Place Compensation Capacitor Across RF
RG
C COMP = C STRAY
RF
Inverting Mode Compensation

Output Capacitance
1
f ZERO ≈
2π CSTRAY R O
Assuming:
RO << RF, RLOAD
VOUT  R F  RO RO 
= 1 + 1 + + + 2π CSTRAY R O 
VIN  R G  R F + R G R LOAD 
Ø Op amps are sensitive to capacitance on output (CSTRAY)
Ø Real op amps have output Impedance (RO)
Ø RO and CSTRAY create a zero to in the feedback which can lead to
instability
Output Capacitance is Bad
Bode Plot
Stability is determined by rate of
closure between open loop gain
Open Loop Gain and feedback factor
In dB
a Aol
Acl = vo / vi = = -20dB/dec
1 + a β 1 + Aol β
Inverse of
Feedback Factor with Rate of closure = 40dB/dec = Not Stable
output capacitance
Rate of closure = 20dB/dec = Stable

Inverse of
Ideal Resistive Frequency in Hz
Feedback Factor f ZERO ≈
1
2π CSTRAY R O
Minimizing Effects of C at Output
Solutions:
1. Eliminate Ground Planes and Power Planes under output node
2. Use series output resistor
3. Shorten traces by moving components closer to output pin – especially
Series Matching R
4. Increase Noise Gain of System (i.e. decrease feedback factor)
5. Use Feedback Compensation
Do not use for CFB

RG RF RG RF RG RF
CC
RN
- RO RSERIES - RO - RO RI
V CN V V
+ + +
CSTRAY RLOAD CSTRAY RLOAD CSTRAY RLOAD
VIN RTERM VIN RTERM VIN RTERM
Adding Series R for Isolation Increasing Noise Gain Only Feedback Compensation
Example of High Speed Layout
1. TOP LAYER Attributes
2. Signal In/Out traces are microstrip line with
Z0 = 50Ω.
3. Terminating Resistors next to Amplifier.
4. Output Series Resistor next to Amp.
5. 100pF (NPO HF) Bypass Caps next to Amp.
6. Larger Bypass Caps Farther Away with
Ferrite Chips for HF isolation of currents.
7. MULTIPLE Vias Everywhere to Allows for
Reduced Current Flow Area
8. Short, Fat Traces to reduce inductance
9. Large Solid Ground Plane – No Spokes
10. Side Mount SMA connectors for Smooth
Signal Flow
11. Rounded Signal Traces, no 90° bends
Layer 2: Signal GND Plane Layer 3: Power Plane

GND Plane Next To Signal Plane for Notice Cut-Out in Sensitive areas near
Continuity in Return Current Amplifier on ALL planes.
Bottom Layer – GND Plane
1. Solid GND plane to minimize
inductance.
2. Layer-2 GND plane and
Bottom Layer form excellent
bypass capacitor with Power
Plane.
3. All Signals are on Top Layer
to minimize the need for
signals to flow through vias.
4. Again, Multiple Vias
Everywhere
5. Cut-Out around Amplifier to
reduce Stray Capacitance –
except when turned into
Microstrip Line
Example: VCA810 EVM (DEM-VCA-SO-1A)
For VCA82x, pls refer to DEM-VCA-SO-1B

Example: General High Speed OPA EVM
(DEM-OPA-SO-1A)
Example: Non-Inverting High Speed OPA
EVM (DEM-OPA-SO-1B)
High Speed ADC
ADC Architectures
• ADCs
– Delta Sigma: DC or Audio Apps
– SAR: DC and KHz Signal Apps
– Pipeline: Wideband Apps, like CI and Video
– Flash: Ultra-High Speed, like Oscilloscope
32
24 ~ MSP430
DS
20
Delta Sigma
MSP430
16 DS
C2000
12
SAR MSP430
SAR
SAR
Pipeline
Stellaris
SAR
8
10 100 1K 10K 100K 1M 10M 100M 1G
Texas Instruments
Conversion Rate (SPS)
Did you know…?
TI released the highest speed 14-bit ADC…three times!
ADS5500 ADS5546 ADS5474

2004 2005 2007
14-bit, 14-bit, 14-bit,
125MSPS 190MSPS 400MSPS
Did you know…?
TI released the highest speed 12-bit ADC…three times!
ADS5463 ADS5400 ADC12D1800

2006 2009 2010
12-bit, 12-bit, 12-bit,
High Speed Pipeline ADC Portfolio
Lowest Power Low Power Highest Speed and

Highest Density High Performance Performance
10 – 12 bit 11 - 16bit 12 - 16 bit
ADS52xx ADS4xxx ADS54xx

ADS6xxx
ADS55xx
Highest performance
Lowest Power ADCs High IF Highest SNR, SFDR
High channel density High SNR Highest speed
Small package Low power Highest IF performance
Serial LVDS I/F High density High input impedance
Input buffer
Communications
Medical Imaging Imaging Communications
CCD Imaging Portable Test Test and Measurement
Communications Defense Defense
40 to 70 MSPS 65 to 250 MSPS up to 1000 MSPS

Pipeline ADC – Example ADS5424
• Notice that there are 3 sub-ADCs
– Sub-ADC1 = 5 bits
– = 16 bits for a 14-bit ADC ?
• ADS5424 is an 80MSPS 14 bit ADC
– The extra bits are used for internal error correction, only 14 bits
come out
– The Clock Latency is 3 cycles – it takes three periods of the clock for
the converted signal to come out in digital format
Pipeline A/D Converter
Timing and Data Latency
Sample Points
S4 S5
S8
S1 S9
Analog Input
S2 S6
S3
S7
Track
Clock
Hold Data Latency, 6.5 clock cycles
Track
Internal
S/H
Hold n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Output Data n-7 n-6 n-5 n-4 n-3 n-2 n-1 n

ADC clock considerations
• Symptoms of clock issues
• System jitter spec
• Internal ADC jitter spec
• External Components jitter spec

Jitter affect the ADC
IF ADC Most Care about: Jitter in Time Domain
System Jitter:
Clk Jitter + ADC inherent Jitter
ADC Internal Jitter = 150fs
System Jitter: Maximum ADC SNR
[
SNR[ dBc ] = S / N = −20 log10 2 ⋅ π ⋅ Fin ⋅ Jitter TOTAL ]
110.00
100.00
90.00 TOTAL System Jitter

SNR [dBc]
80.00
0.1ps
70.00
0.2ps
60.00 0.4ps
0.8ps
50.00 1.6ps
3.2ps
40.00
1.00E+07 1.00E+08 1.00E+09
Fin [Hz]
Calculation for Clock Jitter Requirement
• Solve for the RMS jitter required of the system in
order to get at least 70dB SNR at 100MHz Fin
[
SNR [ dBc ] = − 20 log 10 2 ⋅ π ⋅ Fin ⋅ Jitter TOTAL ]
Jitter TOTAL = (10 ^ ( − SNR [ dBc ] / 20 )) / 2 ⋅ π ⋅ Fin
503 fs = (10 ^ ( − 70 / 20 )) / 2 ⋅ π ⋅ 100 e 6
• …now solve for required Clock Jitter with 105fs of internal
ADC aperture jitter
(Jittertotal)2 = (jitterADC)2 + (jitterCLOCK)2 (now rearrange)
jitterCLOCK = [(jitterTOTAL)^2 − (jitterADC)^2 ]^0.5

jitterCLOCK = [ (503e-15)^2 – (105e-15)^2 ] ^ 0.5 = 492fs
Jitter Calculator for High Speed ADCs
yellow is a user input
Calculate Jitter-limited SNR
Input Frequency 170.00 MHz desired input frequency to ADC analog inputs
Aperture Jitter 120.00 fs rms aperture jitter comes from ADC datasheet
Ext Clock Jitter 100.00 fs rms rms jitter of clock source at ADC clock inputs
Total Jitter 156.20 fs rms rms jitter of clock and ADC jitter combined
SNR 75.55 dBc Signal-to-Noise Ratio of ADC
Calculate Required Clock Jitter to achieve desired SNR

Input Frequency 160.00 MHz desired input frequency to ADC analog inputs
Aperture Jitter 150.00 fs rms aperture jitter comes from ADC datasheet
Ext Clock Jitter 218.07 fs rms rms jitter of clock source at ADC clock inputs
Total Jitter 264.68 fs rms rms jitter of clock and ADC jitter combined
SNR 71.50 dBc Signal-to-Noise Ratio of ADC
These analyses assume large clock amplitudes such that the slope-dependency jitter is minimal.
The user should note that at high clock rates and/or low clock amplitudes, the slope of the clock source
could affect SNR by a small margin.
• Calculator located in all high speed ADC product folders

TI Clock Chain
Oscillator Clock Buffers External VCO On-Chip VCO

IC Clock Clock
Generators Generators
Oscillator Package
PLL Fan-out PLL

PLL +
+ Buffer VCXO
VCO VCO
<300MHz CMOS: Without PLL Jitter Cleaner RF Signal :

CDCE706/949 CDCLVP110 CDCE72010 TRF3761
Up to 1.175GHz: CDCL1810 CDCM7005 Clk Signal:
CDCE421 With PLL CDCL6010
CDC5801A CDCE62005
PLL in a Glance
晶振 ÷ R分频器鉴相器 LPF VCO
SPI控制数据
数据寄存器 ÷N分频器
Reference clock: Reference clock:
Non-PLL
Non- PLL
FanOut FanOut Clock
PLL
Feed-
back
Reference clock:
Reference clock: Output 1:
Output 1: Disadvantages:
• Non-PLL Buffer adds a
Output 2:
Output 2: Output 3:
Output 3: Propagation Delay time
• Process and Part to Part Output 4:
Output 4: Output 5:
Skew might be an issue
PLL as Jitter Cleaner: CDCM7005
Jitter Cleaner: Any PLL-based clock that cleans the noises from the reference
clock and provides a clean and synchronized signal for the receivers using an
external VCO (VCXO) or internal VCO.
Ideal Input clock:

Real Input clock with Jitter:
LPF
PLL+
CDC
Jitter Cleaning
Clk Distribution
V304 VCXO
using a VCXO
Ideal Input clock:
Clean Clock:
CDCM7005 Application Circuit
CDCE62005
3:5 Frequency Synthesizer/Jitter Cleaner
• Input frequencies from 80kHz to 500MHz • Fully Integrated twin VCOs support wide output frequency
• Crystal Inputs from 2MHz to 42MHz range
• Output frequencies from 4.25MHz to 1.175GHz • Wide input/output frequency range supports high and low
• Output up to 5 LVPECL/5 LVDS/10 LVCMOS end of frequency standards
• Individual phase adjust • Selectable input/output standards reduces translation
logic
• Optional high swing LVPECL mode • Integrated/external loop filter provides flexibility
• Wide-range integer divide selectable by output • EEPROM saves default start-up settings
• Low output skew (~ 20ps, typ) • SPI interface provides in-system programming
• Integrated/External PLL Loop Filter • QFN-48 package, Tem -40 to 85 C
• Low jitter (< 1ps RMS, 10k-20MHz), ~ 25ps, pk-pk
• On-chip EEPROM
Loop
Filter
LVPECL/LVCMOS/LVDS
LVDS/LVPECL/LVCMOS
Wide Range Integer

• Wireless BTS
5 Individual Divider
Input PFD
(Pico cell, WiMax, Macro Base band)
Phase Adjust
Divider Charge Pump VCO1
Prescaler
• Data Communications
• Medical VCO2
Crystal/LVCMOS
• Test Equipment Sampling
• Jitter Cleaners Now SPI Feedback
EEPROM Divider
3.3V
Sep/08 In Production
CDCE421
Tiny Flexible Frequency Synthesizer for Data Com
• Output Frequency from 10.9MHz up to 1175MHz • Customers can qualify one device for multiple
• Accepts 27.35MHz to 38.33MHz input crystal and LVCMOS frequencies
input • Low frequency input lowers system cost
• Integrated loop filter • Provides very small foot print
• Low jitter design (< 1ps RMS) 10K – 20MHz, • Ideal for Data Communications (Ethernet, Fiber
< 40ps, pk-pk period jitter Channel, S ATA, PCI Express)
• LVDS or LVPECL selectable output • Industrial Temperature range -40 to 85 C
• ~2x~2mm die size, 4x4mm QFN Package
• On-chip EEPROM
• Power ~ 300mW for LVPECL
Output Enable/Programmable Interface
PFD / Charge Pump

Crystal
Loop
Oscillator
LVPECL or LVDS
Filter
Output Divider
• XO for Data Communications Input
Prescalar
• 5x7 Oscillators (XO) from 10MHz -> ~1.2GHz (LVPECL
or LVDS)
• Mass market XO applications Feedback VCO 1
Divider
VCO 2
1Ku / $7.00
CDCE421EVM
High Speed DAC
DAC Technologies
20
DS
16
R-2R
String Current
12 Steering
~
~
8
10000 10 8 6 4 2 0.1 0.01
Settling Time- µs
Did you know…?
TI released the smallest TX DACs… three times!
DAC5682Z DAC3283 DAC3484

2008 2009 2011
Dual 16-bit, Dual 16-bit, Quad 16-bit,
9x9mm QFN 7x7mm QFN 9x9mm QFN
High Speed D/A converter portfolio
8 – 14-bit 14 – 16-bit 14 – 16-bit
Straight DACs Wideband DACs Full-Featured DACs
DAC900 DAC5681 DAC568xZ

DAC5675A DAC32xx
Input data = DAC sample rate
Highest / widest bandwidth DAC5688
Input data = DAC sample rate High IF
Low power DAC On chip data interpolation
LVDS I/O
High bandwidth Low data rate @ high Fs
CMOS parallel I/F Internal digital mixing
Quadrature Modulation Correction
• Communications
• Communications • T&M • Communications
• AWG • Defense and Aerospace • T&M
• T&M • Defense and Aerospace
30 – 275 MSPS 400 - 1000 MSPS 500 – 1000 MSPS

CMOS LVDS CMOS LVDS
Single Dual Single Single Dual

DAC900/2/4, DAC2900/2/4
Single/Dual 10/12/14-bit, 125 MSPS DACs
Features
Single Supply: 3.3V or 5V
3.3V or 5V CMOS Data Input
Offset Matching: 0.02% min
Low Power: 350 mW @ 61.44 MSPS
Pin Compatible Family
Performance (14-bit version)

SFDR: 78dB at 10 MHz
WCDMA TM1 ACPR:
69 dBc @ Baseband
68 dBd @ 30.72 MHz IF
DAC5652/62/72
Dual 10/12/14-bit, 275 MSPS DACs
Features
Single Supply: +3.3V
3.3 Input
Interleave input mode
Offset Matching: 0.02% min
Low Power: 350 mW @ 275 MSPS
Pin Compatible Family
Performance (14-bit version)

SFDR: 74dB at 20MHz, 275Msps
WCDMA TM1 ACPR:
78 dBc @ Baseband
73 dBc @ 30.72MHz IF
TI High Speed Data Converters Naming Rules
Delta-Sigma:
• ADS16xx: 16bit, Delta-Sigma, up to 10MSPS
流水线型高速ADC:
• ADS55xx/6xxx: 11-16bit, up to 250MSPS, 低功耗，高性能，含串行LVDS输出
• ADS54xx: 11-16bit, up to 500MSPS, 最高性能
• ADS51xx/52xx: 10-12 bit, up to 70MSPS, up to 8 通道同时采样, 并行输出，
适合医疗等多通道信号采集设备
• ADS8xx: 8-12bit, up to 80MSPS, 低端流水线型ADC，适合本科学生使用
Current Steering DACs:

• DACy90x: 8 – 14bits, up to 200MSPS, 单/双通道
• DAC56x2: 10 – 14 bits, up to 275MSPS, 双通道
• DAC568x: 16 bits, up to 1GSPS, 单/双通道，不带/带插值滤波功能
Agenda
• TI Overview
TI Power Overview
TI Analog Overview: Power
240VAC 48/24V Hot

AC/DC 48/24V to 5V 5V to -5V -5V
Swap
5V to 3.3V 3.3V
AC/DC或一次电源：背板电源：
交流电到直流电源总线电源总线到板卡级电源转换，主
5V to 2.5V 2.5V
的转换，主要使用UCC 要使用UCC系列的芯片，小功率
系列芯片。或不需要隔离时可考虑使用
1.XV 1.XV
主要组成部分(TI)： TPS40K和TPS54K。
PFC 主要组成部分（TI）：负载端（POL）电源：
Power PWM Controller Hot Swap(热拔插) 主要使用TPS系列的芯片。
MOSFET Driver PWM Controller 主要组成部分（TI）：
MOSFET Driver 电感型DC/DC开关稳压器
DC/DC Converter and Controller MOSFET Driver and MOSFET

电容式DC/DC开关稳压器
MOSFET
线性稳压器
TI Power Reference Design Search Tool
§ Easy to use search tool
§ Search by input / output criteria, application, topology
§ Can export list to excel spreadsheet
§ Provides link to the reference design folder for detailed information
§ Popular designs available at www.ti.com/powerlab
www.ti.com/powerlab
期待与您合作！
黄争
frank-huang@ti.com
ti_cup@126.com
13764149990
POL Power Types
• Linear Regulator: TPS7xxx

• Switch Mode Regulator
- Inductive
- Inductor less: Charge Pump
• What is Best
Linear regulator
A linear regulator will operate with an input/output difference < 2V
In an LDO VDO is typically <0.5V in today’s LDOs
Pass Transistor
Regulated
Input
Output
Voltage
VREF Error
REF Amp Sampling
Element
Feedback
Voltage
– Current flow through the device is continuous
– Output voltage is controlled by varying the impedance of the pass transistor
– Input voltage must be greater than the output voltage
– If the input voltage gets too low, the output drops out of regulation
– Pass element can be implemented with a Bi-Polar Transistor or a MOSFET
– Today’s new LDOs ues MOSFET pass element due to its low RDSON
How Linear Regulator Works
• VOUT provides feedback that is
compared to internal Voltage
Reference
• Error amp senses VOUT change and

controls Pass Element to maintain
constant VOUT
• Power not delivered to the load is

dissipated in the pass element which
generates heat and reduces efficiency
• Pass element can be implemented

with a Bi-Polar Transistor or a
MOSFET
• Today's new LDOs use MOSFET pass

element
• Due to the low RDSON of today

MOSFETS we can achieve very low
drop out voltages
A Linear Regulator Application Circuit
Data Sheets – Things to look out for
• VOUT Accuracy
– Verify how VOUT accuracy is specified
– TI specifies VOUT over full operating temp range.
• VIN
– Low VIN to VOUT ratio relates to decrease in performance .
• Performance at low VIN usually not listed in data sheets.
• VDO (Drop Out Voltage)
– Verify the IOUT used to specify VDO
• Thermals
– Verify the package can handle the power dissipation required @ the expected
ambient temp. (Refer to previous slide)
• IQ (Quiescent Current)
– IQ critical at very low IOUT
– If IOUT 100mA low IQ is pretty much not a factor
– Also listed as Ground Current
• PSRR
– Degrades as VIN to VOUT. ratio decreases
• Noise Density
– Noise Density is a multiple of VOUT
Linear Regulator parameters: VDO
• Input Voltage
The minimum Vin must be larger than Vout + VDO, independent from the minimum
value given in the selection table.
• Efficiency
By neglecting the quiescent current (Iq) of the LDO, efficiency can be calculated as
Vout/Vin.
• Power Dissipation
PD = (Vin – Vout) x Iout; PD is limited by package. Compare with step down buck DC-
DC, for higher power dissipation or requirements for higher efficiency, recommend
buck.
Pwaste =(VIN-VOUT) IOUT

=VDOIOUT
Pass Element: Bipolar & FET
Bipolar Transistor Conventional Linear Regulators
VDO=2VBE+VCE
Bipolar Transistor Low Drop Out (LDO) Regulators
VDO=VCE
Bipolar Transistor Quasi LDO Regulators
VDO=VBE+VCE
Bipolar Transistor Linear Regulator Summary:

FET Linear Regulators
Min (VIN - VO) ≈ RON IL
VIN VOUT
REF
GAIN
BENEFITS
• Min (VIN - VOUT) reduces to zero as IL reduces to zero
• Very low quiescent current, regardless of load current
LIMITATIONS
• Limited input voltage (today)
• Slow dynamic response
P-Channel Pass Element
• Easier to Drive
– Requires VG < VIN to turn MOSFET on
• High Output Impedance

– Requires High ESR Cap
• Regulation
– Change in VOUT does not effect VGS
ID Drain Current (A)
– Requires response from Error Amp
• PSRR Performance
– VGS affected by VIN
– VGS and VDS affected by variations on VIN
which degrades PSRR
N-Channel Pass Element
• Difficult to drive
– Requires VG > VIN to turn MOSFET on
• Low Output Impedance

– Stable with low ESR Cap
• Source Follower Output Topology

Typical N-Channel ID vs VDS Plot
2.5 – Stable power buffer circuit
ID Drain Current (A)
2.0 VGS = 3.2V

• Self Regulating
1.5 – Change in VOUT affects VGS
VGS = 3.0V – Responds to VOUT Transient’s without Error
1.0 Amp Response
VGS = 2.8V
0.5
• Better PSRR Performance
VGS = 2.6V
VGS = 2.4V
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 – VGS not affected by VIN
VDS Drain to Source Voltage (V) – PSRR dependent on VGS and VDS
– VDS alone affects PSRR performance
Adding Values in LDO
TI’s Competitive Advantage
• VBIAS to improve efficiency at heavy load
– LDO efficiency > 80%
• Soft Start
– Ability to slowly ramp up the output voltage on startup.
• Dynamic Voltage Scaling (DVS)
– Dynamically adjust the Level of VOUT.
• Factory EEPROM Programmable VOUT
– Flexibility to quickly created new fixed VOUT versions
• IQ Current
– Supply current drawn by LDO - Lowest in the Industry
• Power Supply Rejection Ratio (PSRR)
– Ability of the LDO to filter out switching noise.
Achieving Ultra Low VDO: VBIAS
• High Efficiency
– Low VOUT applications
• High PSRR performance
– PSRR performance not
dependant on VIN to VOUT ratio
• N-Channel Pass Element
– Stable with Any/No Capacitor
• Require: VBIAS > VOUT by 1.4V
– Draws ~ 4mA
– Minimal Load on Power Rail
– VBIAS can be > 3.3V for VOUT <
1.8V
• Fast Transient Response
– Strong/Stable Gate Drive
– VOUT variation changes VGS
– Topology designed to self
regulate VOUT with out Error
Amp response
VBIAS – Increasing LDO Efficiency
Example with VBIAS = VIN
VIN – 3.3V
VOUT – 1.2V
VBIAS – 3.3V
Eff = POUT/ PIN ~ VOUT/ VIN
Eff = 1.2/3.3 x 100 = 36%

Example with VBIAS > VIN
VIN – 1.5V
VOUT – 1.2V
VBIAS > 3V
Eff = POUT/ PIN ~ VOUT/ VIN
Eff = 1.2/1.5 x 100 = 80%

TPS742 Application
1.4V for 6416/DM642

1.2V for C55x/
Cyclone/Spartan
TPS742
• VOUT Accuracy
• VIN
• Thermals
• PSRR
• Noise Density
Dissipation Rating is Important
If: Vin=5V, Vo=3.3V, Iomax=400mA,
Then: TPS7333: Available in 2.5V, 3V, 3,3V, 4,85V and 5V output voltage.
Output current range from 0mA to 500mA
Dissipation Rating Table –Free air temperature
Pd=(Vin-Vo) * Imax = 680mW
So: If Ta is less than 70’C, TPS7333P is a good choice.

If Ta is less than 25’C, TPS7333D is a good choice.
• VOUT Accuracy
• VIN
• Thermals
• PSRR
• Noise Density
• VBIAS
• Dynamic Voltage Scaling (DVS) Especially useful
when driving
– Dynamically adjust the Level of VOUT. Ultra Low Power
• IQ Current Processors: like
MSP430
• Soft Start
System Frequency
Minimum Operating Voltage MSP430F21X1
Supply Voltage
MSP430 IAM Current (F Version)
• Across VCC and Frequency
– Current consumption of Active Mode vs. System Frequency (F-Version)
– IAM = (IAM)[1MHz] x f(System)[MHz]
MSP430 “F Version” Active Mode Current (IAM)
9
VCC vs. Operating Frequency
8 VCC - 3.6V
7 VCC - 3.3V
IAM 6 VCC - 2.7V
(mA) 5
VCC - 2.2V
4
VCC - 1.8V
3
2
1
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Operating Frequency (MHz)
Dynamic Voltage Scaling (DVS)
Discrete DVS implementation Benefits of DVS
• Dynamically switch VOUT between
2 preset levels
• Lower VCC results in lower IQ thus
prolonging battery life
• Integrated DVS eliminates power
lost in the discrete components
DVS implementation with TPS780xx

TPS780 DVS Feature lowers Average IQ Current Drawn
by MSP430
3.0V
VIN VOUT VCC
1uF 1uF
LDO MSP430
I/O
GND VSS
VCC 3.0V
Active
Mode
` 1.6uA IQ -- LPM3/
sleep mode
• With VCC @ 3V during Sleep Mode MSP430 • With VCC @ 2.2V during Sleep Mode MSP430
IQ = 1.6µA IQ = 700nA
• Without DVS VCC remains constant • With DVS you can Dynamically lower VCC
• Ability to lower VCC results in lower • Lower VCC – Lower processor clock – Lower IQ
processor clock speed • Lower IQ improves Battery Life
• Lower the clock speed the lower the IQ so
less power is consumed
Battery Life Comparison for MSP430F2619
TPS780 Battery 1uA LDO 20uA LDO

(Days) (Days) (Days) (Days)
Efficiency with VBAT=3.0 VCC=2.2V 73% 100% 73% 73%
LDO Quiescence Current (IQ) 0.5uA 0 1uA 20uA
MSP430 Active current 2.19mA 3.09mA 2.19mA 2.19mA
MSP430 Low Power current 0.5uA 0.6uA 0.5uA 0.5uA
Active Mode 1 sec/hour 5742 6286 4373 434
Active Mode 1000 sec/hour 15.4 10.7 15.4 14.9
Active Mode all the time 4.2 3.0 4.2 4.2
Note: Never ruin your low power design with wrong LDO!
e.g. The popular TLV1117 has a quiescent current of 5mA!
DVS LDOs
Device VIN IOUT VOUT IQ VDO Package
(V) (mA) (V) (uA) (mV)
TPS780330220 2.2 - 5.5 150 3.3 / 2.2 0.5 130 TSOT-23/SON 6
TPS780230300 2.2 - 5.5 150 2.3 / 3.0 0.5 130 SON 6
TPS780300250 2.2 - 5.5 150 3.0 / 2.5 0.5 130 SON 6
TPS780270200 2.2 - 5.5 150 2.7 / 2.0 0.5 130 TSOT-23
TPS78001 2.2 - 5.5 150 1.22 - 5.25V 1.7 130 TSOT-23/SON 6
TPS781330220 2.2 - 5.5 150 3.3 / 2.2 1 130 TSOT-23/SON 6
TPS78101 2.2 - 5.5 150 1.22 - 5.25V 2.7 130 TSOT-23/SON 6
TPS728185315 2.7 - 6.5 200 1.85 / 3.15 45 230 SON 6/WCSP
Low IQ LDOs
Device VIN IOUT VOUT IQ VDO Package
(V) (mA) (V) (uA) (mV)
TPS714 2.5 – 10 80 1.2 – 9.0 3.2 670 SC-70/SON 6
TPS782 2.2 - 5.5 150 1.5 – 4.2 1 130 TSOT-23/SON 6
TPS780 2.2 - 5.5 150 1.22 – 5.25 0.5 130 TSOT-23/SON 6
TPS781 2.2 - 5.5 150 1.22 – 5.25 1 130 TSOT-23/SON 6
TPS715 2.5 - 24 50 1.2 - 15 3.2 415 SC-70
TPS715A 2.5 - 24 80 1.2 - 15 3.2 670 SON 6/SON 8
TPS797 1.8 - 5.5 50 1.8, 3.0 & 3.3 1.2 110 SC-70
• VBIAS
• Soft Start
• IQ Current
What is Soft Start?
TPS742/401 Start-Up Response
• Reduces In-rush
currents during start-up
• Limits supply rail

voltage sag at start-up
Soft Start
Discrete Soft Start Circuit Required before introduction of TPS74X LDOs
EN EN
VOUT
VOUT
VIN COUT1
VIN
NR/FB COUT2
GND
CIN
CNR
Integrated Soft Start Circuit Using TPS74x Family of LDOs

1.5V
VIN Power
Good
CIN TPS74701
VBIAS
1.2V @500mA
VOUT
3.3V
Enbable
COUT
CBIAS
Soft Feed
Start GND Back
CSS
VBIAS & Soft-Start LDOs
VIN Max IOUT VOUT VBIAS VDO IQ
Device (uA)
(V) (A) (V) (V) (mV)
TPS720 1.1 - 4.5 0.35 0.9 – 3.6 2.5 – 5.5 110 32
TPS747 0.8 - 5.5 0.50 0.8 – 3.6 2.7 – 5.5 50 N/A
TPS742 0.8 - 5.5 1.5 0.8 – 3.6 2.7 – 5.5 55 N/A
TPS743 0.8 - 5.5 1.5 0.8 – 3.6 2.7 – 5.5 55 N/A
TPS748 0.8 - 5.5 1.5 0.8 – 3.6 2.7 – 5.5 60 N/A
TPS744 0.8 - 5.5 3 0.8 – 3.6 2.7 – 5.5 115 N/A
TPS749 0.8 - 5.5 3 0.8 – 3.6 2.7 – 5.5 120 N/A
• VOUT Accuracy
• VIN
• Thermals
• PSRR
• Noise Density
• VBIAS
• Soft Start
• IQ Current
Power Supply Ripple Rejection Ratio (PSRR)
• Measurement of power supply’s ability to reject/filter noise on the input bus

• Critical in many Audio and RF applications.
• Historically LDOs have poor high frequency PSRR performance
• Today TI has LDOs with PSRR > 40dB @ 5MHz
TPS717 Typical LDO PSRR Graph Comps Low Noise LDO

~20dB PSRR @
1MHz
>40dB PSRR @
1MHz
PSRR Comparison
Input Spectrum Competition o/p Spectrum
1000.00 100.00
100.00
10.00
10.00
uV / sqrt(Hz)
uV / sqrt(Hz)
1.00
1.00
0.10
0.10
0.01 0.01
0.00
0.00
10 100 1K 10K 100K 1M 10M
10 100 1K 10K 100K 1M 10M
Freq (Hz) Freq (Hz)
TPS717 o/p Spectrum
•
100.00
Switching frequency spike (~1MHz)
10.00
– Not attenuated by competitions LDO
uV / sqrt(Hz)
1.00
– Attenuated by TPS717
– May show up at output of RF VCO which 0.10
after mixing will affect the PA

performance 0.01
– May fold back into audio band and

0.00
create noise in audio application 10 100 1K 10K 100K 1M 10M
Freq (Hz)
BACK
LDO used as Output Filter
Analog
12V in Digital 5V 3.3V/1.8V
• LC filter as an output filter • LDO as an output filter

– Inductor and Capacitor cost – No calculations need for second
increase with output current filter
– Second LC filter can adversely – Very little impact on transient
affect the transient response response
– Can affect loop stability – Does not affect loop stability
– LC Filter can be costly for – Much wider filtering capability
Higher IOUT with TI’s wide PSRR LDOs
High-Performance
Noise Sensitive Applications
-18V Switcher
@300kHz
+18V Switcher
@ 300kHz
-12V LDO
+12V LDO
BACK
PSRR vs. Noise Density
TPS717
PSRR
• The ratio of VOUT/ VIN Noise
• Measure of how well a LDO rejects VIN
ripple/noise at various frequencies
– Expressed in dB
Noise Density TPS717
• Mainly generated by the Internal VREF

• Noise Density is expressed 2 ways
– Spectral Noise Density (μV/√Hz)
• Plot of Noise Density vs. Frequency.
– Spectral Noise Density RMS (μVrms).
• Integrated over a finite frequency range
example - 30uVrms typ (100 to 100kHz)
Noise Density
• Sources of Noise Density
– Noise generated by the LDOs Internal Band Gap Reference
– Noise injected into the Feed Back pin of Adjustable Versions
• Noise Density is a Factor of VOUT
– The larger VOUT the Higher the value of Noise Density
+
+
-
-
Low Noise LDOs
IOUT IQ VDO VIN VOUT Output
Device (mA) (uA) (mV) (V) (V) Noise PSRR @
(uVRMS) 1kHz (dB)
TPS717 150 40 170 2.5 - 6.5 0.9 – 6.2 30 70
TPS799 200 40 100 2.7 – 6.5 1.2 – 6.0 29.5 65
TPS734 250 44 125 2.7 - 6.5 1.0 - 6 28 60
TPS735 500 46 250 2.7 - 6.5 1.0 - 6 28 60
TPS731 150 400 30 1.7 - 5.5 1.2 - 5 30 55
TPS732 250 400 40 1.7 - 5.5 1.2 - 5 30 55
TPS736 400 400 40 1.7 - 5.5 1.2 - 5 30 55
TPS7A45 1500 1000 300 2.1 - 20 1.21 - 20 35 68
TL1963 1500 1000 340 2.1 – 20 1.21 – 20 40 68
TPS795 500 260 110 2.7 – 5.5 1.2 – 5.0 33 60
TPS796 1000 260 250 2.7 – 5.5 1.2 – 5.0 40 60
TPS786 1500 260 390 2.7 – 5.5 1.2 – 5.0 40 60
Summary: Adding Values in LDO
• For High Output Current: >3A, up to 7.5A
e.g. TPS744xx, TPS759xx, TPS756xx
• For Ultra Low Noise Output: High PSRR
e.g. TPS79xxx, TPS786xx, TPS717xx
• For Ultra Low Dropout Voltage: low as 30mV
e.g. TPS770xx, TPS73xxx, TPS742xx
• “Cap Free” Technology: reduce cost, easy to use
e.g. TPS73xxx, TPS742xx
• Powering MSP430: Low Iq, Dynamic Voltage Scaling
e.g. TPS797xx, TPS770xx, TPS780xx
• For Low Power Processors: Dual Output, POR, Supervisor
e.g. TPS703xx, TPS767D3xx
Cap Free technology
• Why Tantalum Capacitor is best after a traditional LDO?
Cap Free Technology
• Why Tantalum Capacitor is best after a traditional LDO?
10uF, 1Ω ESR makes the

Zero at 16kHz
TPS703xx Driving TI C5000/2000 DSP
VCORE 1.8V Up to 2A, VIO 3.3V Up to 1A, with POR and Power on Sequencing
Computing/Industrial LDOs
Click to see one
3A TPS744/749 – VIN 0.8V to 5.5V IOUT 3.0A
page overview
LP38500/1/2/3 – VIN 2.7V to 5.5V IOUT 1.5/3.0A
TPS7A45 – VIN 2.1V to 20V IOUT 1.5A
TPS740 – VIN 1.2V to 5.5V IOUT 1.5A
TPS7A71/2/3 – VIN 1.5V to 6.5V IOUT 1.0/2.0/3.0A
TPS7A33 – VIN -3.0V to -36V IOUT -1.0A VBIAS
TPS7A48 – VIN 3.0V to 36V IOUT 1.0A

High PSRR
TLV1117LV – VIN 2.0V to 5.5V IOUT 1.0A
High VIN
TPS7A80 – VIN 2.2V to 6.5V IOUT 1.0A
Dual
LP3878 – VIN 2.5V to 16V IOUT 800mA
TPS747/48– VIN 0.8V to 5.5V IOUT 0.5/1.5A No - CAP

IOUT
LP38690/1/2/3 – VIN 2.7V to 10V IOUT 0.5/1.0A

Negative LDO
LP2989 –VIN 2.1V to 16V IOUT 500mA
FlexCap
TPS75005 – VIN 4.0V to 6.5V IOUT 500mA
TPS734/35 – VIN 2.7V to 6.5V IOUT 250/500mA
TPS732/36 – VIN 1.7V to 5.5V IOUT 200/400mA
TPS7A30 – VIN -3.0V to -36V IOUT -200mA
LM9076 – VIN 3.3V to 40V IOUT 150mA
TPS7A49 – VIN 3.0V to 36V IOUT 150mA
TPS7A16 – VIN 3.0V to 60V IOUT 100mA
LM2936HV – VIN 5.5V to 60V IOUT 50mA
50mA TPS7A40 – VIN 7V to 100V, IOUT 50mA
0.8V 10V 100V

VIN
Low Power LDOs
Click to see one
350mA
page overview
TPS720 – VIN 1.1V to 4.5V IOUT 350mA IQ = 38uA
TLV712/02 – VIN 2.0V to 5.5V IOUT 300mA IQ = 35uA
TPS727 – VIN 2.0V to 5.5V IOUT 250mA IQ = 7.9uA VBIAS
LP5904 – VIN 2.2V to 5.5V IOUT 200mA IQ = 11uA High PSRR
High VIN
TLV700 – VIN 2.0V to 5.5V IOUT 200mA IQ = 31uA
Dual
DVS
IOUT
LP8900 – VIN 1.8V to 5.5V IOUT 200mA IQ = 48uA

Value

Low IQ
TLV710/711 – VIN 2.0V to 5.5V IOUT 200mA IQ = 35uA
TPS782 – VIN 2.2V to 5.5V IOUT 150mA IQ = 500nA
LP5900 – VIN 2.5V to 5.5V IOUT 150mA IQ = 25uA
TPS714 – VIN 2.5V to 10V IOUT 50mA IQ = 3.2uA
50mA TPS715A – VIN 2.5V to 24V IOUT 80mA IQ = 3.2uA
1.1V 30V
VIN
Linear Regulator Summary:
“Always” Advantage:
• Low cost
• Few peripheral components
• Small output noise
Disadvantage:
• Lower efficiency @ heavy load
- consider using TI Ultra VDO Parts to improve it
• Uncontrollable startup
- consider using TI “Soft Start” Parts to improve it
• Only Step Down
Power Types
• Linear Regulator
- Inductive
• What is Best
Switching Regulator
A switching regulator can step-up, step-down or invert the input voltage
Switching Element
Regulated
Input
Output
Voltage
VREF Error
REF Amp Sampling
Element
Feedback
Voltage
– Uses inductors for energy storage
– Current flow from input to output is not continuous
– Output voltage is controlled by varying the on time or switching speed of
the pass element
– Input voltage may be greater than, less than or equal to the output voltage
– Switching regulators are designed to allow for higher efficiencies and
often higher power than linear regulators
Understanding the Inductor
V V V
di
V = L⋅
dt
Understanding the Pulse Width Modulation
OSCILLATOR
RAMP
FEEDBACK OUTPUT SWITCH

SIGNAL E/A STAGE DRIVE
COMMAND PWM
COMPARATOR
REF
VOLTAGE
PWM RAMP
CONTROL
ON
SWITCH
DRIVE
OFF
PWM with output filter
Switching Regulator Topologies
three basic switching topologies in common
• BUCK
• Step-down power stage. Power supply designers choose the buck power stage.
the required output voltage is always lower than the input voltage
• BOOST
• step-up power stage. Power supply designers choose the boost power stage.
the required output voltage is always higher than the input voltage
• BUCK/BOOST
• step-up/down power stage. Power supply designers choose the buck-boost
power stage. the output voltage is inverted from the input voltage, and the
output voltage can be either higher or lower than the input voltage.
Buck in a glance
Vout = Vin ⋅ D , D is the duty cycle of the PWM wave

Vout ≤ Vin
Boost at a glance
Vin , D is the duty cycle of the PWM wave

Vout =
1− D
Vout ≥ Vin
Buck-Boost/Inverting in a glance
D
VOUT = −VIN ⋅ , D is the duty cycle of the PWM wave
1− D
VIN ≤ VOUT ≤ VIN
Simplify your design with DC-DC Converters
DC/DC Converter: with internal MOSFET DC/DC Controller: with external MOSFET
SWIFT (TPS54xxx) & TPS60K TPS40K
Advantages: Advantages:
• Easy to use • flexible
• Small • Can be high current output
Disadvantages: Disadvantages:
• Limited output power • More external elements
• Complex
DC/DC Converter Overview
14.0A
10.0A
7.5A Step down DC/DC Converter (SWIFT): TPS54xxx

Output
Current
1.5A
1.0A
Step down DC/DC Converter: TPS62xxx
0.8A
0.3A
0.1A Step up DC/DC Converter: TPS61xxx
Step up DC/DC Converter (Charge Pump)

0.01A
TPS60xxx
REG7xx
0.3V 0.9V 1.8V 2.25V 2.5V 3.3V Input 5V 6.0V 10V 12V 17V 24V 36V
Voltage
Integrated FET DC/DC Converters
Step-Down Converters > 42V Input Synchronous
Non-Sync
3A LM5576
TPS54260
2.5A
LM5005
Output Current (IOUT)
1.5A LM5575
TPS54160
1A LM5574
LM5010A
LM5017 *Sampling Now
LM5006
0.5A
TPS54060
LM5007
350mA LM5008A
150mA LM5009A
50mA TPS54062
3.5V 4.5V 5.5V 6.0V Input Voltage (VIN) 36V 42V 60V 75V 100V
TPS54062 SWIFTTM
4.7V to 60V Input, 50mA Synchronous Step-Down
SWIFTTM Converter
• Fully Synchronous with Integrated • High Efficiency with More than 20mm2 Board
1.5/0.8Ω Power MOSFETs Space Savings. No External Diode Needed
• 100kHz to 400kHz Adjustable Frequency • Synchronizes to Clock to Reduce Noise
• 0.8V Reference with 2% Accuracy Over - • 25°C More Thermal Headroom than Similar
40°C to +150°C Operating Tj Integrated Synchronous Competitors
• 89uA Operating Quiescent and 1.7uA • Improves Light Load Efficiency for Longer
Shutdown Current Battery Life
TPS54062
• Industrial Process Control, Metering,
Security Systems
• 4-20mA Current Loop Powered Sensors
• Low Power Standby or Bias Voltage Supply
• High Voltage Linear Regulator Replacement
TPS54062EVM-695 8 pin MSOP

SwitcherProTM
TPS54062 Powering 4-20mA Sensors
• ADCIN determines how 2-Wire Current Loop Application
much current (Iout) to sink: ~3.5mA budget
Ø 0% = 4mA (must be <4mA) Synchronous Buck Converter
Ø 100% = 20mA
Vin EN
Vout
• High efficiency, low Iq + VIN PH ∩∩∩∩
synchronous buck converter RT/CLK
allows more current than a TPS54062

linear to meet current
budget
Ø Faster micro-controller Vloop to VIN (V+)
VCC
speeds sensors
ADCIN
Ø Additional circuitry Base
• Fixed / Synchronizable DACOUT
- Emitter IIN
frequency of TPS54062 IOUT MSP430
(CLK pin) helps reduce XTR115
noise to analog circuitry Iout
4-20mA Current- Micro-Controller
Loop Transmitter
Integrated FET DC/DC Converters
Step-Down Converters ≤ 42V Input
5A TPS5450
LM25576
3A Synchronous
TPS5430
Non-Sync
TPS54240
2.5A
LM3102
2A LM22680
LM25011
LM25575
1.5A TPS54140
LM3100
LM22672
1A
LM25010
LM3103
0.75A
LM25007
LM25574
0.5A
LM22674
TPS54040
3.5V 4.5V 5.5V 6.0V Input Voltage (VIN) 36V 42V 60V 75V 100V
TPS5430
5.5V to 36V Input, 3-A Step Down Converter
• Integrated 110mΩ N-channel MOSFET • High Efficiency Up to 95%

• Fixed 500kHz Switching Frequency • Small Output Inductor & Capacitor
• Output Voltage to 1.23V with 2% accuracy • High Performance
• Internal Slow Start Circuit • Limits Start-up Inrush Current
• Internal Compensation • Reduced External Components
• Enable Pin • Easy On/Off Control
• Current limit & Thermal Shutdown • Self-Protected from Fault Conditions
• Only 17uA Shutdown Quiescent Current • Low Power Consumption when Switched Off
• -40°C~125°C Operating Junction Temp. • Reliable & Robust at Extreme Temperatures
• Thermally Enhanced 8 pin HSOIC • Small with Good Thermal Performance
• SWIFTTM Software Tool • Quick & Easy Design www.ti.com/swift
INPUT VOUT
VIN PH
• Consumer: LCD-TV, STB, Car Audio Entertainment TPS5430
• Industrial: Point-of-load regulation for 3.3/5V logic BOOT
• Battery Charging off 9-18V AC/DC Wall Bricks

• Distributed Power Systems off 12/24V Bus ENA VSENSE
EVM/Tool GND
• TPS5430EVM-136
• SWIFT Software Tool
1ku pricing: $1.85
TPS54325 & TPS54326
4.5V to 18V Input, 3A Synchronous Buck Converters
• Fast Adaptive On-Time (D-CAP2TM) • High Performance with 2x22uF Ceramic Cout
Control Architecture Eliminates – Faster than 20us transient response time
Compensation Components – Less than 10mVp-p output voltage ripple
• Auto-skipping Eco-ModeTM version – • Helps meet Green Mode and Energy Star
TPS54326 Requirements
• Adjustable Soft-Start Time • Reduces Inrush Currents During Startup
• Power Good and Enable Pins • Easily Implement Sequencing Schemes
• Fixed 700kHz Switching Frequency • Allows 50% Smaller Inductor Value than 350kHz
• Digital TV
• HD Blue-ray DiscTM Player
• Networking Home Terminal Device Iout
Eco-
Mode
• Digital Set Top Box
TPS54325 3-A
TPS54326 3-A ü
TPS54325EVM
TPS54326EVM
All Devices Pin Compatible in 14HTSSOP
And 3x3mm QFN
Point of Load Efficiency Graphs
TPS54326 TPS54325
TPS54326 with Eco-Mode TPS54325
95% 100%
90% 90%
85% 80%
70%
80%
Efficiency
Efficiency
60%
75%
50%
70%
40%
65% 30%
60% 20%
55% 10%
50% 0%
0.01 0.10 1.00 10.00 0.01 0.10 1.00 10.00
Load Current (A) Load Current (A)
1.2Vout 1.8Vout 2.5Vout 3.3Vout 5Vout 1.2Vout 1.8Vout 2.5Vout 3.3Vout 5Vout
• The Auto-Skipping Eco-Mode of the TPS54326 greatly

improves the light load efficiency performance compared
to a traditional fixed frequency DC/DC converter
Low/Mid Vin Integrated FET DC/DC Converters
TPS56221 - 5x6mm QFN VM
25A
TPS56121 - 5x6mm QFN VM
15A
LM21215 - 20eTSSOP VM
LM21212 - 20eTSSOP VM
10A
TPS54020 - 3.5x3.5mm QFN CM
TPS54623- 3.5x3.5mm QFN EM CM

Samples
6A LM21208 - 14eTSSOP VM
Production
TPS54620/2- 3.5x3.5mm QFN CM
TPS54618/78 – 3x3mm QFN CM
VM – Voltage Mode
LM21305 – 5x5mm LLP CM CM – Current Mode
EM – Eco Mode
LM2864 – 16LLP, 16eTSSOP CM
4A
TPS54418/78 – 3x3mm QFN CM
TPS54318 – 3x3mm QFN CM

3A TPS54320 - 3.5x3.5mm QFN
– 16LLP, 16eTSSOP
LM2863CM CM
2A TPS54218 – 3x3mm QFN EM DCAP2
2.95V 4.5V 6.0V 14.5V 17V 18V

Input Voltage (VIN)
DC/DC Controllers
Step-Down Controllers
50A
LM5119 / LM25119 – Current Mode, Dual Channel
40A
Synchronous
30A
LM27402 - Voltage Mode Non-Sync
TPS40055/57 - Voltage Mode w/ Feed Forward
20A
TPS40170 - Voltage Mode w/ Feed Forward
LM5116 / LM25116 – Current Mode
LM5117 / LM25117 – Emulated Current Mode
15A LM3150/1/2/3 – Constant On-Time
LM5088 / LM25088 – Emulated Current Mode
10A
LM5085 / LM25085 – Constant On-Time
5A
TPS40200 - Voltage Mode w/ Feed Forward
LM3485 – Hysteretic PFET Control
4.5 5.5 6 8 10 13 40 42 52 55 60 65 75 80 100
Input Voltage (VIN)
DC/DC Controllers and Converters
Other Topology (Boost, Buck/Boost, SEPIC, etc)
LM2587/8 5A – Boost / SEPIC / Flyback

LM2585/6 3A – Boost / SEPIC / Flyback
LM5118 – Single Inductor Buck/Boost
Features
LM5022 – Boost / SEPIC / Flyback

LM5020 – Boost / SEPIC / Flyback
TPS40210 – Boost / SEPIC / Flyback With FET
Controller
LM5000 2A - Boost
LM5001 1A - Boost / SEPIC / Flyback
LM5002 0.5A - Boost / SEPIC / Flyback
TPS55010 Isolated Fly-BuckTM
3V 4.5V 6V 8V 40V 42V 52V 55V 60V 75V 90V

Input Voltage (VIN)
Portable Switching Power Solution: TPS60K
14.0A
10.0A

Output
Current
1.5A
1.0A
0.8A
0.3A

0.01A
TPS60xxx
REG7xx
Voltage
Buck only
Buck/Boost
TPS60K Buck Products: TPS62xxx new or preview
smallest
Vout package
1.5A (Iq 18uA max) TPS62510 0.6 to 3.8V 3x3 QFN

(Iq 20uA max) TPS62110 1.2 to 16V 4x4 QFN

1.2A
TPS63000 1.2 to 5.5V 3x3 QFN
dual TPS62420 1.0A+0.6A EasyScale interface 0.6 to 6V 3x3 QFN

1.0A
TPS62290 0.6 to 6V 2x2 QFN
TPS62350 CSP I2C interface 0.75 to 1.5V 2.2x1.4 CSP

0.8A (Iq 20uA max) TPS62050 0.7 to 6V 3x5 MSOP
dual TPS62410 0.8A+0.8A EasyScale interface 0.6 to 6V 3x3 QFN

Output
Current 0.6 to 6V 2x2 QFN
TPS62260
(Iq 75uA max) TPS62000 0.8V to 5.5V 3x5 MSOP
0.6A
dual TPS62400 0.6A+0.4A EasyScale interface 0.6V to 6V 3x3 QFN
(Iq 105uA max) TPS62300, TPS62320 CSP 0.6 to 5.4V 2x1 CSP
0.5A
(Iq uA max) TPS62100 0.8 to 8V SOIC
0.4A (Iq 25uA max) TPS62220 0.7 to 6V TSOT-23
(Iq 30uA max) TPS62200 0.7 to 6V SOT-23

0.3A
(Iq 10uA max) TPS62240 0.6 to 6.0V 2x2 QFN
1.8 2.5 2.7 Input Voltage 5.5 6.0 9.0 10.0 17.0V
Boost only
Buck/Boost
TPS60K Boost Products: TPS61xxx new or preview
smallest
Vout package
4.5A TPS61030 1.8 to 5.5V 4x4 QFN
TPS61050 2.5 to 5.5V 2.0x1.5 CSP
2.0A TPS61090 1.8 to 5.5V 4x4 QFN
TPS61029 1.8 to 5.5V 3x3 QFN

1.8A TPS63000 0.7 to 5.5V 3x3 QFN
TPS61200 1.8 to 5.5V 3x3 QFN
1.5A TPS61020 1.8 to 5.5V 3x3 QFN

TPS61059 2.5 to 5.5V 3x3 QFN
Switch
Current dual TPS61100 +LDO 1.5 to 5.5V 4x4 QFN
Limit dual TPS61120 +LDO 2.5 to 5.5V 4x4 QFN
1.3A TPS61130 2.5 to 5.5V 4x4 QFN

TPS61081 2.5 to 27V 3x3 QFN
TPS61058 2.5 to 5.5V 3x3 QFN

1.1A TPS61000, TPS61010 1.5 to 3.3V 3x5 MSOP
Oct. 2007 TPS61161, TPS61171 3.0 to 38V 2x2 QFN
1.0A TPS63700 INVERTER -2 to -15V 3x3 QFN
0.8A TPS61028 1.8 to 5.5V 3x3 QFN
dual TPS61140, TPS61145 LED+OLED 2.5 to 27V 3x3 QFN

0.7A dual TPS61150 LED+LED 2.7 to 27V 3x3 QFN
TPS61070 1.8 to 5.5V TSOT-23

0.6A TPS61001/2, TPS61011/2 1.5 to 3.3V 3x5 MSOP
Oct. 2007 TPS61160, TPS61170 3.0 to 38V 2x2 QFN
0.5A TPS61080 2.5 to 27V 3x3 QFN

TPS61040 1.8 to 28V 2x2 QFN
0.4A TPS61060 CSP 2.7 to 25V 1.5x1.5 CSP
0.3 0.8 0.9 1.8 2.5 2.7 3.3 Input Voltage 5.5 6.0 18V
DC/DC Converter Overview
14.0A
10.0A

Output
Current
1.5A
1.0A
0.8A
0.3A

0.01A
TPS60xxx
REG7xx
Voltage
Power Types
• Linear Regulator
- Inductive
• What is Best
Charge Pump
A charge pump can step-up, step-down or invert the input voltage
Input Switches are internal but capacitors may

Voltage be internal or external
Regulated
Output
VREF Error
REF Amp Sampling
Element
Feedback
Voltage
– Uses capacitors for energy storage
– Current flow from input to output is not continuous - unless push-pull
switching topologies are used
– Output voltage is controlled by varying the off time (pulse-skip mode) or
internal resistance of the charge pump (constant frequency mode)
– Input voltage can be greater or less than the output voltage
– Typically Charge Pumps are designed to allow for higher efficiencies
than linear regulators
Charge Pump
Types of Charge Pump Devices:

Types of Charge pump devices are available in different topologies:
Voltage Doubling (2X) Charge Pumps

• Vout = 2 x Vin
Fractional Charge Pumps

• Vout = N x Vin, where N = device multiplication
– Example: Vout = 1.5 x Vin
Regulated Output Charge Pumps

• Can be 2x, 3x, Fractional, etc.
Voltage Double Charge Pump
Working principle:
VIN
Cin S1 S3
C+
CONTROL
SHDN / CLOCK
Cfly
S2 S4
C-
VOUT
Cout
GND
Voltage double charge pump block diagram (Vout = 2 x Vin)

Voltage Double Charge Pump
Charge Pump Phase Cycle 1: Charge Pump Phase Cycle 2:

Charge CFLY Bootstrap CFLY to the Output
I
VIN I
+ VIN
CIN
- S2 S1
+ CIN
S2 S1
CFLY +
- CFLY
S4 S3 -
S4 S3
VOUT
VOUT
COUT +
COUT
-
Equivalent Circuit for Equivalent Circuit for

Phase Cycle 1: Phase Cycle 2:
VOUT
+
VIN CFLY
+ + - +
CIN CFLY VIN COUT
+ -
CIN
-
Fractional Charge Pump
Working principle: Fractional Charge Pumps:

• Fractional charge pumps
offer a technique to multiply
ENABLE
CONTROL / an input voltage by a non-
OSCILLATOR
integer multiplication factor
• Fractional charge pumps can
have efficiency advantages in
low output voltage
VIN S1
applications
CFLY1
CIN
S2
VOUT
S3
COUT
CFLY2
S4
Fractional Charge Pump
Fraction Charge Pump Works:
•Operates with 2 switching cycle phases (same as a voltage doubling charge pump)
•Two “Flying” capacitors are used:
•In the first switching cycle CFLY1 and CFLY2 are connected in series and placed across
Vin, which effects a voltage divider at Vc = Vin/2 for each “Fly” capacitor.
•In the second switching cycle CFLY1 and CFLY2 are connected in parallel, then switched
to be in series between Vin and Vout.
•Vout = Vin + Vin/2 = 1.5 x Vin
Equivalent Circuit for Equivalent Circuit for

Phase Cycle 1: Phase Cycle 2:
VIN VOUT VOUT
+ + +
VIN VIN
CFLY2 CFLY1 CFLY2
- 2 + 2
+ - - +
VIN CIN COUT VIN COUT
- + - +
VIN -
CFLY1 2 CIN
- VIN -
Regulated Charge Pump
Working principle: Regulated Charge Pumps:

• Regulated charge pumps are
voltage doubling, tripling or
VIN fractional charge pumps with
Cin
an output voltage regulation
S1 S3
SHDN
C+ system and feedback control.
CONTROL
•
Cfly
Regulated charge pumps can
S2 S4
C- provide a stable output
voltage from a varied input
VOUT
VREF supply, which is ideal for
Cout
battery operated devices.
+
GND
Charge Pump Efficiency
Efficiency of Regulated Charge Pumps:
• Regulated Voltage Doubling Charge Pumps
Fixed output voltage level

Input voltage may vary with in the device operating range
The input voltage is doubled, then regulated down to the desired output voltage.
• Theoretical Efficiency = η = VOUT / 2VIN
Example: VIN = 2.8V, VOUT = 3.3V, η = 58.9%

Example: VIN = 3V, VOUT = 4.5V, η = 75%
Charge Pump Efficiency
Efficiency of Fractional Charge Pumps:
• Regulated Fractional Charge Pumps
Fixed output voltage level

Input voltage may vary with in the device operating range
Fractional charge pumps have an advantage in low voltage applications since the
Input to Output difference voltage to be regulated is small.
• Theoretical Efficiency = η = VOUT / 1.5VIN
Example: VIN = 2.8V, VOUT = 3.3V, η = 78.6%

Example: VIN = 3V, VOUT = 4.5V, η ≈ 100%
Charge Pumps Family
Simple Regulator Selection
DC/DC Voltage Conversion
Switching Regulators
Inductive Switching Charge Pumps Linear Regulators

Regulators
Inductive Switching Regulators Charge Pumps Linear Regulators and LDO
When: (typically) (= capacitive switching reg.) When: (typically)
- Step-up, step-down When: (typically) - Step-down applications
or inverting applications - Usually step-up (boost) - Narrow input voltage ranges
- Wide input voltage ranges or inverting applications - Cost more important than
- High efficiency is a key - Medium input voltage ranges efficiency (40% to 60%)
care-about (80% to 95%) - Efficiency is a major care- - Ultra Low Noise
- EMI not a major concern about (70% to 90%) - Ultra Low EMI & output ripple
- Low EMI is major care-about
- usually more extra parts - Few extra parts
- few extra parts
Complex Switching Design
• Inductor, Capacitor Value

& Material selection
• Feedback Loop Stability
• PCB Layout
SwitchPro Introduction
• Help you to select the Right Device
Step1 input parameters
Step 2 and Step 3: find the right device
Design it just by a simple click
Analyze it!
Get the Recommend PCB Layout
Where to Find It
• www.ti.com/analogelab (“Design” Section)
• www.ti.com/switcherpro (Tool Folder)
• www.ti.com/switcherpro-dt (Desktop download)
WEBENCH Designer
WEBENCH® Architect Tools
Power Architect (multi supply)
Processor Power Architect
FPGA Power Architect
LED Architect (enter lumens)
WEBENCH® Designer Tools

Power (single supply)
LED (enter LED)
Sensor AFE & Sensor Interface
Active Filters | Amplifiers
EasyPLL
TI Power Reference Design Search Tool
§ Easy to use search tool
§ Search by input / output criteria, application, topology
§ Can export list to excel spreadsheet
§ Provides link to the reference design folder for detailed information
§ Popular designs available at www.ti.com/powerlab
Switch Power PCB Design
Worst Case Layout
What’s wrong right with this layout?

What Causes Layout Issues?
• Changing currents through stray

inductance produce unwanted voltages
dI
Vstray = Lstray
dt
• Changing voltages across stray

capacitances produce unwanted currents.
dV
Istray = Cstray
dt
Review of SMPS - BUCK
Fast Changing Vin

Fast Changing
VOLTAGE
CURRENT gnd Fast Changing
CURRENT
TPS62510
Supply Low Pass Filter Output

Voltage (LC Output Filter) Voltage
PWM
Feedback
Voltage to
duty cycle
conversion
Noise Sensitive
Traces
General High Frequency Board Layout Rules
q Keep input capacitor close to the IC with low inductance

traces.
q Use single point grounding.
q Isolate analog signal paths from power paths.
q Keep trace from switching node pin to inductor short:
Reduce EMI emissions and noise that may couple into other
portions of the converter.
q Output voltage feedback sampling must be taken right at
output capacitor and shielded.
q Always think about the parasitics!
Routing Rules (cont.)
q For high dv/dt signals keep copper to a minimum to
prevent making unintentional parallel plate capacitors
with other traces or to a ground plane. Best to route signal
and return on same layer.
q For high di/dt signals: keep traces short, wide and closely
spaced. This will reduce stray inductance and decrease
the current loop area to help prevent EMI.
q Always avoid vias when possible. They have high
inductance and resistance. If vias are necessary always
use more than one in parallel to decrease parasitics.
q Do not use an auto-router or pour ground planes. Always
manually route and pour grounds to keep single point
grounding scheme and avoid current loops.
Miscellaneous Rules for Inductors
• Always use shielded inductors to reduce magnetic field
coupling.
• Keep ground planes out from under inductors and common
mode chokes.
• Do not route noise sensitive traces (such as feedback lines)
under inductors.
• If there is more than one power supply on the board then try to
separate the inductors as much as possible. The magnetic field
in one inductor can cross couple to the other. One converters
switching frequency will modulate on the other creating several
new frequencies as well as make the converter have poor
performance.
Good Layout – Base Line
PGND FB GND (output)
C3, R1 & R2
AVIN
GND (input) Feedback Network
PVIN R2
AGND
R1
C4 C2
C2 – Output
SW Capacitor
C4 & R5 – Analog C1 Vout
power filter Vin
L1
C1 – Input Capacitor 250 mils

(6.35mm)
Poor Input Capacitor Layout
• Input capacitor moved 110 mils farther from IC.
C4
R1
GND
Vin
C1
Capacitor Layout Stray Inductance
Symptoms of Poor Input Capacitor Layout
• Poor load regulation

• Switching frequency jitter
• EMI radiation
• Won’t start up at power-up
Poor Input Capacitor Comparison
• Compare the measured results of the poor input capacitor to
the base-line layout. (input ripple shown).
The poor layout generates

over twice as much input
ripple. This ripple can
propagate back through
the input power lines and
radiate EMI.
Input Load
Clock Jitter
Ripple Regulation
(ns)
(mV) (%/A)
Base Line 13.5 140 0.07
Poor Input Capacitor 18 300 0.11
Poor Feedback Sampling
Feedback
sample is not at
output
capacitor
Path of ripple Path of changing

currents and load load currents
currents
Symptoms of Poor Feedback Layout
• Poor load regulation and load transient behavior.
Load Output Droop due to

Regulation Load Step (mV)
(%/A) No load to full load
Baseline 0.07 120
Poor Feedback 0.19

220
A Very Bad Layout
GND (input) Star ground is

at wrong point
Power and GND (output)
Analog grounds C2
Feedback trace
are mixed on
is routed under
board
inductor
C1 Vout
L1
Vin
Poor input cap. R2 R1 Feedback

placement Feedback sampled at
network wrong point
grounded to noisy
power ground
Bad Layout Problems
• IC would not start up properly with load.

• Would not regulate with load.
• Two errors made the biggest impact for this
layout.
– Routing the feedback trace path under the
inductor.
– Poor grounding
Worst Case Layout
What’s wrong right with this layout?

PS with Shared Load and Analog Ground
ZT1 ZT2
Changing load current act through ZT1 to produce output voltage error.
PS with Separate Load and Analog Ground
AGND
Separate grounds so load current does not pass through Zt1.
Comparison of All Layout Examples
Input Load Output Droop due to

Clock
Ripple Regulation Load Step (mV)
Jitter (ns)
(mV) (%/A) No load to full load
Baseline 13.5 140 0.07 120
Poor Input Capacitor 18 300 0.11 125

Poor Feedback 14 140 0.19 220
All Bad Does Not Operate
期待与您合作！
frank-huang@ti.com
ti_cup@126.com
13764149990

TI簡介模擬電子培訓資料

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Agenda

Precision Audio Interface High

ØA/D Converters ØAudio Amps ØRS-422/485 ØA/D Converters ØSystem-on-Chip

ØD/A Converters ØAudio Converters ØIsolation, CAN ØD/A Converters ØTransceivers

ØShunt Monitors ØLine Receivers ØClock Distribution ØANT

ØComparators ØCCD AFEs ØClock Generation ØBluetooth® low energy

2nd Order LPF with Fc = 1MHz

Voffset 2.5 5.5MHz的OPA340

2nd Order LPF with Fc = 1MHz

V of f set 2.5 200MHz的OPA354

• 自归零，零温漂 Auto Zero & Zero Drift

• 轨到轨输入/输出 Rail-Rail Input/Output

• 自归零，零温漂 Auto Zero & Zero Drift

• 零交越失真 Zero Crossover

• 轨到轨输入/输出 Rail-Rail Input/Output

• 零交越失真 Zero Crossover

• Zero-Crossover Input Topology • Excellent signal linearity over entire input

• Single Supply Data Acquisition

Standard Two-Stage Input VSS

Frequency Spectrum (16384 Point FFT)

供电电压 设计要求 典型应用 推荐运放工艺 推荐TI产品家族

R-R，低噪声，精密， OPA3xx, OPA7xx,

1.8 V to 5.6V 消费电子，视频， OPA35x, OPA6xx,

差模电压Differential Voltage (VDIFF) – 运放V-和V+包含的不同的信号成分

(1.5V) VCM = (VIN++ VIN-) / 2

When R2=R1 = R4=R3 => Vout = (V1-V2) x Gain

Instrumentation Amplifiers (INA)

Difference Amplifiers Instrumentation Amp Current Sense Amp

CMRR = 20 ∗ log(x) ► 1% 的电阻精度 = 40dB

优势: 极高的输入阻抗， 高增益范围，高CMRR

VA1 = VCM(1+R1/RF) - (VDIFF/2)(1+2R1/RG + R1/RF) – VREF(R1/RF)

CMRR VS Frequency CMRR VS Frequency

• When to choose low side current sensing

• When to choose high side current sensing

Strength: Common-mode range not related to supply voltage

• Precision Current Source

Resistor Range from 5k to 20k:

Bridge Output DMV from -143mV to 200mV

INA128 Output = (INAV+－INAV-)*(1+50k/R8) + VREF,

When theoretical Resolution > Required Accuracy,

12 bit ADC: let’s use MSP430’s internal ADC12 (200ksps)!

VIN S/H + FS: Full Scale

•16-Bit, 500kSPS, Serial ADS8318/19

Increasing Performance, Improved INL and Lower

8 - 16 bit 12 - 18 bit 12 - 16 bit

ADS7229 ADS8422 ADS786x

up to 1MSPS up to 4MSPS up to 1MSPS

CMV Rejection + DMV Amplify + Level Shift

Is there a kind of ADC to achieve all these three functions?

+/- 200mV Maximum

• VIN+ Can be either greater or smaller than

Analog Input Multibit output

SNR = 6.02N + 1.76dB ; (for an N-bit ADC

Same total noise, but spread over more frequencies

Average noise floor

SNR = 6.02N + 1.76dB + 10 log(Fs/2*BW)

Noise removed by filter

SNR = 6.02N + 1.76dB

The integrator serves as a

The result is noise shaping

Digital filter response

Economic Highest Precision Integration Wide Bandwidth

12 - 16 bit 16 - 31 bit 16 - 24 bit 16 - 24 bit

ADS111x ADS128x ADS124x ADS16xx

供电电压设计要求典型应用推荐运放工艺推荐TI产品家族

优势: 极高的输入阻抗，高增益范围，高CMRR

Reference Voltage VRef Digital Supply Voltage DVDD