VLSI FOR ALL

www.vlsiforall.com
 Cerium system Pvt Ltd

Table of Contents

Qualcomm interview questions - 1

Qualcomm interview Questions -2 VLSI FOR ALL

Qualcomm Interview Questions -3

Qualcomm interview questions - 4

Qualcomm interview Questions -5

Qualcomm Interview Questions -6

Qualcomm Interview Questions -7

Extra Questions

Qualcomm interview questions - 1

1) Introduce yourself
I have worked for 2.2 years in PD. Initially I was working with DigiComm, from there, I went to
Sandisk. Worked on 2 Projects. Then I went to Infosys. I worked for Intel Project. I did 2 projects
there.

2) Which company you worked previously ?

I was working at Infosys for Intel Project. VLSI FOR ALL
3) How many projects you handled till now?
Based on resume/CV.

4) What was the duration of your recent project?

Based on resume/CV

5) How you started your project?

I started with floor plan. The DEF file was given to me. It had aspect ratio set, and die size defined. IO
Ports were already placed. I started with macro placement. Then went till routing stage.

6) Explain the issues and fixes you done in your recent project ?

Floor plan issues-

There was notch issue in macro placement. Did multiple trials for avoiding notch issue. Placed
macros based on hierarchy. Followed the guidelines for macro placement. Checked for pin and
macro alignment.

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

Placement Issues -
I got timing violations, since module was splitted during placement. I used placement bounds to fix
setup timing. Then because of cells sitting closer, congestion due to cell density got increased. We
used keepout margin to fix congestion.

CTS Issues -
CTS goal was to fix skew and latency in clock path. In CTS, I got many shorts since since tool had
routed many signals in layers which were reserved for CTS.

Routing Stage -
We faced timing violations in routing stage which we took to prime time and fixed it.

7) What are the inputs for pd and what it contains ?

Mainly, the inputs for PD will be netlist, libs, lefs, tlu+, tech file, io assignment file, upf,

8) What is setup and hold time ?

Setup Time- Minimum time before which data signal should be held steady before the active clock
edge so that the data can be captured reliably by the flop.
Hold Time- Minimum time for which data signal should be held steady after the active clock edge so
that the data can be sampled reliably by the flop.

9) What is timing report? What does it contain?

Startpoint: in1 (input port clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk1
Path Type: max
Point Incr Path VLSI FOR ALL
-----------------------------------------------------------

clock clk (rise edge) 0 0 clock

network delay (propagated) 0 0
input external delay 7500 7500.00 f in1
(in) 142.37 7642.37 f i1/INPUT1
(iinvc) 0.33 7642.70 f i1/OUTPUT1
(iinvc) 1469.09 9111.79 r
out1 (out) 14.66 9126.45 r
data arrival time 9126.45

clock clk (fall edge) 10000 10000 clock

network delay (propagated) 0 10000
output external delay -6000 4000
data required time 4000
-----------------------------------------------------------

data required time 4000

data arrival time -9126.45
-----------------------------------------------------------

slack (VIOLATED) -5126.45

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

10) What about STA? What are the things you come across in it?
During STA, we try to fix max cap, max trans, max fan-out, setup, hold related issues. We take the
updated netlist along with spef, .sdc, .lib in prime time and fix timing in all corners.

11) What is fixes you done for both setup and hold? Explain in detail?

12) Utilization after floor-plan and placement? Also, total design utilization?

13) Which are the scripting languages you know?

I know perl basics.

14) How much time you took for each fixes in each stages?

15) What is the runtime for placement?

20 hours

16) What is the duration of your recent project?

6 Months

17) Have worked on both innovus and icc2 tool?

Icc only

18) Have you done pv checks? What are those? Explain in brief.
For PV, different team was there. I fixed only shorts.

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

Qualcomm interview Questions -2
1st round (PD Profile)

1. How you start your floor-plan?

Floorplan DEF was given to me. I did read_def. It contained block shape and sizing done. I/O Ports
were placed. After that, I placed macros based on hierarchy.

2. Qualifying for each stage?

3. Numbers - Timing, Congestion? It might vary from project to project

4. Diff between set_false_path and set_disable_timing ?

When a false path is set, timing arc will exist and tool will calculate it but will not report. While, if
disable timing arc is true then, tool will not calculate the timing and there will not be any timing arc.

5. If an uncertainty already added to the paths why don’t you check hold before CTS.
The uncertainty before CTS is just an estimate and not real one. The clock is ideal before CTS and
hence we prefer to check once clock is synthesized.

6. Steps to minimize the WNS before Routing and ECO.

7. TAP Cell distance, who will give you the number ?

Tap cell distance was 20um and was given from foundary.

8. What is the Name of the check for missing tap for cell?
Preplacement checks

9. How will you highlight the net in the GUI?

Change_selection in ICC
VLSI FOR ALL
10. Diff between %hash and @array?
Hash is not ordered set of objects while an array is.

11. Write a script to find all the instances with Name inst_* from report?

2nd round (STA Profile)

1. How will you place macro?

I will place macros based on hierarchy and data flow diagram.

2. What are physical cells ?

End caps, Tap cells, Decap Cells, Fudicial Cells, Tie Cells, Fillers.

3. Timing Numbers each stage?

Project Based

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

4. What were target skew and Target Latency ?
Answer based on clock frequency, block size.

5. How did you achieve your skew with this latency number - your block contains 11.89 million
gates?

6. How will you try to minimize the timing in placement and CTS stage ?
Usually placement bounds and path grouping is used to minimize timing in placement stage. In
CTS we can use high driving strength buffers, replace buffers with pair of inverters etc. to
minimize timing.

7. Consider your latency is more, how will you minimize it after CTS is done? We can reduce latency
by using upsized buffers in CTS.

8. How target latency can be achieved?

I had set lesser target than actual one in my CTS Spec file. Hence I was able to meet my target.

9. If a block is placed between two flops, and also combinational path also split due to that, routing
detoured. In this path, timing violation is there, how you will meet timing in this case?

10. Rectilinear block is given to you, how will you proceed?

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

Qualcomm Interview Questions -3
1st Round

1. What are inputs to PD?

Go here.

2. Explain issues faced while placing macros.

3. What was your tap-cell spacing?

20um

4. What issues did you face in placement stage?

Congestion and timing related issues.

5. How tool calculates cap and trans? How does it come to know that cap and trans are violated ?

6. How will you fix cap and transition violation?

VLSI FOR ALL
7. How will you qualify your placement stage apart from timing checks?
Apart from timing, we need to see that there is no congestion. Also, there should not be excessive
buffering done by tool. The floorplan utilization should not shoot up too much.

8. How did you decide uncertainty in placement stage?

Uncertainty is skew + jitters. Overall, it should be around 25%-30% of clock period.

9. How will you qualify CTS apart from timing checks?

Apart from timing, we need to see crosstalk violations, floorplan utilization, target skew and latency
should meet.

10. If setup is violated by 200ps, your clock period is 1ns, and what will you do next. Will you proceed
for routing or go back to rerun CTS after applying fixes for timing violation?

11. If setup or hold is violated at last. Can you still proceed for tape-out? If yes, how will you proceed?
Yes in setup violation, we can proceed for tape-out with reduced frequency.

12. Scenario based question for ECO Stage:

a. If data path is optimized, and setup is violating by 100ps. What will you do to fix
timing?
b. Continuing above, if setup is also violating by 150ps in next path, and data path is
again optimized now what can be done.
13. What was your latency after CTS? How did you achieve it?

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

14. If tool has optimized the clock tree and still the skew is not met in 2000 paths. The clock buffers
used in tree are of highest available strength. What will you do to fix skew? In that case, mostly it
could be related to fan-out of clock.

15. If you have fixed setup in one path but it led to hold violation. List all possible causes for this and
how will you fix it.

2nd Round

1. Explain full PD Flow.

2. Inputs for each stage. How will you proceed from beginning?
Go here

3. Issues faced in each stage.

Go here

4. Commands for each stage.

VLSI FOR ALL
Go to Mediatek face to face interview questions-2, Question no 16

5. How tool calculates cell delay?

Tool calculates cell delay based on input trans and output load

6. What are timing models available for calculation of cell delays?

There is non-linear delay model and concurrent current source model. Tool prefers CCS since it is
more accurate.
7. How tool calculates library setup time?
For one corner, characterization of setup time is done and table is made for input Trans and output
load. Tool will pick-up setup and hold values from this table.

8. For a same standard cell used at many places in design, why library setup time is not reported
same across design?
Library setup time for same flavor of standard cell will vary across different corners. For one single
corner setup time is same.

9. What sort of scripts did you work on. Then, Scripting related questions ?
10. How will you get all cells and instances of same hierarchy?
11. Commands for timing fixing.

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

Qualcomm Interview Questions -4
1) Complexity of recent project

2) How do you say a floorplan is good?

We say a floorplan is good after verifying following checkpoints:
i) All macros are placed to the edge of core and there should not be any
overlapping macros.
ii)There should not be any notches in design. iii) All pins must be aligned
to the center of track. iv) All macros are place.

3) Is utilization depends on floor plan after place opt ?

4) How do you fix congestion and timing ?

Congestion occurs when numbers of routing tracks available for routing are less than required
routing tracks.
Types of Congestions:
a. Congestion between macros
i. First check fly lines, check net connections, place macros connecting each other
closer
ii. If there is more connection from macro to macro, place those macros nearer to
each other preferably nearer to core boundaries
iii. If input pin is connected to macro, better to place nearer to that pin or pad iv. If
macros have more connections to std cells, spread the macros and add soft
blockage if not added already
b. Congestions in core VLSI FOR ALL
i. Local congestion - Check for pin and cell density. Spread cells and insert partial
blockage if necessary
Pin density is due to more pins in particular area. For example, OAI, AOI has
more pins and it causes pin density
ii. Global congestion - Check for cells causing congestion. Do the cell
padding/keep out margin
iii. Module splitting - Tool splits the modules sometimes, causing the congestion
by using routing resources

5) How do you find channel between macros ?

Channel length between macros = (pin pitch*no of pins) + space between pins
Number of horizontal/vertical metal layers

6) Did u have any feed through pins ?

No there weren't any feed through pins.

7) What does spec file contains ?

Spec file contains, target skew, target latency, NDRs, and information related to which buffers to
use for CTS.

8) For leaf cell and non-leaf cells to which cells you apply NDR ? We apply NDR to leaf cells.

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

9) What is use of ndr in spec file ?
NDR is used to specify what metal width and spacing to use in CTS or routing stage. With use of
define_routing_rule command, ndr can be specified.

10) Different flavors of lvt devices and hvt cells and which lvt is used for setup and which lvt cell
for low power?

11) How did you fix DRC w.r.t. double patterning, which metal layers had double and triple
pattern ?

12) How did you fix LVS from Calibre ? #Calibre

13) Inputs for Star rc and inputs for pt shell ? Star RC - .v, DEF, Tech file, Output - SPEF file how
Spice netlist is generated ?

14) Explain routing which net will u route first ?

Firstly, routing will be done for power domains, then for clock domains and last for data signals.

VLSI FOR ALL

Qualcomm Interview Questions -5
1) How you will analyze the congestion?
Report_congestion, it will report grc overflow. For other congestion, we give keep-out margin or
partial blockage. To analyze congestion, you can use, report_congestion -routing_stage

2) Causes of congestion?
Congestion could be caused due to mainly due to cell density, pin density or module splitting.

3) Contents of spec-file?
Spec file is input to CTS Stage. It mainly contains, target skew and target latency (insertion delay). It
also contains NDRs and other details like which buffers to use for building the CTS.

4) CTS methodology and commands Following are commands for CTS:

Cts_opt (synopsis)
Cco_opt (cadence)
In CTS, the aim is to reduce the skew and insertion delay and balance the clock tree. For this, the
tool follows one algorithm, (it could be H-Tree/Pie/Fishbone etc.) and constructs the clock tree and
balances it. The tool will also place clock buffers to ensure signal quality.
For common problems related to clock tree, we can check it using the command, check_clock_tree.

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

5) Explain routing in detail?
Routing is the process of creating physical connections based on logical connectivity. Signal pins are
connected by routing metal interconnects. Routed metal paths must meet timing, clock skew, max
trans/cap requirements and also physical DRC requirements.
There are four steps of routing operations: Global routing, track assignment, detailed routing. Global
route: It identifies nets with shortest path and assigns them to specific metal layers and global routing
cells. It avoids congestion, detours and blockages. Uses steiner tree or maze algorithm.
Track assignment: It takes the global routed layout, assigns track to all nets. It performs DRC
unaware assignment.
Detailed routing: Performs DRC aware routing. It is the final stage of routing.

6) What are the inputs for star rc ?

.nxtgrd (it contains where to pick the delays from, nothing but mapping file), tluplus Routed
db (DEF/GDS)

7) How will you add end cap n tap cells Following are the commands:
add_end_cap
add_tap_cell_array

8) What is the use of filler cells and purposes of metal filling?

filler cells are added to the core area to avoid base drc errors. Similarly metal filling is also done to
avoid metal drc error. Base and metal drc guideline are provided by foundry to add minimum certain
percentage of material for increasing yield.

9) Explain clock gating? VLSI FOR ALL

Clock gating is the method of gating clock signal so that we can save clock power by turning off te
gate in case a certain gated portion of design is not in function.

10) What happens if u put dummy metal in combo path and will it affect other metal?
Dummy metal is added to increase the yield but it may cause shorts, drc violation, if it is cross talk
with data metal then causes timing effect in data path.

11) When you will do clock push?

Clock push is done in the event of utilising the useful skew. We insert delay cells in clock path to
push the clock and use the skew to meet the slack.

12) How will you analyze the report?

13) ECO timing fixing commands?

fix_eco_timing -type setup
fix_eco_drc write_eco_changes
filename

14) How will you fix LVS and DRC?

LVS is layout vs. schematic check. It’s Verilog netlist vs layout netlist check. Typical example of LVS is
open nets, short nets.

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

15) What are fixes of setup apart from buffering, upsize, VT cell swapping? Useful skew, detour net,
cloning.

16) Explain all commands in each stage in ICC.

Stage wise commands in ICC: a)
Sanity Checks:
i. Netlist Checks – Check_design/ Check_mv_design (Checks the current design for
consistency). ii. Sanity Checks – Check_timing (Checks for possible timing problems
in the current design).
iii. Library Checks – Check_library (Performs consistency checks between logic and
physical libraries, across logic libraries, and within physical libraries).
iv. Netlist vs SDC – Report_timin g (Displays timing information about design). b)
Floorplan Stage:
i. Source your ioports.tcl file in icc shell
ii. get_attribute [get_ports *] is_fixed
If port fixing not done, then set_attribute [get_ports *] is_fixed true
iii. Hand place your macros iv. Check_legality -verbose : Checks the floor-plan
for any overlaps

c) Placement Stage:
Pre-placement
VLSI FOR ALL
i. read_def: reads the design data file in def format
ii. add_end_cap: adds end cap cells to current design Example -
add_end_cap -lib_cell cellName
iii. add_tap_cell_array: adds tap cells to the current design Example:
add_tap_cell_array -master_cell_name cellName -distance
distanceValue iv. check_legality: Checks if all cells placed so far are fixed
and not overlapping.
v. place_opt:
vi. insert_buffer/add_buffer_on_route: vii.
magnet_placement:

d) CTS Stage:
i. Get_clocks : displays all the clocks in your design
ii. Report_clocks –clock_name : displays clock information of particular clock
iii. Define_routing_rule : Defines NDR for clock.
Example:
define_routing_rule new_rule -default_reference_rule -widths {m1
0.8 m4 0.9} -spacings {m1 1.0 m4 1.0}
You can specify the reference rule with respect to which NDR is defined. It could be
default_reference_rule too. You need to specify only one reference rule at once.
iv. set_clock_tree_options –routing_rule rule_name –clock_trees
clock_name : It will link the ndr defined above to specified clock clock_name.

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

v. set_clock_tree_references : specifies the buffers, inverters, clock gates to be
used in CTS.
vi. Clock_opt: creates the clock tree, routing of nets, performs extraction and
optimization and hold time violation on the design. vii. Check_clock_tree : Checks
the clock trees of the current design for common problems that can adversely impact
clock tree synthesis.
e) Static Timing Analysis:
i. group_path: ii.
check_timing:
iii. psynopt -area_recovery -congestion: iv.
report_port:
v. report_qor: vi. report_timing -from -to -
trans -cap -net:
vii. report_constraints:
f) Routing Stage:
i. Global routing: route_zrt_global
ii.
iii.
Track Assignment: route_zrt_track
VLSI FOR ALL
Detailed routing: route_zrt_detail -max_number_iterations 20 iv.
route_opt will do all above three actions in single command.

17) Explain latch up problem briefly.

Latch up is development of low resistance path inside CMOS which is not fabricated by design, but
develops because of many CMOS connected in parallel. To avoid latch up, Tap cells are placed
periodically to break that low resistance path.

18) TCL scripting ( for each ,while , array based )

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

Qualcomm Interview Questions -6
1) Write the prime time report?

2) Causes of timing violation in placement stage?

Timing violation in placement stage is due to congestion in standard cells, also HFN.

3) What are the causes of congestion?

Floorplan stage: Congestion can occur in floor-plan stage while placing macros and leaf cells. To
avoid this, we may use following command:
create_fp_placement -congestion_driven

Placement Stage: Congestion in placement stage is mainly due to high pin density or cell density. To
avoid congestion, we can use methods like spreading of cells, use of partial blockage etc. Command
for congestion driven placement is create_placement -congestion.
create_placement -congestion
create_placement -congestion_effort low|medium|high
We may also use refine_placement for refining the placement.
refine_placement -congestion_effort low|medium|high
Congestion effort option specifies the effort level for congestion mode. The default effort level is
medium.
VLSI FOR ALL
CTS Stage: Congestion can also occur in clock tree synthesis.
clock_opt -congestion
The clock_opt is for creating and optimizing the clock tree. Argument -congestion tells the tool to
optimize the clock tree with congestion driven mode.
clock_opt_feasibility -congestion
This command performs analysis on design after CTS for optimization. -congestion argument tells
the tool to remove congestion in CTS.
psynopt -congestion
Psynopt is incremental optimization on the design. Enables congestion removal algorithms for
improved routability. By default, the command does not perform congestion removal.

Routing stage: report_congestion -routing_stage global|track|detail

Above command reports congestion map for routing stage, we need to specify weather it is global
route congestion map, track assignment congestion or detailed congestion map. By default, it is
global. The effort to create the map will be medium. To change effort, we can specify it with -effort
argument.

4) Skew, slew, Trans Everything is fixed. Latency is more why you have to reduce the latency? If
latency is more, chip might consume more power.

5) How will you get to know which buffers to use for CTS stage?
It will be mentioned in .spec file, which buffers to use. In ICC, One can use command
set_clock_tree_references for telling the tool which clock buffers to use for which clock.
Example:

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

icc_shell>set_clock_tree_references -clock_trees CLK1 -references
buffer4x

6) How tool will take buffers for CTS, if it's not mentioned in spec file? The tool will take default
value.

7) Inputs for prime time?

Gate level net-list, Libraries, SDC, SPEF, SDF are input to prime time.

8) Commands for keepout margin?

Select the cell = get_selection
Give keepout margin = set_keepout_margin –type soft –outer {1 1 1 1} [get_selection]

VLSI FOR ALL

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

Qualcomm Interview Questions -7
1) What was complexity of your recent project?
2) What you did in every stage, and what were the challenges faced?
3) Your recent project is on 14nm and previous projects are on 28nm. What was the difference in
implementing the design.

4) If timing is not met during placement stage, can you still continue for CTS?
We should keep on checking the log continuously, and we will observe the value of WNS. If it keeps
on increasing to large value then we need to see our floorplan again.

5) What was the setup and hold values. What was WNS in placement and CTS stage?
WNS - 800 pS others were in range of 300-500 pS
WNS after fixation of timing was 300 pS

6) How many paths were violating and how you fixed?

After routing, there were around 200 path violations for setup and 150-160 path violations for hold.
We took design to primetime and did timing fixations in PT.

7) To fix timing, did you use PT ? If yes, what were the commands.
fix_eco_timing -type setup #setup
fix_eco_timing -type hold #hold

8) How did you fix IR Drop issues in pnr.

Static IR - Increase strap width (Change power.tcl)
Dynamic IR - Use decap
VLSI FOR ALL
9) What were the guidelines given to you by PV team for your design.

10) What is difference between Graph based and Path based analysis.
GBA Mode is more pessimistic and less time consuming.
PBA is more accurate and more time consuming.

11) Out of GBA/PBA which one you use during AOCV and why ?
PBA is more pessimistic. AOCV is more accurate analysis. It considers PBA only. report_timing
-pba_mode

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

Extra Questions
1) What are inputs to PD ?

a) Netlist (logical connection connections)

b) SDC (Design constraints)
a. Clock Definition, Uncertainty, Latency
b. IO Delays
c. DRV Constraints (Max transition, Max capacitance, Max fanout)
d. Path Exceptions (False path, Multicycle Path)
c) Libraries (lib, tlu+, lef, tech file)
a. Logic
b. Physical
c. Timing
i. Modes
1. Func
2. Test
a. Scan capture
b. Scan shift
c. Scan AC
d. Scan DC
ii. Corners
d. Technology file
d) IO Assignment File
2) Explain Antenna Effect ? VLSI FOR ALL
Antenna effect is plasma induced gate oxide damage that can cause reliability problems in manufacturing
of MOS ICs. It occurs due to accumulation of charge carriers near the gate of transistor. The tool will
calculate if metal area connected to gate is more than gate area then, charge accumulation will occur and
may damage the gate. Hence, we need to reduce it. It can be done by use of metal jogging technique (use
of higher metal layers), use of standard cells or use of reverse bias diode.

3) What is Electromigration ?

It is the slow displacement of metal atoms in a semiconductor. It occurs when the current density is high
enough to move metal ions in direction of electron flow. This phenomenon causes the eventual loss of
connections or failure of a circuit. Hence, the circuit faces reliability issues. To test for reliability, the DUT
is put under high temperature operating life conditions, and the data obtained is extrapolated to estimate
the durability.

4) What is difference between keep-out margin and blockage?

Ans - Keep out margin is attached to cell/instance, which means if you move cell/instance the keep-out
margin also moves along with the cell. Blockage depends on its coordinate; hence it stays in the same
place.

5) How exactly is Well TAP cells used to overcome latch-up?

Tap cells ensures n-well substrate continuity in the design. Tap cells should be placed such that they have
uniform horizontal periodicity and vertical continuity in the design. Horizontal periodicity reduces when

www.vlsiforall.com
 Cerium system Pvt Ltd

VLSI FOR ALL

we migrate the design from upper node to lower node. Vertical continuity can be disturbed only if macros
are placed in the path of the tap cells.

6) What are all the ways to fix setup violation?

Remove/reduce buffers from data path

Replace existing buffers, with buffers of faster slew
LVT Swap
Upsizing the buffers
Reduce the net delay by using higher metal resources
Clock pushing (de-touring the clock to slow it down)
Cloning (dividing the load by adding a clone of buffer to make it fast)
Replace buffers with two inverters placed farther apart
Readjust the position of buffers 7) What are commands for
sanity check?

Ans – Netlist Checks - Check_design

SDC Checks – Check_timing
Library Checks – Check_library
Netlist vs SDC – report_timing VLSI FOR ALL
8) How will you create the logical power and ground connections in design?

Ans – derive_pg_connection will connect power and ground pin to specified power and ground
nets. To verify weather all power and ground pins of standard cells, macro cells are connect ed to
corresponding power and ground nets, we can use verify_pg_nets.

9) What is the use of Tie cell ?

Ans - Tie cell is normally used to tie the standard cell or spare cell or any floating input to a known state.
We don’t connect standard cell to a power rail directly, because, it can cause loading issues on rails. Tie
cell helps in reducing the load.

10) What are the sign off checks you performed and how did you do it. Explain with commands. Sign
off checks - DRC and LVS.

11) While analysing setup at worst case slow corner, we don’t derate the late path, however we
derate the early path. Why ?
In slow corner (worst case slow), the data path is already the slowest possible. Hence, we don’t derate it
further.

12) Explain the analysis of in2reg, reg2out, in2out timing analysis ?

13) How tool will know that clock is ideal in placement stage ?

14) What is pipelining technique for fixing the timing of design ? How is it used, explain with commands
?

15) How synchronous cells help in meeting the timing ?

www.vlsiforall.com