CMPE 363

Input Output
Chapter 7 (Stallings Book)

Fall 2022

Note: Slides are based on textbook slides which are © 2016 Pearson Education, Inc.

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Topics
 I/O Modules
 External Devices
 Programmed I/O
 Interrupt- Driven I/O
 Direct Memory Access
 I/O Channels and Processors
 External Interconnection Standards

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Generic Model of I/O Module

3
Input/Output Module
 An I/O module interfaces to the system bus and controls
one or more peripheral devices.
 An I/O module contains logic to perform a
communication function between peripherals and
system bus (not just connectors)
 Why don’t we connect peripherals directly to the system
bus:
 Wide variety of peripherals
 Delivering different amounts of data
 At different speeds
 In different formats and word lengths
 Data transfer rate of all peripherals are much slower than CPU
and RAM, so it is impractical to connect peripherals directly to
system bus. 4
Input/Output Module
 Need I/O modules. They have two main
functions:
 Interface to CPU and Memory via system bus
(internal I/O interface)
 Interface to one or more peripherals by tailored
data links (external I/O interface)

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External Device Block Diagram

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 External Devices – (1)
 An external device attaches to the computer by a link to an
I/O module.
 The link is used to exchange control, status, and data
between the I/O module and the external device.
 An external device connected to an I/O module is often
called a peripheral
 External devices can be classified into:
 Human readable (communicating with computer user)
 Screen, printer, keyboard
 Machine readable (communicating with equipment)
 Magnetic disk and tape systems
 Sensors and actuators, as in robotics
 Communication (communicating with remote devices)
 Modem
 Network Interface Card (NIC) 7
External Devices – (2)
 Interface to I/O module is in the form of control,
data and status signals
 Control signals determine the function that the
device will perform, such as send data to I/O
module, accept data from I/O module, report status,
or perform some control function particular to the
device (e.g., position a disk head)
 Data are in the form of a set of bits to be sent or
received
 Status signals indicate the state of the device
(Ready / Not Ready)
 Transducer converts data from electrical to other
forms of energy during output and from other forms
to electrical during input.
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I/O Module Function
 Control & Timing: to coordinate the flow of traffic
between internal resources and external devices
 CPU Communication: it involves
 Command decoding (read/write sector, seek track number, etc.)
 Data exchanged between the processor and the I/O module over
the data bus
 Status reporting (to know status of I/O module)
 Address recognition (each I/O device has address)
 Device Communication: involves commands, status
information, and data
 Data Buffering: needed due to differences in speeds
between peripherals, and memory and CPU
 Error Detection: e.g., mechanical and electrical
malfunctions reported by the device (e.g. paper jam and
bad disk track), and parity error during transmission
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I/O Steps
 The control of the transfer of data from an external
device to the processor passes through the following
steps:
 CPU interrogates the I/O module to check the status of the
attached device
 I/O module returns device status
 If device is ready, CPU requests data transfer by means of a
command to the I/O module
 I/O module gets data from device
 Data is transferred from the I/O module to CPU
 If the system employs a bus, then each of the
interactions between the processor and the I/O module
involves one or more bus arbitrations.
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I/O Module Diagram

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I/O Module Decisions
 Hide or reveal device properties to CPU
 Support multiple or single device
 Control device functions or leave for CPU
 Also O/S decisions
 e.g. Unix treats everything it can as a file

 An I/O module that takes on most of the detailed

processing burden, presenting a high-level interface to
the processor, is usually referred to as an I/O channel
or I/O processor
 An I/O module that is quite primitive and requires
detailed control is usually referred to as an I/O
controller or device controller
 I/O controllers are commonly seen on microcomputers
 I/O channels are used on mainframes

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Input Output Techniques
 Programmed I/O
 Data are exchanged between the processor and the I/O module
 The processor executes a program that gives it direct control of the I/O
operation, including sensing device status, sending a read or write
command, and transferring the data.
 When the processor issues a command to the I/O module, it must wait
until the I/O operation is complete
 If the processor is faster than the I/O module, this is wasteful of processor
time
 Interrupt driven I/O
 The processor issues an I/O command, continues to execute other
instructions, and is interrupted by the I/O module when the latter has
completed its work.

 Programmed I/O and interrupt driven I/O, CPU is responsible for

extracting data from main memory for output and storing data in
memory for input.

 Direct Memory Access (DMA)

 I/O module and main memory exchange data directly, without processor
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involvement
Three Techniques for Input of a Block of Data

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I/O Tecchniques
Programmed I/O
 CPU has direct control over I/O
 Sensing status
 Read/write commands
 Transferring data
 CPU waits for I/O module to complete operation
 Wastes CPU time

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Programmed I/O - detail
 CPU requests I/O operation from the appropriate
I/O module
 I/O module performs operation
 I/O module sets the appropriate bits in the I/O
status register
 I/O module does not take any further action to alert
the CPU directly
 I/O module does not interrupt CPU
 It is the responsibility of the CPU to check status
bits periodically, until it finds the operation is
complete.
 CPU may wait or come back later

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I/O Commands
 To execute an I/O-related instruction:
 CPU issues address
 Identifies module (& device if >1 per module)
 CPU issues command. Four types of I/O commands:
 Control – Used to activate a peripheral and tell it what to do.
Commands are tailored to the particular type of peripheral
device.
 e.g. spin up disk
 Test – Used to test various status conditions associated with an
I/O module and its peripherals
 e.g. if peripheral is powered on and available? Any errors
occurred?
 Read/Write
 Causes I/O module transfers data via buffer from/to peripheral
device 18
Addressing I/O Devices
 Under programmed I/O, there is a close
correspondance between the I/O-related
instructions that the processor fetches from
memory and the I/O commands that the
processor issues to an I/O module to execute the
instructions (CPU viewpoint)
 That is, the instructions are easily mapped into
I/O commands, and there is often a simple one-
to-one relationship.
 Each device is given a unique identifier (address)
 CPU commands contain identifier (address) of the
desired device
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I/O Mapping – (1)
 When the processor, main memory and I/O share a
common bus, two modes of addressing are possible:
memory mapped and isolated.
 Memory mapped I/O
 Devices and memory share a single address space
 CPU treats the status and data registers of I/O modules as
memory locations and uses the same machine instructions to
access both memory and I/O devices.
 For example, 10 address lines give a combined total of 1024
memory locations and I/O addresses.
 I/O read/write looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands available
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I/O Mapping – (2)
 Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O
 Limited set

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Memory Mapped and Isolated I/O
Assume 10 bit
address lines:
•Memory locations
0-511
•I/O addresses 512-
1023

I/O ports are accessed

only by special I/O
commands
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Interrupt Driven I/O
 Overcomes CPU waiting
 No repeated CPU checking of device
 CPU issues an I/O command to a module and
then go to do some other useful work
 I/O module interrupts CPU when ready to
exchange data with the processor
 CPU then executes the data transfer, as before,
and then resumes its former processing.

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Interrupt Driven I/O
Basic Operation (I/O module viewpoint)
 I/O module receives a READ command from the
CPU
 I/O module gets data from peripheral whilst CPU
does other work
 Once the data are in the module’s data register, I/O
module signals an interrupt to the CPU over a
control line
 Then, the module waits until its data are requested
by the CPU
 When request is done, I/O module places its data
on the data bus and is then ready for another I/O
operation.
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CPU Viewpoint
 CPU issues a READ command
 It then goes off and does something else (e.g., the CPU may be
working on several different programs at the same time)
 At the end of each instruction cycle, the CPU checks for interrupts
 When the interrupt from I/O module occurs:-
 CPU saves the context (e.g., program counter and processor registers)
of the current program
 Then, CPU processes the interrupt
 CPU fetches data word & stores it in memory
 Then, CPU restores the context of the program it was working on and
resumes execution.

 Interrupt I/O is more efficient than Programmed I/O, because it

eliminates needless waiting.
 However, interrupt I/O still consumes a lot of CPU time, because
every word of data that goes from memory to I/O module or from
I/O module to memory must pass through CPU

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Simple Interrupt
Processing
 Consider CPU
role in interrupt
driven I/O
 Interrupt
occurrence
triggers a number
of events, both in
the CPU’s
hardware and
software.
 When an I/O
device completes
an I/O operation,
the following
sequence of
events occur: PSW = Program Status
Word Register 26
Changes
in
Memory
and
Registers
for an
Interrupt

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Design Issues
 Two design issues arise in implementing
interrupt I/O:
 How do you identify the module issuing the
interrupt?
 How do you deal with occurrence of multiple
interrupts?
 i.e. an interrupt handler being interrupted

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Identifying Interrupting Module (1)
 Four general categories of techniques are in general
use:
 Multiple interrupt lines (Different line for each module)
between the CPU and the I/O module
 Limits number of devices
 Still more than one device can be connected to the module
 Software poll
 When a CPU detects an interrupt, it asks each module in turn,
to determine which module caused the interrupt
 Poll could be in the form of a separate command line TESTI/O.
The CPU raises TESTI/O and places the address of a particular
I/O module on the address line. The I/O module responds
positively, if it set the interrupt
 Alternatively, each I/O module could contain an addressable
status register that can be read by the CPU
 Slow
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Identifying Interrupting Module (2)
 Daisy Chain or Hardware poll (vectored interrupt)
 All I/O modules share a common interrupt request line.
 Interrupt acknowledge line is daisy chained through the modules
 When CPU senses an interrupt, it sends an interrupt Acknowledge down
the chain
 The signal propagates through a series of I/O modules until it gets to a
requesting module
 Requesting module responds by placing a word (vector) on data bus
 Vector is either the address of the I/O module or some other unique
identifier
 CPU uses vector to identify handler routine

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Identifying Interrupting Module (3)
 Bus Arbitration (vectored interrupt)
 I/O module must gain control of the bus before it can raise interrupt
 One module can gain control of the bus at a time
 When CPU detects interrupt, it responds on the interrupt acknowledge line
and requesting module places its vector on data lines

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Multiple Interrupts
 Multiple lines:
 Each interrupt line has a priority
 Higher priority lines can interrupt lower priority
lines
 Software polling:
 Order in which modules are polled
 Hardware polling:
 Order of modules on daisy chain
 Bus arbitration:
 Only current master can interrupt

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82C59A Interrupt Controller
 80386 has a single Interrupt Request (INTR) and a
single Interrupt Acknowledge (INTA) line
 To allow 80386 to handle a variety of devices and
priority structures, it is usually configured with an
external interrupt arbiter, the 82C59A interrupt
controller.
 External devices are connected to 82C59A, which in
turn connects to the 80386.
 82C59A has 8 interrupt lines (it can handle up to 8
module). If more than 8 modules are to be handled, a
cascade arrangement can be used to handle up to 64
modules.
 82C59A’s sole responsibility is the management of 33
interrupts
Sequence of Events
 82C59A accepts interrupt requests from
attached modules
 82C59A determines which interrupt has the
highest priority
 82C59A signals 80386 processor (by raising the
INTR line)
 CPU Acknowledges via INTA line
 82C59A puts correct vector information on data
bus
 CPU can then proceed to process the interrupt
and to communicate directly with the I/O module
to read or write data
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82C59A Interrupt
Controller
 82C59A is programmable.
 80386 CPU determines
priority scheme to be used
by setting a control word in
82C59A.
 Interrupt modes:
 Fully nested: interrupt
requests are ordered from
0 (IR0) through 7 (IR7)
 Rotating: Interrupting
devices are of equal
priority. When a device is
serviced, receives lower
priority in the group
 Special Mask: Allows CPU
to inhibit interrupts from
certain devices
Intel 8255A
Programmable Peripheral Interface
Intel 8255A
Programmable Peripheral Interface – (1)
 8255A is an example of an I/O module used for
programmed I/O and interrupt driven I/O
 8255A is a single-chip, general purpose I/O module
designed for use with 80386
 Right side of block diagram is the external interface of
the 8255A.
 24 I/O lines are programmable by the 80386 by means
of the control register
 80386 can set the value of the control register to specify
a variety of operating modes and configurations.
 24 lines divided into three 8-bit groups (A, B, C).
 Each group can function as an 8-bit I/O port
 Group C is subdivided into 4-bit groups (CA and CB),
may be used in conjunction with A and B I/O ports
Intel 8255A
Programmable Peripheral Interface – (2)
 Left side of the block diagram is the internal
interface to 80386 bus.
 It contains an 8-bit bidirectional data bus (D0 to
D7), to transfer data to and from I/O ports and to
transfer control information to the control
register
 Two address lines specify one of the three I/O
ports or the control register.
 Transfer takes place when Chip Select is
enabled with either the READ or WRITE lines
 RESET initializes the module
Intel 8255A
Programmable Peripheral Interface – (3)
 Control register is loaded by the CPU to control
mode of operation
 In Mode 0 operation, the three groups of eight
external lines function as three 8-bit I/O ports.
 Otherwise, groups A and B function as I/O ports,
and lines of group C serve as control lines for A
and B
 Control signals serve two principal purposes:
“handshaking” and “interrupt request”.
 Handshaking is a simple timing mechanism
Keyboard/Display Interfaces to
82C55A
 Keyboard provides 8 bits
of input, with two bits
having special meaning
(transparent to the
82C55A), and two
handshaking signals
 Display is linked through
an 8-bit data port, with two
bits having special
meaning. Two
handshaking lines and
two lines provide
additional control
functions
Direct Memory Access
 Interrupt driven I/O, though more efficient than simple
programmed I/O, still requires active CPU intervention
to transfer data between memory and an I/O module,
and any data transfer must traverse a path through the
processor.
 Both I/O techniques suffer from:
 Transfer rate is limited by the speed with which the processor
can test and service a device
 CPU is tied up in managing an I/O transfer; a number of
instructions must be executed for each I/O transfer
 When large volumes of data are to be moved, DMA is
the answer
DMA Function
 DMA involves an additional Module (hardware)
on the system bus
 DMA module mimics the processor and takes
over control of I/O from CPU
 DMA module must use the bus only when the
CPU does not need it, or it must force the CPU
to suspend operation temporarily (cycle
stealing).
Typical DMA Module Diagram
DMA Operation
 When the CPU wishes to read or write a block of data, it issues a
command to the DMA module, by sending the DMA module the
following information:-
 Read/Write is requested, using read/write control line between the CPU
and DMA
 I/O device address, communicated on data lines
 Starting address of memory block for data to read from or write to,
communicated on data lines and stored by DMA controller in its
address register
 Number of words to be read or written, communicated via data lines
and stored in the data count register
 CPU carries on with other work
 DMA module deals with transfer of the entire block of data, one
word at a time, directly to or from memory, without going through
CPU
 When transfer is complete, DMA module sends an interrupt signal
to CPU
 CPU is involved only at the beginning and at the end of the transfer
DMA Transfer
Cycle Stealing
 DMA controller takes over bus for a cycle
 Transfer of one word of data
 Not an interrupt
 CPU does not switch context

 CPU suspended just before it needs to use the

bus
 i.e. before an operand fetch, a data fetch or a
data write
 Slows down CPU but not as much as CPU
doing transfer
DMA and Interrupt Breakpoints
During an Instruction Cycle
DMA Configurations (1)

Single Bus, Detached DMA module

 Each transfer uses bus twice
 I/O to DMA then DMA to memory
 CPU is suspended twice
DMA Configurations (2)

Single Bus, Integrated DMA module

 DMA logic may actually be a part of an I/O module, or it
may be a separate DMA module that controls one or
more I/O modules
 Each transfer uses bus once
 DMA to memory
 CPU is suspended once
DMA Configurations (3)

Separate I/O Bus

 Bus supports all DMA enabled devices
 Each transfer uses bus once
 DMA to memory
 CPU is suspended once
8237 DMA Usage of System Bus
Fly-By DMA Controller
 While DMA using buses, processor is idle
 Processor using bus, DMA idle
 Known as fly-by DMA controller
 Data does not pass through and is not stored in
DMA chip
 DMA only between I/O port and memory
 Not between two I/O ports or two memory locations
 Can do memory to memory via register
 8237 contains four DMA channels
 Programmed independently
 Any one active
 Numbered 0, 1, 2, and 3
51
 Table 7.2

Intel
8237A
Registers

E/D = enable/disable
TC = terminal count 52
 Evolution of the I/O Function
1. The CPU directly controls a
peripheral device.
2. A controller or I/O module is
added. The CPU uses
programmed I/O without
interrupts.
3. Same configuration as in
step 2 is used, but now
interrupts are employed.
The CPU need not spend
time waiting for an I/O
operation to be performed,
thus increasing efficiency.
4. The I/O module is given direct
access to memory via DMA. It
can now move a block of data to
or from memory without involving
the CPU, except at the beginning
and end of the transfer.
5. The I/O module is enhanced to
become a processor in its own
right, with a specialized
instruction set tailored for I/O
6. The I/O module has a local
memory of its own and is, in fact,
a computer in its own right. With
this architecture a large set of I/O
devices can be controlled with
minimal CPU involvement.
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I/O Channel
Architecture

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Universal Serial Bus (USB)
 Widely used for peripheral connections
 Is the default interface for slower speed devices
 Commonly used high-speed I/O
 Has gone through multiple generations
 USB 1.0
 Defined a Low Speed data rate of 1.5 Mbps and a Full Speed rate of 12 Mbps
 USB 2.0
 Provides a data rate of 480 Mbps
 USB 3.0
 Higher speed bus called SuperSpeed in parallel with the USB 2.0 bus
 Signaling speed of SuperSpeed is 5 Gbps, but due to signaling overhead the
usable data rate is up to 4 Gbps
 USB 3.1
 Includes a faster transfer mode called SuperSpeed+
 This transfer mode achieves a signaling rate of 10 Gbps and a theoretical
usable data rate of 9.7 Gbps
 Is controlled by a root host controller which attaches to devices to
create a local network with a hierarchical tree topology

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FireWire Serial Bus
 Was developed as an alternative to small computer system
interface (SCSI) to be used on smaller systems, such as
personal computers, workstations, and servers
 Objective was to meet the increasing demands for high I/O
rates while avoiding the bulky and expensive I/O channel
technologies developed for mainframe and supercomputer
systems
 IEEE standard 1394, for a High Performance Serial Bus
 Uses a daisy chain configuration, with up to 63 devices
connected off a single port
 1022 FireWire buses can be interconnected using bridges
 Provides for hot plugging which makes it possible to connect
and disconnect peripherals without having to power the
computer system down or reconfigure the system
 Provides for automatic configuration
 No terminations and the system automatically performs a
configuration function to assign addresses
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SCSI
 Small Computer System Interface
 A once common standard for connecting peripheral
devices to small and medium-sized computers
 Has lost popularity to USB and FireWire in smaller
systems
 High-speed versions remain popular for mass memory
support on enterprise systems
 Physical organization is a shared bus, which can support
up to 16 or 32 devices, depending on the generation
of the standard
 The bus provides for parallel transmission rather than
serial, with a bus width of 16 bits on earlier
generations and 32 bits on later generations
 Speeds range from 5 Mbps on the original SCSI-1
specification to 160 Mbps on SCSI-3 U3

57
 Thunderbolt
 Most recent and fastest
peripheral connection
technology to become available
for general-purpose use
 Developed by Intel with
collaboration from Apple
 The technology combines data,  Provides up to 10 Gbps
video, audio, and power into a throughput in each direction
single high-speed connection and up to 10 Watts of power to
for peripherals such as hard connected peripherals
drives, RAID arrays, video-
capture boxes, and network
interfaces

58
InfiniBand
 I/O specification aimed at the high-end server market
 First version was released in early 2001
 Heavily relied on by IBM zEnterprise series of
mainframes
 Standard describes an architecture and specifications
for data flow among processors and intelligent I/O
devices
 Has become a popular interface for storage area
networking and other large storage configurations
 Enables servers, remote storage, and other network
devices to be attached in a central fabric of switches
and links
 The switch-based architecture can connect up to
64,000 servers, storage systems, and networking
devices
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PCI Express SATA
 Serial Advanced
 High-speed bus Technology Attachment
system for  An interface for disk
storage systems
connecting  Provides data rates of
peripherals of a up to 6 Gbps, with a
maximum per device of
wide variety of 300 Mbps
types and speeds  Widely used in desktop
computers and in
industrial and
embedded applications

60
Ethernet
 Predominant wired
networking technology
 Has evolved to support  Has moved from bus-based
data rates up to 100 Gbps to switch-based
and distances from a few
meters to tens of km  Data rate has periodically
increased by an order of
 Has become essential for magnitude
supporting personal  There is a central switch
computers, workstations, with all of the devices
servers, and massive data connected directly to the
storage devices in switch
organizations large and
small  Ethernet systems are currently
available at speeds up to 100
 Began as an experimental Gbps
bus-based 3-Mbps system

61
  As the technology of
Wi-Fi antennas, wireless
transmission techniques,
 Is the predominant wireless and wireless protocol
Internet access technology design has evolved, the
 Now connects computers, IEEE 802.11 committee
tablets, smart phones, and has been able to
other electronic devices introduce standards for
such as video cameras TVs new versions of Wi-Fi at
and thermostats higher speeds
 In the enterprise has
 Current version is 802.11ac
become an essential (2014) with a maximum data
means of enhancing worker rate of 3.2 Gbps
productivity and network
effectiveness
 Public hotspots have
expanded dramatically to
provide free Internet access
in most public places

62