A hata Conte CELEBRATING 14 YEARS OF EXCELLENCE IN VSI TRAINING: Advanced Physical Design & Verification Course [PDPT] (Titolo eaie ML) 1K+ Lele) os on eens} Dec fee ee nyMAVEN-SILIGON.COM MAVEN SILICON rsticonis ateading provider ot VS training for students and professionals, We offer a range of high-quality VLSI training programs and internships, taught by experianced Industry professionals, aimed at helping enginaers to upskill and advance their careers In the fast-growing Semiconductor industry. From digital design and verification to physical design ‘and design for testing, Maven Silicon covers a wide variety of topics along with abs and projects through Industry standard EDA tools. Our state-of-the-art training facilities, coupled with innovative training methods, provide students with hands-on experience and « stfong foundation in the fotest VLSI technologies. Our curriculum is designed to meet the demands of the industry and Is constantly updated to keep pace with the latest advan: ‘ments. In addition, Maven Silicon offers flexible schadullng options and customized traning programs to eccommadata student's busy schedules. ‘With a commitment to excellence and a passion for empowering students and professioncls, Maven Silicon is dedicated to providing the highest quality hands-on training to help ‘engineers reach ther full potential in the Semiconductor industry. My vision is to create an excellent learning ecosys supetior technical expertise, nands-on 1 ‘nd industry-oriented courses with innovative learning For more than 14 yeare, Maven Silicon has been a benchmark for the VLSI training ecosystem in Inia, offering high-quality VLSI troining courses for VLSI aspirants, professionals, ond organizations across the globe. Sivakumar P R Founder and CEO ‘Our CEO, Sivakumar PR, has 26+ years of experience in the engineering and semiconductor industries. He hos worked as o Verification Consultant in the top EDA companis ‘various ASIC and FPGA desion houses and helped them to use the EDA solutions e gate designs adence, ond Mi ke Symopsys, itor Graphics. During this tenure, he worked very closely with rtt-mition Ively for the successful tpe-out ‘To know more about our CEO, visit https://www linkedin com/in/sivaprMAVEN. Three reasons to muse with @ Dynamic VLSI courses designed and delivered by Industry experts Maven Silicon is the Best VLSI training center which provides high-class industry standard VLSI traning, The courses have been iy designed by industry experts, based on the job opportunities and career growth in ctor industry and we keep Updating our VLSI Curriculum as per the latest industry trends. a Superior Training Methodology and Infrastructure ‘Our training methodology is unique. t helps our students to laarn even complex technologies in a short span of time and make 1urse time Is dadicated to the labs, mini projects, and the fnal project. Ou tralning course instr, ther parts. 70% of tha hell you to acquire th ® Hands on Learning This program offers hands ‘9s physical synthesis, floor-plonning, placement, clo help of industry-standard EDA tools which makes, the chica sls w ich are highly requirad to got ajob In the semicondt 3 stops (from RTL to GDS-I) in back-and flow ‘experience on various implementation and sign ‘tree synthesis, routing, static timing analysis, LVS and DR‘ rainees industry ready. withthe EDA Partner SIE Se ee an cen Seay o ane Geet ee ee Rene Poe ri conquer design challenges in the seemingly daunting chip. de: erie eee world of boord and chip de eaeCOURSE CURRICULUM Advanced Physical Design & Verification Course 14 Modules MAVEN-SILICON.COM 08 Linx | EDA Tools - Synopays Siemens + VLSIDesign Flow + ASIC VS FPGA « Introduction to ASIC Verification Methodologi + Introduction to VLSI + VLSiDesion Flow Steps - Demo + Components of the UND system * Ditectory Structure + Utities and Commands + ViEditor ca + Introduction to DFT «Types of Testing + Bosic Testing Principles + Fault Collapsing + DFT Techniques - Ad-hoc Techniques + Structured Techniques * BIST @Boundary Soan + Introduction to Slernens EDA's ‘Tessent Shell + Labs: Tessent Labs — + Introduction - Overview + Desoription of Physical Design Processes, * Partitioning + Floorplan & Powerplan + Plocement « Static Timing Analysis (Signal Integrity ‘and Cross Tak Issues) + Clock Tree Synthasis + Routing + Physical Verification & Design Signott + Teloverview ‘= What Is FLOOR PLANNING? + Telve Pert « Several criteria are used to measure + Evaluating TOL scripts under Unix ‘the quaity of Floorplans * Telsyrtox «+ Inputs requires += Dotatyoos + Howto qualfy forlmport Design? = Operators What Is required to come up with a * Branching & looping construct {9001 floor plan? = Subroutines + Howto do floor planning for placing + File operations Moore? + Rogular expressions + Special variables + Built-in functions « Introduction to Tk graphics * Floorplon Steps «+ How to qualfy for Floorplan? + Power pionning « Analyze GOR, Timing, congestion trea, and power. * tHiararctica! floor planning and design partitioning ~ labs + {fo planning and RDL routing. « Introduction to STA = Comparison with OTA ‘© Timing Path and Constraints * Different types of clocks * Clock demoin ang Variations * Clock Distribution Networks * How to fx timing falure + Timing Closure + Timing ECO's for each type of Violation ‘+ Whats hierarchical timing closure ~ time budgeting and clocking. nt criteria driving the placement process « Different tasks in placement Goals of placement Sanity checks before placement Placement algorithons placement Optimization techniques Placement qualification Analyze GOR, Timing, congestion, oreo, ond power, ign Synthesis & PDKe * Introduction to Synthesis * Physical Synthesis + Standord input and output files for o Synthesis tool How te Write SDC? + How to analyse the synthesis report? + Lec + PF PDK (to Jeff ptfte.nam ao Mikyway, tp fies ) Too! related Technology HesMAVEN-SILICON.COM COURSE CURRICULUM Advanced Physical Design & Verification Course 14 Modules 8 = Linux | EDA Tools - Synopsys,siemens Ee E : ee EDA Tools ue Me += Synopsys (Design Compiler) ~ for Synthesis 1 Seno eemannson earns « Design ue Check (ORC) 1 Sone (Omer) er PRR Row oes Preperotona Liuedeade “Sperone: 9 25 fo Dre esran an Sos TO ah {Soy retina) fr Tg ora SruNeGs(FENS)S Gokieesmimag, 2 <2 wmma smiemato(ie) + SemengEDA (Clie) fr Psa sauce oeacantie * Comment faced LS sues Optimization + IRDrop Analysis + Whetisteaference between ® Boot Maton clock buffer and normal buffer? + CTSGoale + Clock Tree Design Rule Constraints + Clock Tee Exceptions + NDRS (rea, and power + Methods to fix EM » RISC-V IP ~ Physical Design + Sanity checks + Routing flow (Global routing, Track ossign= ‘ment, Detolled Routing, Search and repair) + Goalsof Routing + Routing Constraints + Post Routing Optimization + Analyze GOR, Timing, congestion, area, cond power. ene « Signal integrity + Concerns addressed by signal intagrty + Factors affecting signalintegrity + Cross Talk Noise + Gross Talk Delay + Antenna affectsfh Antares! Centre of Excellence in VLSI Sere eM aaa leet igi) Bannerghatta Main Rd, Bengaluru, ere eer} Rae eae Association & Partnerships synopsys SIEMENS “RIsc @iESA ALDEC )