DECADE OF

EXCELLENCE
IN
VLSI TRAINING

HANDS-ON LEARNING WITH INDUSTRY STANDARD EDA TOOLS

ADVANCED ASIC VERIFICATION COURSE

PART TIME
MAVEN SILICON
Evolved in VLSI Technologies, Maven Silicon is a VLSI Training company that offers a wide range of corporate and professional training services. Maven Silicon is
the world-class VLSI training company that offers SystemVerilog and UVM based advanced verification courses and holds the credit of training 500+ engineers
per year. With shrinking process technologies, ever-growing design sizes, and increasing integration of IP to a single chip, verification has become an extremely
complex and critical part of any SoC design today. As chip verification consumes 60% of the design cycle, most of the VLSI companies hire fresh VLSI engineers
who have extensively been trained on ASIC verification methodologies and technologies and have dedicated themselves only to chip verification.

Usually, 70% of the engineers in any product or services company dedicated only to functional verification, and the remaining 30% of the engineers work on
RTL design, STA and Analog, etc. So there are plenty of job opportunities for fresh VLSI engineers who are highly skilled in ASIC verification. We at Maven Silicon
have designed the courses keeping this fact in our mind. You can leverage our expertise and be a part of a world-class training infrastructure to learn the VLSI
technologies and then get a job in the best semiconductor companies.

Our CEO, Sivakumar P R, has 22+ years of experience in the engineering and semiconductor industries. He has worked as a Verification Consultant in the top
EDA companies like Synopsys, Cadence, and Mentor Graphics. During this tenure, he worked very closely with various ASIC and FPGA design houses and helped
them to use the EDA solutions effectively for the successful tape-outs of multi-million gate designs.

To know more about our CEO, visit https://www.linkedin.com/in/sivapr/

REASONS TO MUSE ON MAVEN SILICON INCLUDES,

1. SystemVerilog and UVM based Advanced Verification
Maven Silicon, as the training centre, edifies engineers on the advanced ASIC Verification methodologies and SystemVerilog. In addition to these advanced
technologies, we also impart the basic VLSI technologies like Advanced Digital Design Methodology, Verilog, ASIC & FPGA's design flow, STA & CMOS
fundamentals.

2. Course Delivered by Industry Experts

As the courses are composed of advanced VLSI design and verification technologies, only experienced VLSI engineers can deliver and give an enriched learning
experience. At Maven Silicon, industry experts share their experience and guide you on enhancing your skills in VLSI Industries.

3. Superior Training Methodology

At Maven Silicon, the experienced engineers who work in the top semiconductor industries share their experiences with you and simulate their expertise to help
you learn via real-time scenarios. Only 30% of 720 hours of VLSI-VM course is dedicated to imparting concepts, and the remaining 70% for labs, mini-projects,
and final projects.

4. Excellent work environment

We provide an excellent work environment, which has adequate hardware and software infrastructure. Maven Silicon has chosen Mentor Graphics as its EDA
partner and provides great opportunities to engineers to work on verification platforms like Questa and explore the advanced ASIC verification technologies and
methodologies.

Maven Silicon has set the benchmark for VLSI Training by offering the best-curated package comprised of a holistic curriculum, standard
training methodologies, modern infrastructure, and excellent customer service.

EDA PARTNER - MENTOR GRAPHICS

Mentor Graphics is a leader in Electronic Design Automation. Its innovative products and solutions help engineers conquer design challenges in the seemingly
daunting world of board and chip design.
To know more about Mentor Graphics, please visit https://eda.sw.siemens.com/en-US
 ADVANCED ASIC VERIFICATION COURSE

MODULE 1 MODULE 8
MODULE 6
Introduction to Linux
SystemVerilog HVL UVM - Universal Verification Methodology

Components of UNIX system [1] Introduction to SystemVerilog Introduction to UVM Methodology

Directory Structure New Data types Overview of Project
Utilities and Commands Tasks and Functions UVM TB Architecture
Vi Editor Interfaces Stimulus Modeling
Clocking blocks Creating UVCs and Environment
UVM Simulation Phases
[2] Object-Oriented Programming and
Testcase Classes
Randomization
TLM Overview
OOP Basics
Configuring TB Environment
MODULE 2 Classes - Objects and handles
Polymorphism and Inheritance
Advanced Verilog for Verification UVM Sequences
Randomization
UVM Sequencers
Constraints
Tasks and Functions Connecting DUT- Virtual Interface
Delays - Regular, Intra Assignment and Virtual Sequences and Sequencers
[3] Threads and Virtual Interfaces
Inertial Delays Creating TB Infrastructure
Fork Join
Race Conditions Connecting multiple UVCs
Fork Join_any
File I/O operation Building a Scoreboard
Fork Join_none
TB Constructs Introduction to Register Modeling
Event controls
Self checking Testbenches Building reusable environments
Mailboxes and semaphores
Virtual Interfaces
Transactors
Building verification environment
Testcases
MODULE 9
MODULE 3 Verification Mini Project:
[4] Callbacks
Code Coverage Verification and RTL sign-off
Facade Class
Statement coverage Building Reusable Transactors Project specification analysis
Branch Coverage Inserting Callbacks Defining verification plan
Expression Coverage Registering Callbacks Creating Testbench architecture
Path Coverage Defining Transaction
Toggle Coverage [5] Direct Programming Interface Implementing the transactors - Generator,
FSM - State, Transition and Sequence Driver, Receiver and Scoreboard
coverage [6] Functional Coverage Implementing the coverage model
Coverage models Building the top level verification environment
Coverpoints and bins Building regression test suite
Cross coverage Coverage Analysis and Coverage Closure
Regression testing
MODULE 4
MODULE 10
ASIC Verification Methodologies
Assertion Based Verification - SVA
Directed Vs Random
MODULE 7 Introduction to ABV
Functional verification process
Stimulus Generation Advanced SystemVerilog Immediate Assertions
Bus function model Environment Configuration Simple Assertions
Monitors and reference models Reference Models and Predictor Logics Sequences
Coverage Driven Verification Using Legacy BFMs Sequence Composition
Verification Planning and management Scenario Generation Advanced SVA Features
Testcases - Random, Directed and corner case Assertion Coverage
Coding styles for VIP

MODULE 11
MODULE 5 Verification Planning and Management
Design Automation using Scripts - Perl Verification Plan
Introduction to Perl TB Architecture
Functions and Statements Coverage Model
Numbers, Strings, and Quotes Tracking the simulation process
Comments and Loops Building regression testsuite
Testsuite optimization
 ADVANCED ASIC VERIFICATION COURSE

MODULE 12 MODULE 13
Industry Standard Project
RISC V Processor
Project specification analysis
[1] RISC-V Instruction Set Architecture Defining verification plan
RISC-V processor overview Creating Testbench architecture
RISC-V ISA Overview Defining Transaction
RV32I – R and I Type Instruction Implementing the transactors - Generator,
RV32I – S and B Type Instructions Driver, Receiver, and Scoreboard
RV32I – J and U Type Instructions Implementing the coverage model
RV32I – Assembly Programs Building the top-level verification environment
Defining weighted random, corner case and
[2] RISC-V RV32I RTL Architecture Design directed
RISC-V Execution Stages and Flow Building the functional and code coverage
RISC-V Register File and RV32I Instructions reports
Format
RV32I – R and I Type ALU Datapath
RV32I – S Type ALU Datapath - Load and Store
RV32I – B and U Type ALU Datapath
RV32I – J Type ALU Datapath – JAL EDA TOOLS
and JALR
Mentor Graphics
Xilinx
[3] RISC-V RV32I 5 Stage Pipelined RTL Design Aldec
CPU Performance and RISC-V 5 Stage Pipeline
Overview
RISC-V 5 Stage Pipeline – Data Hazards and
Design Approach
RISC-V 5 Stage Pipeline – Control Hazards and OPERATING SYSTEM
Design Approach
Linux - Ubuntu

OTHER SUPPORT

Delivered by Industry Certification on

Live Q&A sessions
Experts completion

WhatsApp Support Group 24/7 Lab Access

REACH US ASSOCIATION & PARTNERSHIPS

# 21/1A, III Floor, Marudhar Avenue,
Gottigere, Uttarahalli Hobli, South Taluk, DESIGN PARTNER TECHNOLOGY PARTNER
Bannerghatta Road, Bangalore - 560076

+91 - 95133 98555 / +91 - 97415 19977

admission@maven-silicon.com / TRAINING PARTNER

vlsivm@maven-silicon.com * Logos are the trademarks of the respective companies.

Copyright 2021 Maven Silicon, All Rights Reserved.