Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank

pages. Revealing of identification, appeal to evaluator will be treated as malpractico.

.
 OR

a) Explain the organization of IK x1 memory chip

b) A cache is organized in the direct-mapped manner with the following
parameters:
Main memory size of 64K words.
Blocks of 16 words each.
Cache consisting of 2K words.
i. How many bits are there in a main memory address?
ii. How many bits are there in each of the TAG, BLOCK and WORD
fields?
c) Illustrate with neat diagram Set- Associative mapping technique. 05

UNIT IV
a) Explain the design of 4-bit carry look ahead adder. 10

b) Multiply (+22)(Multiplicand) x Multiplier(-6) using Booth's 05

Algorithm Method

c)Multiply 110101 (Multiplicand) x 011041'(Muliplier) using l 05

Recoding Method

1t,OR
6 a) Explain the EEE Floating PointEprmat Represent (0.0625)10 in 10
IEEE Floating point Formats.

circuit binary multiplier along with the 10

b) Multiply 14 x 12 using seguential
hardware configuration diagram.

UNIT - V

Using a'Singlèi Büs Architecure, Write & Explain the sequence of control steps 10
7 a)
required for,ADD THE (IMMEDIATE) NUMBER NUM TO REGISTER R

of a Hardwired Control Unit 10

Explain'with block diagram the basic organization
w
******
 SEE EXAM
BMS COLLEGE OF ENGINEERING, BANGALORE -19
(Autonomous Insttute, Afilated to VTU)

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