ICC2017: WT07-Workshop on Full-Duplex Communications for Future Wireless Networks

Compensation of ADC-induced Distortion

in Broadband Full-Duplex Transceivers
Christian A. Schmidt, Gustavo González, Fernando Gregorio, and Juan E. Cousseau
Instituto de Investigaciones en Ingenierı́a Eléctrica - CONICET
Universidad Nacional del Sur
Avda. Alem 1253, 8000 Bahı́a Blanca, Argentina
Emails: [cschmidt,ggonzalez,fernando.gregorio,jcousseau]@uns.edu.ar

Taneli Riihonen and Risto Wichman

Department of Signal Processing and Acoustics
Aalto University School of Electrical Engineering
P.O. Box 15400, FI-00076 Aalto, Finland

Abstract—The performance of full-duplex transceivers is
highly dependent on their ability to remove the self-interference
(SI) that is generated by the simultaneous transmission and
reception in the same frequency band. Even after passive isolation
and RF cancellation, the magnitude of the residual SI is usually
considerably higher than the signal of interest. The resolution
of the analog-to-digital converter (ADC) must be rather high
to accommodate both the residual SI and the intended signal
to allow the digital SI cancellation. Adding to this technical
challenge, 5G systems will occupy large signal bandwidths of
hundreds of MHz. Thereby, high-speed and high resolution
ADCs are required. In order to obtain a reasonable compromise
between performance and massive production cost, a time-
interleaved ADC (TI ADC) structure is often used. In this paper,
we analyze the TI-ADC induced nonlinear distortion on the
performance of a full-duplex transceiver. In particular, time-
mismatch errors are considered, and in addition, we apply a
digital post-processing to mitigate ADC imperfections. Simulation
results show that even a slight mismatch in the TI ADC array
can severely deteriorate the performance of the whole system.
On the other hand, we show that included ADC compensation
can restore adequate performance.
I. I NTRODUCTION
Full-duplex (FD) transceivers have become an appealing
research topic due to their theoretical capability of doubling
the communication throughput between two devices. This
is due to their operation mode in which transmission and
reception take place simultaneously in time and sharing the
same frequency band [1], [2]. However, this mode of operation
introduces self-interference (SI) when the transmitted signal
leaks into the receiving signal path, which has to be canceled
in order to be able to detect the received signal of interest. The
SI signal power is usually more than 100 dB higher than the
received signal, which makes this approach challenging. In [1],
it is shown that successful SI cancellation can be accomplished
by combining antenna isolation techniques, active analog
cancellation, and digital post-correction.
Digital post-processing for SI cancellation presents a set
of challenges to be solved. In particular, non-ideal behavior
in the analog front-end components, such as power amplifier
(PA) nonlinearity, I/Q imbalance and ADC induced distortion,
affects the residual SI signal and makes its cancellation dif-
ficult to achieve. After the down-conversion, the automatic
gain control (AGC) scales the received signal to fit into
the dynamic range of the ADC. At this point, even after
antenna and RF cancellation, the SI is tens of decibels above
the signal of interest. Therefore, high resolution ADCs are
required in order to avoid the signal of interest be buried in the
quantization noise [3]. ADC resolution effects and transmitter
PA nonlinearities are also addressed in [4] assuming the ADC
as a memoryless nonlinearity using a classical approach [5].
Large bandwidth channels from hundreds of MHz to one
GHz will be used in 5G networks to satisfy the demand of
high data rates [6]. Then, high-speed ADCs are required to
handle those broadband signals. On the other hand, it is well
known that there is a compromise between the sampling rate
(signal bandwidth) and dynamic range for practical ADCs
[7]. Therefore, FD operation in broadband channels is even
more challenging, since high dynamic range and high sampling
frequency are required.
High resolution ADCs such as successive approximation
register (SAR) ADCs are slow (the higher the resolution, the
more clock cycles needed for the digital output word to be
available) [8]. On the other hand, a TI ADC structure offers
two possible solutions: moderate resolution at high sampling
rate, or high resolution at a moderate sampling rate. In our
case, where high effective resolution is required, a TI ADC
structure allows the use of these “slower-but-more-accurate”
ADCs while keeping a moderate sampling rate adequate for
the application. As digital dynamic range is proportional to
the effective resolution, in this sense a TI ADC facilitates a
sufficiently high dynamic range i.e., an effective number of
bits (ENOB) of 12 or above, that otherwise would be diffi-
cult to reach even through post-compensation on commercial
ADCs [9]. As high-speed and high-resolution ADCs are a key
component in broadband communications systems employing
FD transceivers, TI-ADCs are a natural choice for analog to
digital conversion.

978-1-5090-1525-2/17/$31.00 ©2017 IEEE

 ICC2017: WT07-Workshop on Full-Duplex Communications for Future Wireless Networks

A TI ADC is an array of several ADCs working in parallel where PG and PO model the gain and offset mismatches re-
and interleaved in time by uniformly shifting their clocks, spectively, radI (n) is the ideally sampled signal, and ∆rad (n)
such that the overall conversion rate is proportionally increased represents the shift in the sampling instant defined in the next
[10]. However, several mismatches between the ADCs (due to section. The digital cancellation output is
the manufacturing process) introduce nonlinear distortion that
needs to be compensated for [11]. rdc (n) = rad (n) − x(n) ∗ ĥsi (n) (5)
The higher the ADC resolution, the higher the digital where ĥsi (n) ≈ Kpa Klna Aan Arf hsi (n) is an estimation of
dynamic range available for post-processing, which is par- the residual channel. If the PA and the ADC do not introduce
ticularly important for FD communications. However, the significant distortion, upa (n) ≈ Kpa x(n) and rad (n) ≈
usable dynamic range after AD conversion can be severely Klna z(n) ∗ hsr (n) + Klna Aan Arf upa (n) ∗ hsi (n) + w(n).
reduced due to distortion, measured both in terms of ENOB Then, it is easy to show that
and spurious-free dynamic range (SFDR). To the best of our
knowledge, the incidence of the real ADC induced distortion in rdc (n) ≈ Klna z(n) ∗ hsr (n)
the performance of a FD system has not yet been considered. +Kpa Klna Aan Arf x(n) ∗ hsi (n)
In this work, we present an analysis of the incidence −x(n) ∗ ĥsi (n) + w(n)
of TI-ADC induced distortion in the performance of a FD
transceiver. To reduce the harmful effects of the mismatches, ≈ z(n) ∗ hsr (n) + w(n) (6)
we introduce a gain and offset mismatch compensation and Then, after channel equalization, it is possible to recover
analyze the effect of timing mismatch before and after digital the signal of interest. In the next section, we introduce the TI
correction. Simulation results confirm the good performance ADC nonlinear model and a compensation of its effects.
of the compensation technique in a FD scenario.
III. TI-ADC IMPERFECTIONS AND ITS COMPENSATION
II. F ULL - DUPLEX TRANSCEIVER MODEL
The TI ADC architecture is composed of M ADCs inter-
A block diagram of the FD direct-conversion transceiver leaved in time such that the overall conversion rate of the
is shown in Fig. 1. Transmitted and received signals are system is increased proportionally to the number of ADCs
modulated with orthogonal frequency-division multiplexing used. Each ADC samples the input signal with a sampling
(OFDM), for which we assume perfect time and frequency period T and a relative phase shift (m − 1)T /M , and their
synchronization and that the cyclic prefix (CP) is longer than outputs are then multiplexed.
channel impulse responses. The SI channel hsi (n) is modeled
as Rician and the source-receiver channel hsr (n) is a Rayleigh A. Mismatch errors in a TI ADC
frequency-selective fading channel. To simplify the notation, Unfortunately, due to fabrication process inaccuracies, any
non-ideal effects are modeled in base band. TI ADC architecture presents gain, offset, and timing mis-
The OFDM signal x(n) after the power amplifier (PA) is match errors between the different ADC channels, which lead
given by to a non ideal behavior.
upa (n) = Kpa fpa {x(n)} (1) Let us now consider the output of the mth ADC with only
offset and gain mismatch.
where Kpa is the PA amplification factor and fpa {·} is the PA
nonlinear response, e.g. soft-limiter (SL) or solid-state power radm [k] = Gm radIm [k] + Om = Gm r(kT + τIm ) + Om (7)
amplifier (SSPA) models [12].
where Gm and Om are the gain and offset of the mth ADC,
The received signal r(n) after antenna and RF cancellation
respectively, and τIm is the ideal clock shift from the mth
can be written as
ADC.
r(n) = Klna z(n) ∗ hsr (n) It is clear that Gm and Om terms affect the multiplexed
output rad [n] every M th sample. Hence, by defining the
+Klna Aan Arf upa (n) ∗ hsi (n) + w(n)
discrete sequences
(2)
∞
X
where z(n) is the signal of interest, w(n) is additive Gaussian PG [n] = G[n − kM ] (8)
noise, and Klna , Aan and Arf are respectively the low noise k=−∞
amplifier (LNA) gain, and the antenna and RF attenuation. and ∞
After the digital conversion, the signal becomes X
PO [n] = O[n − kM ] (9)
rad (n) = fad {r(n)}, (3) k=−∞

where fad {·} is the nonlinear model of the TI-ADC described where G[n] = [G0 , G1 , · · · , GM−1 ] and O[n] =
by: [O0 , O1 , · · · , OM−1 ], respectively (both defined for 0 < n <
M − 1). Thus, we can model the non ideal output rad [n]
rad (n) = (radI (n) + ∆rad (n)) PG (n) + PO (n) (4) (affected by offset and gain mismatches) as a function of
 ICC2017: WT07-Workshop on Full-Duplex Communications for Future Wireless Networks

x(n) upa (n)

TX stream DAC PA htd (n) Destination

hsi (n)
Dig. Canc. LO RF Canc.

w(n)
- -
Compensator TI-ADC
RX stream LNA hsr (n) Source

z(n)
rdc (n) rac (n) ADC r(n)

Fig. 1. FD transceiver model.

mismatch errors on the ideally sampled signal radI [n] as in

the following expression
rad [n] = radI [n]PG [n] + PO [n]
Now let us consider the mth ADC channel with all kinds of
mismatch errors. According to the notation used so far, the
output of such ADC should be rewritten as
radm [k] = Gm r(kT + τm ) + Om
where now a timing mismatch is allowed between each ADC,
and therefore
m−1
τm = τIm + ∆tm = T + ∆tm (12)
M
A ∆t shift in the sampling instant will result in an amplitude
error ∆A. Therefore, we can model the effect of timing
mismatch as an additive distortion to the ideal sample radIm [k],
i.e.
radm [k] = Gm (radIm [k] + ∆radm [k]) + Om (13)
The output signal from the TI ADC with all mismatch errors
is then
rad [n] = (radI [n] + ∆rad [n]) PG [n] + PO [n]
This manner to model the timing mismatch distortion as an
(unknown) additive error renders the sequential estimation and
correction of all mismatch errors possible and efficient, as
shown in [11].
B. TI ADC compensation
Compensation of the gain and offset mismatch errors in
TI ADCs can be easily accomplished by first subtracting the
estimated offset from the output samples of each ADC, and
then multiplying by the inverse of the estimated gain error (see
Fig. 2).
As the timing shifts have previously been estimated and the
overall ideal sampling frequency is known, we have available
the following data,
• The actual instants where samples are being taken in each
ADC (tm [k] = kT + ∆tm ).
• The value of the samples taken at the actual time instants
after correcting for offset and gain error r̂adm [k].
(10)
(11)
Fig. 2. Gain and offset compensation scheme. r̂ad [k] is the time interleaved
sequence with timing mismatch.
The ideal sampling instants with no timing mismatches
•
t[n] = nT /M .
Therefore, we can estimate the ideal samples that would have
been taken at the ideal time instants through interpolation
between the available samples using the available timing in-
formation. To that purpose, we propose the use of a simplified
form of the Lagrange interpolation polynomial, as discussed
in [11]. This leads to a time-varying filter implementation. The
(14) coefficients of the resulting time-variant filter are known, so
the computational complexity is in the order of that of an FIR
filter of order less than 160 [11].
Other compensation methods such as fractional delay filters
[13] or spline interpolation [14] could also be used. The fully
compensated signal rac (n) is then a good estimate of the
ideally sampled signal radI (n).
IV. S IMULATION RESULTS
For the simulation, we use an OFDM signals with N =
1024 subcarriers, a cyclic prefix of Ncp = 64, and 16-
QAM symbols. The residual SI link (after antenna and RF
cancellation) is a Rician channel of length Lsi = 3 coefficients
and a K-factor1 of 5dB; and the SR link is a time-varying
frequency-selective Rayleigh channel of length Lsr = 5
coefficients. The channels are assumed known. The transmitted
power is Ptx = 20 dBm unless it is stated otherwise.
Antenna and RF cancellation are respectively Aan = −50 dB
1 The K-factor in the Rician channel model is the ratio between the energy
in the specular path and the energy in the scattered paths.
 ICC2017: WT07-Workshop on Full-Duplex Communications for Future Wireless Networks

and Arf = −30 dB. On the other hand, we consider the

30
challenging situation when the received signal is close to the
receiver sensitivity level. We assumed that the signal of interest
is received with a power of Prx = −80 dBm, i.e. the SI is 20
20 dB over the signal of interest at the LNA input. We consider
that the LNA2 gain is

SINR [dB]
q 10
Klna = Ptx Prx /(Aan Arf P{z(n)}) (15)
6 bits
where P{·} is the peak-to-average power ratio, so that the 0
8 bits
received signal fit into the ADC dynamic range. We use the 10 bits
soft-limiter model (linearized PA) to describe the behavior of −10 12 bits
the PA and consider an input back-off of 8dB to moderate
clipping effects [15]. 14 bits
The soft limiter model is specified as −20
10 15 20 25 30
SNR
(
νx(n) |νx(n)| < As
fpa {x(n)} = (16)
As |νx(n)| > As Fig. 3. Receiver SINR as a function of ADC resolution, considering ideal
quantization. The resolutions considered are 6, 8, 10, 12, and 14 bits (Tx
where ν is the input backoff (IBO), which scales the symbols power = 20dBm).
to reduce in-band distortion and As is the saturation output
amplitude. The signal to noise ratio, SNR, in the FD receiver
is given by, 30
Prx
SN R = (17)
Pw 25
where Prx is power of the received signal (signal of interest)
20
and Pw is the source-receiver channel noise. In our setup,
SINR [dB]

the Prx is fixed in −80 dBm and the channel noise is 15

scaled to obtain a SNR variation range from 10 to 30 dB.
The simulated ADC is an 8 branch TI ADC with timing 10
mismatch following the model in [16], working at a sample Ideal ADC
frequency equal to twice the signal bandwidth at baseband. We 5 1% mismatch
focus on timing mismatch because gain and offset are static 2% mismatch
errors and therefore straightforward to estimate and correct 0 3% mismatch
for, whereas timing mismatch is signal dependent and requires Compensated
signal processing. −5
10 15 20 25 30
A. Analysis of performance degradation SNR
The received signal quality at a receiver can be measured by Fig. 4. Receiver SINR for the ideal ADC, for a TI ADC with 1-3% timing
the signal-to-interference plus noise ratio (SINR), which is the mismatch, and for the TI ADC after compensation (Tx power = 20dBm).
ratio of the power of the useful signal to the distortion plus
noise power. Generally, the standards define a threshold for
the SINR [17]. Different constellation size and coding rate will self-interference signal and the channel noise. The interference
require different SINR thresholds to operate correctly. Systems signal can be calculated as the difference between the original
with reduced constellation size are able to operate with low signal Z(k) and the impaired signal Rad (k), i.e.
levels of SINR. If the size of the constellation increases, the
I(k) = Rad (k) − Z(k) (19)
SINR should be increased as well.
The SINR, evaluated after the DFT operation and channel where Rad (k) = DFT{rad (n)}.
equalization, is defined as In Fig. 3, we show how the number of bits of the ADC
N −1
1 X E[|Z(k)| ]
2 affects the performance of the SI digital cancellation reducing
SIN R = 2 (18) the SINR at the receiver side. We can infer than using less
N E[|I(k)| ]
k=0 than 10 bits compromises seriously the performance of the SI
where E[|Z(k)|2 ] is the power of the intended signal at cancellation.
subcarrier k and E[|I(k)|2 ] is the power of the interference In Fig. 4, we investigate the SINR degradation in the system
signal introduced by the non-ideal ADC and PA, the residual with a time mismatch of 0-3% in a 12-bit TI ADC. Comparing
Figs. 3 and 4, we see that the effect of a timing mismatch
2 Note the AGC gain is also absorbed in Klna greater than 2% is equivalent to having an ENOB of 8 bits,
 ICC2017: WT07-Workshop on Full-Duplex Communications for Future Wireless Networks

30 40
Ideal Ideal
W/mismatch 35 W/mismatch
25 Compensated Compensated
30
SINR [dB]

20 25

L [dB]
20
15 15

10
10
5

5 0
10 15 20 25 30 6 8 10 12 14 16
SNR ADC resolution
Fig. 5. Receiver SINR for the ideal ADC, a TI ADC with 1% timing Fig. 7. SINR loss for the ideal ADC, a TI ADC with 1% timing mismatch,
mismatch, and for the TI ADC after compensation when considering saturation and for the TI ADC after compensation when considering saturation effect
effect on the PA (Tx power = 20dBm, IBO = 8dB). on the PA and different ADC resolution (SNR = 30dB, IBO = 8dB).

30 operation and limited ADC resolutions, defined as L[dB] =

SN R[dB]−SIN R[dB], as a function of ADC resolution for a
25 SNR of 30 dB. It can be seen that once the required resolution
for adequate detection is reached, increasing the resolution
20 beyond this value does not affect performance. However, ADC
SINR [dB]

compensation is still needed.

15
10
Ideal
5 W/mismatch
Compensated
0
−20 −10 0 10 20 30
Tx Power [dBm]
Fig. 6. Receiver SINR for the ideal ADC, a TI ADC with 1% timing
mismatch, and for the TI ADC after compensation when considering saturation
effect on the PA (SNR = 30dB, IBO = 8dB).
whereas a 1% mismatch is like having an ENOB of 10 bits.
However, after compensation we regain the lost resolution due
to the ADC distortion.
Fig. 5 shows the SINR including the clipping effects on
the transmitter PA that affects the SI cancellation performance
(a linear digital canceller is considered in our study). Here
there is a slight loss of performance when comparing with
the previous case of an ideal PA, and ADC induced distortion
results in an even worse performance if not compensated.
In Fig. 6, we show the SINR as a function of the transmitted
power for a fixed SNR of 30 dB and ADC resolution of 12
bits. It can be seen that, as expected, the higher the transmitted
power, the lower the SINR, since the SI is larger for higher
transmitted power.
Fig. 7 shows the penalty in terms of SNR due to full duplex
Simulation results show that for a compensated TI-ADC,
the SINR loss due to the FD operation mode is around 3 dB.
In other words, this means that the SINR requirements at the
FD receiver input are increased by 3 dB.
For example, a half-duplex LTE user requires a SINR of
22.6 dB to operates with 64 QAM and coding data rate of 4/5
[17]. Using the proposed implementation, the 3 dB penalty
increases the required SINR to 25.6 dB. On the other hand,
a TI ADC without compensation can not reach the necessary
SINR level, as noted from Figs. 6 and 5.
V. C ONCLUSIONS
We investigate the effect of ADC induced distortion in a
full-duplex (FD) transceiver in case of mismatch errors in
a time-interleaved (TI) topology. The self-interference (SI)
can be tens of decibels larger than the signal of interest,
and mismatch errors limit significantly the SI compensation
capability, because they reduce the effective digital dynamic
range of the ADC. Even a low mismatch of 1% introduces
a penalty of approximately 12 dB (equivalent to 2 bits in
the ENOB) for a 12-bit ADC. On the other hand, we show
that a digital compensator is able to restore most of the
performance lost and enables the use of TI-ADCs in 5G
broadband transceivers.
 ICC2017: WT07-Workshop on Full-Duplex Communications for Future Wireless Networks
R EFERENCES
[1] M. Heino, D. Korpi, T. Huusari, E. Antonio-Rodriguez, S. Venkatasub-
ramanian, T. Riihonen, L. Anttila, C. Icheln, K. Haneda, R. Wichman,
and M. Valkama, “Recent advances in antenna design and interference
cancellation algorithms for in-band full duplex relays,” IEEE Commu-
nications Magazine, vol. 53, pp. 91–101, May 2015.
[2] A. Sabharwal, P. Schniter, D. Guo, D. W. Bliss, S. Rangarajan, and
R. Wichman, “In-band full-duplex wireless: Challenges and opportu-
nities,” IEEE Journal on Selected Areas in Communications, vol. 32,
pp. 1637–1652, Sept 2014.
[3] T. Riihonen and R. Wichman, “Analog and digital self-interference
cancellation in full-duplex MIMO-OFDM transceivers with limited
resolution in A/D conversion,” in Proc. Asilomar Conference on Signals,
Systems and Computers, Nov. 2012.
[4] D. Korpi, T. Riihonen, V. Syrjälä, L. Anttila, M. Valkama, and R. Wich-
man, “Full-duplex transceiver system calculations: Analysis of ADC and
linearity challenges,” IEEE Transactions on Wireless Communications,
vol. 13, pp. 3821–3836, July 2014.
[5] J. J. Bussgang, “Cross correlation function of amplitude-distorted Gaus-
sian input signals,” Res. Lab Electron., M.I.T., Cambridge, MA, Tech.
Rep. 216, vol. 3, Mar. 1952.
[6] 3rd Generation Partnership Project; Technical Specification Group Radio
Access Network, “Study on scenarios and requirements for next gen-
eration access technologies; (release 14).” 3GPP TR 38.913 V14.0.0,
2016.
[7] S. Ouzounov, R. van Veldhoven, C. Bastiaansen, K. Vongehr, R. van
Wegberg, G. Geelen, L. Breems, and A. van Roermund, “A 1.2v 121-
mode CT x00394; x003A3; modulator for wireless receivers in 90nm
CMOS,” in 2007 IEEE International Solid-State Circuits Conference.
Digest of Technical Papers, pp. 242–600, Feb 2007.
[8] Y. Chi, D. Li, and Z. Wang, “A 16-bit 1MS/s 44mW successive approx-
imation register analog-to-digital converter achieving signal-to-noise-
and-distortion-ratio of 94.3dB,” in 2013 IEEE International Conference
of Electron Devices and Solid-State Circuits (EDSSC), pp. 1–2, June
2013.
[9] C. Schmidt, O. Lifschitz, J. Cousseau, J. Figueroa, and P. Julian,
“Methodology and measurement setup for analog-to-digital converter
postcompensation,” IEEE Transactions on Instrumentation and Mea-
surement, vol. 63, pp. 658–666, March 2014.
[10] R. V. de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-
Analog Converters. Dordrecht, The Netherlands: Kluwer Academic,
2003.
[11] C. A. Schmidt, J. E. Cousseau, J. L. Figueroa, B. T. Reyes, and
M. R. Hueda, “Efficient estimation and correction of mismatch errors
in time-interleaved ADCs,” IEEE Transactions on Instrumentation and
Measurement, vol. 65, pp. 243–254, Feb 2016.
[12] D. Dardari, V. Tralli, and A. Vaccari, “A theoretical characterization of
nonlinear distortion effects in OFDM systems,” IEEE Transactions on
Communications, vol. 48, pp. 1755–1764, Oct. 2000.
[13] T. Laakso, V. Valimaki, M. Karjalainen, and U. Laine, “Splitting the unit
delay [FIR/all pass filters design],” IEEE Signal Processing Magazine,
vol. 13, pp. 30–60, Jan 1996.
[14] G. Qin, G. Liu, M. Gao, X. Fu, and P. Xu, “Correction of sample-
time error for time-interleaved sampling system using cubic spline
interpolation,” Metrology and Measurement Systems, vol. 21, pp. 485–
496, Aug. 2014.
[15] R. Prasad, OFDM for Wireless Communications Systems. Boston Artech
House, 2004, 2004.
[16] M. Seo, M. J. W. Rodwell, and U. Madhow, “Comprehensive digital
correction of mismatch errors for a 400-msamples/s 80-dB SFDR
time-interleaved analog-to-digital converter,” IEEE Transactions on Mi-
crowave Theory and Techniques, vol. 53, no. 3, pp. 1072–1082, 2005.
[17] I. T. Stefania Sesia and M. Baker, LTE – The UMTS Long Term
Evolution: From Theory to Practiced. John Wiley & Sons, Ltd., 2009.