Lecture 10

Parallel Input/Output

Topics
 Parallel Input/Output Interfacing
 8086 Basic I/O Interfaces

2
 Input/Output Interfacing
 Peripheral Devices are I/O devices that exchange data with a CPU.
 Examples : Switch, push-button, light-emitting diode (LED), monitor,
LCD screen, printer, mouse, keyboard, disk drive, sensor, motor, audio, etc.
 Interface Chips are used to resolve the differences between CPU and I/O
devices.

System Bus Data Bus

CPU Address Bus
Control Bus

I/O I/O I/O I/O

1 2 3 4 Interface Ch ps

key- mon tor Per pheral Dev ces

pr nter d sk
board

I/O Interfacing Methods

 An interface chip resolves the differences between the CPU and
a peripheral device.
 Data codes and formats in peripherals may be different.
 A synchronization mechanism is needed.
Data transfer rate of peripherals are usually slower than CPU.
 Communication between CPU and Interface Chip:
Always parallel.
 Communication between Interface Chip and I/O Device:
Can be either parallel or serial.

 There are two I/O interfacing methods:

 Isolated I/O Method
 Memory-Mapped I/O Method

4
 Isolated
I/O Interfacing Method
 The M / IO control signal of the CPU is used as a selector
between Memory chips and Input/Output chips.
 Separate memory and I/O address spaces are used.
 There are distinct input and output instructions.
 Example 8086 Assembly language instructions : IN , OUT

Using M/IO Signal for

Isolated I/O Interfacing
The M / IO control s gnal of the CPU s used as Memory ch p
select on and also Input-Output Interface ch p select on.

 M / IO = 1 means Memory ch p s selected

 M / IO = 0 means Input-Output ch p s selected

M / IO
CPU CS

RAM

CS
I/O
Interface
 Address Spaces in
Isolated I/O Interfacing
●
The entire memory address space is used by memory chips only.
●
There are no reseved addresses for I/O chips in memory address space,
because the I/O addresses are separated from memory addresses.

FFFFFH

1MB
Total Memory

(ROM & Separate

RAM chips) Address Space

0FFFFH
64KB
I/O chips
00000H 00000H

Port Map in
Isolated I/O Interfacing
●
The bytes of data in two consecutive I/O addresses could be accessed
as either byte-wide data, or as word-wide data.
●
Example: I/O addresses 0000h, 0001h, 0002h, 0003h can be treated as
independent byte-wide ports 0, 1, 2 and 3.
●
Or they can be treated as as word-wide ports 0 and 1.
 Memory-Mapped
I/O Interfacing Method
 The M / IO control signal is not used.
 Memory and I/O addresses share common address space.
 There are no specific input/output instructions.
 Usual memory load/store instructions are used.
 Example 8086 Assembly language instruction : MOV

Address Spaces in
Memory-Mapped I/O Interfacing
●
There is a reseved address range in the memory space for the I/O chips.

FFFFFH

64KB
64K
I/O Reserved for I/O

Memory
(ROM &
RAM

00000H
 Example: Memory Mapped I/O Interfacing
 Example: 4 memory addresses are reserved (ded cated) for Input-Output register addresses.
 Suppose the memory addresses from 0000h to 0003h are reserved for I/O reg sters.
 The NAND gate can be used on address l nes A15 - A2 for ch p select ons (RAM or I/O).
 For I/O reg ster select ons w th n the I/O nterface ch p, A0 and A1 l nes can be used.

(Alternat ve method:
An Address Decoder can be
used, nstead of NAND gate.)
A15 - A2
RAM
CPU NAND CS

A1
CS
I/O
Interface A0
Reserved addresses for I/O nterface ch p:
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
(Hex)

0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address Map Used by
0001h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0002h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0000h - 0003h I/O

0003h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0004h - FFFFh RAM

11

Differences Between Isolated I/O

and Memory-mapped I/O

12
 Input/Output Transfer
Synchronization
 The tasks of the interface chip are :
 Synchronizing data transfer between CPU and Interface chip (Control signals).
 Also between Interface chip and I/O device (Handshaking signals).

Control Handshake
s gnals s gnals
Interface I/O
CPU
Ch p Dev ce

Data Bus

Address Bus

13

CPU and I/O Interfaces

 Programmed I/O (Polling method)
 CPU checks device status in a loop

 CPU waits for I/O module to complete operation

 Wastes CPU time

 Interrupt Driven I/O

 Overcomes CPU unnecessary waiting

 No repeated CPU checking of device

 I/O module interrupts when ready

 Direct Memory Access (DMA)

 Requires additional hardware module on bus

 DMA controller takes over from CPU, for I/O operations

14
 Programmed I/O
(Polling method)
 Input Operations :
Microprocessor checks a status bit of the interface
chip, to find out whether the interface has
received new data from input device.

 Output Operations :
Microprocessor checks a status bit of the interface
chip, to find out whether it can send new data to
interface chip.

15

Interrupt Driven I/O

 Input Operations :
Interface chip interrupts the microprocessor,
whenever it has received new data from input device.

 Output Operations :
Interface chip interrupts the microprocessor,
whenever it can accept new data from microprocessor.

16
 Parallel Communication
 In parallel communication, all bits are transferred at the same time.
 Each bit is transferred along its own line.
 In addition to eight parallel data lines, other lines are used to read status
information and send control signals.

Ready s gnal

D7

Transm tt ng Rece v ng
S de S de

D0

Data Val d s gnal

17

Example: Synchronization of
two parallel computers
 Transmitter and receiver interfaces use handshaking protocol.
 Transmitter initiates 2-wire handshaking
 DV low indicates new data is available.
 DR low indicates that receiver has read the data.

Data Valid (DV) s gnal

Handshak ng

Data Received (DR) s gnal

18
 Basic Parallel Input Interface
 The basic input device (to the microprocessor) is a set of tri-
state buffers.
 When data is coming in by way of a data bus (either from port
or memory) it must come in through a three-state buffer.
 Tri-state buffer chips can be used as input interface.
(Example chip: 74244)
 Output pins of interface are connected to Data Bus of CPU
(as input of CPU).
 Input pins of interface are connected to an input device.

19

Basic Parallel Input Interface

D7
. D7
.
Input Device

.
Basic
Input
CPU Interface
D0
D0

Address Bus R/W

CLOCK
CS
Address (control s gnal)
Decoder SELECT

20
 Basic Input Interface Timing Diagram
1) Address placed on address bus at the falling edge of clock.
CLOCK

ADDRESS

2) Address decoded, in order to form the CS (Chip Select) (Enable) signal.

SELECT

R/W

3) NAND {CLK, M/IO, READ} applied, in order to form CS signal.

CS

DATA
21

Basic Parallel Output Interface

 The basic output device (from the microprocessor)
is a set of latches.
 Since the data provided by the CPU to an output port is on the
system data bus for a limited amount of time
(50 - 1000 nano seconds) it must be latched before it is lost.
 D-Latches (Data Latches) can be used as output interface.
(Example chip: 74374)
 Inputs of interface are connected to the Data Bus of CPU.
 Outputs of interface are connected to an output device.

22
 Basic Parallel Output Interface

D7

. Q7
. .

Output Device
Basic

.
Output
CPU Interface .
D0 .
Q0

R/W
Address Bus

CLK
HOLD
Address
Decoder SELECT

23

Basic Output Interface Timing Diagram

1) Address placed on address bus at the falling edge of clock.
CLOCK

ADDRESS

2) Data is placed on the data bus.

DATA

3) Address decoded, in order to form the Select signal.

4) NAND {CLK, SELECT, R/W} applied, in order to form HOLD.

SELECT

R/W
HOLD

24
 Topics
 Parallel Input/Output Interfacing
 8086 Basic I/O Interfaces

25

8086 Minimum Mode

I/O Interface
The interface circuitry performs the following tasks.
●
Selecting the particular I/O port
●
Synchronise data transfer
●
Write the output data
●
Read the input data

26
 Parallel I/O Interface Chips
for 8086 CPU
Generic Name Chip Number I/O Direction Usage

74374
Latch Output only
(or 74373)

74244
Buffer Input / Output
(or 74245)

Programmable
8255 Input / Output
Peripheral Interface

27

8086 Assembly Instructions for I/O

●
The 8086 microprocessor can access data from I/O ports as well as from the
memory.
●
8086 can be used with isolated I/O, or memory-mapped I/O interface methods.
●
In isolated method, the IN and OUT instructions are used between CPU and I/O
interface for data transfers.
●
Any I/O port in the interface chip can be used for either 8-bit or 16-bit data
transfer.

Port Input Output

Description
Address instruction instruction

Fixed IN AL, port OUT port, AL

Port addresses between 00-FF
address
are written with instruction.
(Direct) IN AX, port OUT port, AX

Variable IN AL, DX OUT DX, AL Port addresses between 100h-

address FFFFh should be loaded to DX
(Indirect) IN AX, DX OUT DX, AX register first.(Indirect addressing)

28
 Ports

I/O devices connect to the CPU through ports.

Ports are:
●
Registers (part of the I/O interface chip)
●
Can be 8, 16, or 32 bits wide
●
Addressed in the range 0000-FFFFh
●
Accessed with Assembly instructions IN, OUT

29

IN Instruction
●
The IN instruction copies data from a peripheral device port to the AL or AX register.
●
If an 8-bit port is read, the data will go to AL.
●
If a 16-bit port is read, the data will go to AX.
●
IN instruction does not change any flag.
●
IN instruction has two possible formats, fixed port and variable port.
●
FIXED PORT FORMAT: The 8-bit address of a port is specified directly in the instruction.
Up to 256 possible ports can be addressed.

General Syntax IN Accumulator, PortNumber

Examples: 8 bit fixed port address

IN AL, OC8H Input a byte from port OC8H to AL

IN AX, 34H Input a word from port 34H to AX

30
 IN Instruction
●
VARIABLE-PORT FORMAT: The port address is loaded into the DX register
(Indirect Addressing) before the IN instruction.
●
Since DX is a 16-bit register, the port address can be any number
between 0000H and FFFFH.
●
Therefore, up to 65,536 ports are addressable in this mode.
●
The variable-port IN instruction has advantage that the port address
can be computed, or dynamically determined in the program.

Examples: 16 bit variable port address

MOV DX, 0FF78H Initialize DX to point to port

IN AL, DX Input a byte from 8-bit port 0FF78H to AL

IN AX, DX Input a word from 16-bit port 0FF78H to AX

31

Example: IN Instruction
●
Suppose that the port address 13H is an input port for
monitoring the temperature.
●
A sensor input data can be read from that port.

●
Write the Assembly language looping instructions to monitor
the port continuously for the temperature of 100 degree.
●
If temperature 100, then store 1 to the BH register.

MOV BH, 0 ;Clear BH register

OKU:
IN AL, 13H ;Get the temperature data from port# 13H
CMP AL, 100 ;Is temperature =100?
JNZ OKU ;If not, keep monitoring

MOV BH, 1 ;Temperature =100, load 1 into BH register

32
 Input Buffering
Reason for buffering:
●
Input devices must be isolated from the global system data bus.
Otherwise unwanted data (random) may be transferred on to the
data bus.
●

When data comes in from a port/memory, data must be input

through a tri state buffer.
●

Tri-state buffers are used which provide isolation as well as

strengthen the signal.
●

●
Example: Interfacing input devices like switches require buffers.

33

Example: Address Decoding Circuit

for Input Port 9Ch
Example instruction:
IN AL, 9CH

74244
Buffer
To From
8086 Input
CPU Device

34
 OUT Instruction
●
The OUT instruction copies a byte from AL or a word from AX to the specified port.
●
OUT instruction does not change any flag.
●
Similarly to IN instruction, the OUT instruction has two possible forms,
fixed port and variable port.
●
FIXED PORT FORMAT: The 8-bit port address is specified directly in the instruction.
●
Up to 256 possible ports can be addressed.

General Syntax OUT PortNumber, Accumulator

Examples: 8 bit fixed port address

OUT 3BH, AL Copy the content of AL to port 3BH

OUT 2CH, AX Copy the content of AX to port 2CH

35

OUT Instruction
●
VARIABLE PORT FORMAT: The OUT instruction copies , content (data) of AL or AX
to the port at an address contained in DX.
●
The DX register must be loaded with the desired port address,
before this form of the OUT instruction is used.

Examples: 16 bit variable port address

MOV DX, 0FFF8H Load a port address (16 bit) in DX

OUT DX, AL Copy content of AL to port FFF8H

OUT DX, AX Copy content of AX to port FFF8H

36
 Output Latching
Reason for latching:
Any microprocessor-based system when data is sent out by processor,
the data on the data bus must be latched by the receiver/output
●

device.
●
Memory chips have internal latches store data.
●
Latching system must be designed for I/O ports.
Data provided by the processor is available only for short period of
time 50 1000 ns) data must be latched else it will be lost.
●

●
Example: Interfacing output devices like LEDs require latches.

37

Example: Address Decoding Circuit

for Output Port 9Ch
Example instruction:
OUT 9CH, AL

From To
74374
8086 Output
Latch
CPU Device

G: Gate enable
OE: Output Enable

38
 Basic Output Interface
with 74374 Latch chip
●
The 74374 chip is a three-state Octal (8 bit) D-type Latch.
●
It can be used for output.
●
Suppose 8 LEDs (Light Emitting Diodes) are connected
to the latch chip.
●
The latch chip is connected to the 8086 CPU.
●
Isolated I/O interface method will be used.
●
Suppose the fixed port address of the Latch chip is 00004h.
●
For address decoding, logic gates (NAND) will be used.
●
Draw the block diagram hardware design showing
the connection signals and address decoding circuit.

39

Internal Diagram of
74374 Latch chip
●
The D-Latch chip has 8 inputs (D1-D8), and 8 outputs (Q1-Q8).
●
CLOCK pin is used as chip enable signal.
●
Output Control pin is connected to ground.

40
Application Example1: LEDs Blinking Program
M / IO
Address 74374 Latch chip is used to drive 8 LEDs
WR
●

Decode (supplying the electrical current).

Logic NAND gate is used for address decoding.
A0
●

Address Resistors are required for limiting the

A1 (For
●

Lines port
current on each LED.
A2 (04h)

8086
A3-A15 Output Select

CPU (As Chip Enable) LEDs Resistors

(Minimum
CLK Q0
D0
Mode)
D0 Q1
D1 D1 Q2

74374
D2 D2 Q3
D3 D3 Q4
D4 D4 (Latch) Q5
D5 D5 Q6
D6 D6 Q7
D7 D7
Data OC
Bus
Output
Control 41

LEDs Blinking Program

●
Write an Assembly program that turns all 8 LEDS
on / off continiously (Blinking = Flashing).
●
There should be some waiting time between each
on and off operation.
●
When user press a key on keyboard, program exits
the endless loop.

All LEDs are on

All LEDs are off

42
 LEDs Blinking Program

Part-1
; Program for Blinking (Flashing) all LEDs.
; (With 74374 Latch chip)
; In Emu8086, all 12 traffic lights are turned on and off endlessly.

.model small

.data
Cumle DB 'CIKMAK ICIN BIR TUSA BASINIZ',13,10,'$'

.code
BASLA PROC

.STARTUP
mov dx, OFFSET Cumle ;Move address of Cumle variable to DX
mov ah, 09h ;Function code for displaying string
int 21h

43

Part-2
MainDongu: ;Endless main loop
mov ax, 0FFFH ;Turn all LEDs on
out 4, ax ;Fixed address of output port is 4.

; Wait for 1 second.

mov cx,0FFh
bekle1: loop bekle1

mov ax, 00H ;Turn all LEDs off

out 4, ax

; Wait for 1 second.

mov cx,0FFh
bekle2: loop bekle2

MOV AH, 01 ;Check for keyboard press

INT 16H ;Using INT 16H
JE MainDongu ;Jump if ZF equal 1

.EXIT
BASLA ENDP

END BASLA ;End of file

44
 LEDs Blinking Program
(Using Emu8086 Emulator)
●
Run the LEDs program in Emu8086 emulator.
●
Open the Virtual Devices --> Traffic_Lights.exe program.
●
By default, Emu8086 uses the port address at 4 for LED outputs.
●
Emu8086 enumarates the 12 LEDs as 0,1,2,3,...,A,B.
●
The following is the emulation screen for the LED binking application,
by using the 12 traffic ligths as LEDs.

All LEDs are turned off All LEDs are turned on

45

Application Example2: Sending Sound Output

to Computer Speaker
●
Write an Assembly program to that sends a fixed volume sound to the
computer’s internal speaker.
●
The port address of the internal speaker of computer is 61h.
●
It is an output port in 8255 Programmable Peripheral Interface chip.
●
Program runs in endless loop, until user press a key on keyboard to exit.

hoperlor EQU 61h ; Port address of internal computer speaker

.model small
.data
Part1 Cumle DB 'CIKMAK ICIN BIR TUSA BASINIZ','$'

.code

Basla PROC

.startup

mov dx, OFFSET Cumle ;Move address of Cumle variable to DX

mov ah, 09h ;Function code for displaying string
int 21h ;DOS interrupt service
46
 Part2

mov AL, 00000011b ;Set rightmost two bits

out hoperlor, AL ;Turn speaker on and start the sound
;---------------------------------
dongu: ;Endless loop
MOV AH, 01 ;Check for key press
INT 16H ;Using INT 16H of BIOS keyboard service
JE Dongu ;Jump if ZF equal 1
;---------------------------------
mov al, 0 ;Clear all bits
out hoperlor, al ;Turn speaker off

.exit
Basla ENDP
END Basla

47

Basic Input Interface

with 74244 Buffer chip
●
The 74244 chip is a Octal (8 bit) 3-state Buffer
(Line Driver / Line Receiver).
●
It can be used as memory-address driver, and bus-oriented
transmitter/receiver.
●
Suppose 8 Buttons are connected to the buffer chip.
●
The buffer chip is connected to 8086 CPU.
●
Suppose the port address of the Buffer chip will be
stored in DX register as 00001h.
●
Draw the block diagram hardware design showing
the connection signals and address decoding circuit.

48
 Internal Diagram of
74244 Buffer chip
●
The Buffer chip has 8 inputs (A1-A8), and 8 outputs (Y1-Y8).
●
Each of the G1 and G2 pins controls 4 input bits.

G: Gate enables
49

Application Example3: Buttons Inputs Program

M / IO
RD
Address
Address A0 (01h)
Lines Decode Input
A1-A15 Logic Enables
5V
Pull-Up
Resistors

8086
Minimum
G: Gate enables
Buttons
G1 G2

Mode
A0
D0 Y0 A1
D1 Y1 A2

74244
D2 Y2 A3
D3 Y3 A4
D4 Y4 (Buffer) A5
D5 Y5 A6
D6 Y6 A7
D7 Y7
Data
Bus 50
 Switch Bounce Problem
●
When a switch is closed, it could cause multiple ON and OFF signals lasting
several milliseconds.
●
This multiple switch closing / opening action is called Switch Bounce problem.
(Also called as Contact Noise problem)
●
Software solution: Detect first key-press, wait for a short time, then read again.
●
Hardware solution: Use a Pull-Up or Pull-Down resistor with the switch (or button).

5V Vout
If switch is open, the output is 0V (Low, Logic 0)
If switch is closed, the output is 5V (High, Logic 1)

Expected Pulse Bounce Problem

Switch
is closed

Switch
is open
51

Switch with
Pull-Up Resistor
●
The pull-up resistor pulls a pin of a chip up to a HIGH state.
●
Input of the buffer chip is normally HIGH.
●
When the switch is closed, input of the chip drops to LOW.

Resistor Input
High

(Buffer)

52
 Switch with
Pull-Down Resistor
●
It is the opposite of Pull-Up resistor.
●
The pull-down resistor pulls a pin of a chip down to a LOW state.
●
Input of the buffer chip is normally LOW.
●
When the switch is closed, input of the chip becomes HIGH.

Input
Low

Resistor (Buffer)

53

Buttons Inputs Program

●
Write an Assembly program to continiously read the 8 buttons connected to 74244 chip.
●
Program should exits when user presses any button,
or presses any key on computer keyboard.
; (With 74244 Buffer chip)
.model small
.data
Cumle DB 'CIKMAK ICIN BIR TUSA BASINIZ',13,10,'$'
.code
BASLA PROC
.STARTUP
mov dx, OFFSET Cumle ;Move address of Cumle variable to DX
mov ah, 09h ;Function code for displaying string
int 21h
;------------------------------------------------------------------------------------------
mov dx, 00004h ;Variable address of output port is 04h.
MainDongu: ;Endless main loop
in AL, dx ;Read all button inputs
cmp AL, 0FFh ;FF means inputs are normally all high.
;When a button is pressed, its input drops to low.
JNE Son ;Jump if ZF equal 0 (a buttons is pressed)
;------------------------------------------------------------------------------------------
MOV AH, 01 ;Check for keyboard press
INT 16H ;Using INT 16H
JE MainDongu ;Jump if ZF equal 1
;------------------------------------------------------------------------------------------
Son:
.EXIT
BASLA ENDP
END BASLA ;End of file 54
 Example4: Switches
and 7-Segment LEDs

Switches

8086
CPU 74244
Buffer

Pull-down
resistors

74374
Latch 7 segment
LEDs

55

Example5:
8 LEDs
a) 74245 Buffer as
output interface chip.

b) Address decoding circuit

+5V
c) Outputs (8 LEDs)

Port address
(74245 chip
selection) is
0F000h

56
 Determining the Port Address
M/IO Write A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

0
0 Port address =
0
0 0F000h
0
0
0
0
0

0
0
0
1
1
1
1
0
0
57

Example6:
8 Buttons
+5V

a) 74245 Buffer as
input interface chip.

b) Address decoding circuit

c) Inputs (8 buttons)

Port address
(74245 chip
selection) is
0F000h

58