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Denver Pels 20071113 Cooper Vhdl-Ams
Denver Pels 20071113 Cooper Vhdl-Ams
Modeling Language
Scott Cooper
Mentor Graphics
Pin Definitions:
p1, p2 - electrical pins
entity resistor is
port (
terminal p1, p2 : electrical);
end entity resistor;
Entity/model name
i = v / res
Characteristic Equation:
i = v / res
Architecture name
Quantity “v” refers to “v” and “i” are defined with respect
the across aspect of to terminal ports p1 and p2
terminal ports p1 and p2
Generic type
Optional initializer
entity resistor is
generic (
Generic name res : real := 10.0e3);
port (
terminal p1, p2 : electrical);
end entity resistor;
+ v- Pin Definitions/Argument:
p1
i
p2 p1, p2 : electrical pins
ind : user supplied argument
use ieee.electrical_systems.all;
entity inductor is
generic (
ind : real); -- inductance value
port (
terminal p1, p2 : electrical);
end entity inductor;
+ v- Fundamental Equation:
p1 p2 di
i
v = ind
dt
Pin Definitions/Argument:
p, n : electrical pins
Isat : user supplied argument
entity diode is
generic (
-- saturation current
Isat : current := 1.0e-14;
port (
terminal p, n : electrical);
end entity diode;
Fundamental Equation:
v
i = Isat * (exp vt
− 1 .0 )
entity opamp_3p is
generic (
a_ol: real := 100.0e3;
f_0dB: real := 1.0e6
);
port (
terminal in_pos: electrical;
terminal in_neg: electrical;
terminal output: electrical
);
end entity opamp_3p;
v T
i hflow
R v*i = power => heat flow rth cth
(Powerelectrical = Powerthermal)
Electrical model governing power Thermal model governing power (heat flow)
For the thermal capacitance component (cth), the governing equation is:
hflowcap = cth*dT/dt
where the heat flow is the product of the time derivative of the filament
temperature (T) and the thermal capacitance (cth). The thermal conductance
(rth) component is formulated as follows:
hflowres = (T - TA)/rth
where the heat flow is the ratio of the delta temperature (actual temperature
(T) minus ambient temperature (TA)), and the thermal resistance. The lamp
will also dissipate heat in the form of electromagnetic radiation.
entity Lamp is
generic (
r_cold : resistance := 0.2; -- Filament resistance at temp_cold
temp_cold : temperature := 27.0; -- Calibration temperature [deg C]
alpha : real := 0.0045; -- Resistive temp coefficient [ohms/deg C]
ke : real := 0.85e-12; -- Radiation coefficient [watts/K^4]
rth : real := 400.0; -- Thermal conduction [deg C/watt]
cth : real := 0.25e-3; -- Thermal heat capacitance [joules/C]
temp_amb : temperature := 27.0); -- Ambient temperature [deg C]
port (terminal p1, p2 : electrical);
end entity Lamp;
Q’above(threshold);
When signal S changes value, quantity Q tracks this change, but transitions to
it over a linear interval of tr or tf, depending on the direction of the change.
The ‘ramp attribute also performs the function of restarting the analog solver at
the discontinuous points when signal S is updated. This is a very important
consideration for analog simulation so that the simulator does not get “lost”
when encountering a discontinuity.
entity a2d is
generic (vthreshold : real := 2.0);
port (d_output : out std_logic;
terminal a_input : electrical);
end entity a2d;
The purpose of this switch is to allow or prevent current flow between pins p1
and p2, depending on the value of sw_state. Ports p1 and p2 are electrical
analog, and port sw_state is std_logic digital.
entity switch_dig_nogen is
port ( sw_state : in std_logic;
terminal p1, p2 : electrical );
end entity switch_dig_nogen;
entity limiter_ideal is
generic (
limit_high : real := 10.0; -- upper limit
limit_low : real := -10.0); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_ideal ;
Input perturbations
D The Designer’s Guide to Analog & Mixed-Signal Modeling (R. S. Cooper - ISBN
0-9705953-0-1, published by Avant!, 2001) includes numerous model examples in
both the VHDL-AMS and MAST modeling languages.
Scott Cooper
Mentor Graphics
www.mentor.com/systemvision
INTRODUCTION environment in which a system can be tuned,
This paper introduces a systematic process for optimized, and critical insights can be gained –
developing and analyzing system models for the before any hardware is built. During the
purpose of computer simulation. This process is verification phase of the design, simulation
demonstrated using the Digitally-Controlled technologies can again be employed to verify
Positioning System (referred to as “Position intended system operation.
Controller”) shown in Figure 1. It is a common mistake to completely design a
system and then attempt to use simulation to
WHAT IS COMPUTER SIMULATION? verify whether or not it will work correctly.
The general concept of “computer simulation” Simulation should be considered an integral part
(referred to simply as “simulation” in this paper) of the entire design phase, and continue well into
is to use a computer to predict the behavior of a the manufacturing phase.
system that is to be developed. To achieve this, a
“system model” of the real system is created. This SYSTEM OVERVIEW
system model is then used to predict actual system The Position Controller is composed of two
performance and to help make design decisions. sections, as indicated by the dotted line dividing
Simulation typically involves using the system shown in Figure 1. These sections are
specialized computer algorithms to analyze, or referred to as the Digital Command and Servo
“solve”, the system model over some period of subsystems. These subsystems will be developed
time (time-domain simulation) or over some range individually, and then combined to form the
of frequencies (frequency-domain simulation). overall Position Controller system.
The Position Controller works as follows: A
WHY SIMULATE? Digital Command subsystem is used to generate a
Simulation is useful for many reasons. Perhaps series of user-programmable “position profile”
the most obvious use of simulation is to reduce commands, which the motor/load are expected to
the risk of unintended system behaviors, or even precisely track. The digitally-generated command
outright failures. This risk is reduced through drives a digital-to-analog (D/A) converter which
“virtual testing” using simulation technologies. produces an analog representation of the digital
Virtual testing is typically used in conjunction command.
with physical testing (on a physical prototype). The D/A output is then filtered, and used to
The problem with relying solely on physical command an analog servo loop, the purpose of
testing is that it is often too expensive, too time- which is to precisely control the position of an
consuming, and occurs too late in the design inertial load connected to the shaft of a motor.
process to allow for optimal design changes to be Each of these blocks will be explored in detail in
implemented. this paper.
Virtual testing, on the other hand, allows a
Digital Servo
system to be tested as it is being designed, before Command
actual hardware is built. It also allows access to
the innermost workings of a system, which can be Digital Servo/
D
difficult or even impossible to observe with Command 2 Motor/
physical prototypes. Additionally, virtual testing A Load
allows the impact of component tolerances on
overall system performance to be analyzed, which
is impractical to do with physical prototypes. Figure 1 – Position Controller
When employed during the beginning of the This type of servo positioning system is
design process, simulation provides an commonly employed in various applications in
Summing Junction
A mathematical description of an ideal summing
Figure 3 - Example switching waveform junction is also fairly intuitive. This behavior can
As shown in the figure, it takes quite a few be described as shown in Equation (2).
time steps to construct a single pulse in such a vout = K 1 * vin1 + K 2 * vin 2 (2)
system. A 20 KHz switching amplifier could
easily require more than 1,000,000 time steps for Note that optional gain factors (K1 and K2) have
a 1 second simulation! been included in the model equation. This allows
This is one of the reasons that a simplified either input to be optionally scaled, and also
model is desired. The important question is: “Can allows the model to be changed from a summing
reasonable simulation results be achieved with a junction (e.g. +K1 and +K2), to a differencing
simple gain block approach?” The short answer is junction (e.g. +K1 and –K2).
yes. Even if the actual power amplifier in the The addition of optional gain coefficients is a
system is going to be implemented as a switching recurring theme in many of the models presented
amplifier, the gain block representation is in this paper. This is not by accident. Generally
acceptable given the following two assumptions: speaking, models should be developed so that
they are re-usable. By simply adding user-
• The frequency of the switching amplifier is
adjustable gain coefficients at strategic locations
much greater than the bandwidth of the
control loop (true in the vast majority of in a model, the model becomes useful to a wider
designs) audience at negligible cost in terms of model
development time.
• Power consumption is not of great
concern in this phase of the design process Potentiometer
A potentiometer is a device that generates a
For the purposes of this paper, these are perfectly voltage level in proportion to a rotational angle.
reasonable assumptions in the early phases of the (For greater precision, optical encoders are often
overall design. Ultimately, the actual behavior of employed for this purpose). The behavior of a
the switching amplifier will be accounted for, at potentiometer can be expressed as shown in
which time the simple gain block model will be Equation (3).
replaced by a switching amplifier model.
Now that the scope of the initial power vout = K * anglein (3)
amplifier model has been determined, the next The potentiometer behavior is very similar to that
step is to identify a mathematical description that of the amplifier behavior shown in Equation (1).
Load (Inertia)
The load is a fairly critical system component
since it will likely represent one of the largest
time constants in the entire system. This will
directly influence the speed of the system. For this
design, the load will be represented as an inertia, Figure 5 - Motor as resistive load
the behavior of which is described in Equation
(9). The drawback to this model, of course, is that
it doesn’t take any motor dynamics into account.
dω In addition, this simplistic approach doesn’t even
torq = j * (9)
dt completely model the electrical portion of the
In essence, this equation defines how much torque motor, which includes winding inductance as well
will be required as the load is accelerated as winding resistance.
(acceleration is calculated as the derivative of the
Motor as resistive/inductive load
load angular velocity). Equation (9) depicts load
The resistive load motor model can be improved
torque as a function of (shaft) velocity (ω). The by representing it as a resistor in series with an
load torque can also be calculated as a function of inductor. This includes the electrical dynamics of
(shaft) position (θ). This formulation is given in the winding – i.e. the winding resistance and
Equation (10). inductance, as shown in Figure 6.
d 2θ
torq = j * 2 (10)
dt
This second formulation is used in the Servo
subsystem illustrated in Figure 2.
Note how “like-natured” ports are optionally The first line of this model architecture
declared on the same line. If this component was declares an architecture called “ideal.” This
modeled with a non-conserved modeling style, the architecture is declared for the entity called
ports would be declared as port quantities, rather “gain”.
than terminals. In that case, the ports would not As with entities, the model developer also
have across and through aspects. selects the names for architectures. For this
Ports can also be of type signal. These non- model, “ideal” was chosen as the architecture
conserved ports are used for digital connections. name since this is an idealized, high-level
Signal ports will be discussed in the Integrate implementation. “Behavioral” or “simple” could
Digital Command and Servo Subsystems phase of just as well have been chosen to denote this level
the design. of implementation.
Now that the model’s ports are defined, the The actual model equations(s) appear between
model must declare any parameters that will be the begin and end keywords, which indicate the
passed in externally. For the gain model, there is area where simultaneous equations and concurrent
only the gain parameter, K (referred to as a statements are located in the model (concurrent
generic in VHDL-AMS). This generic is statements will be discussed in the Integrate
accounted for as follows: Digital Command and Servo Subsystems phase).
The basic equation for the gain component given
entity gain is in Equation (13) can be implemented as follows:
generic (
K : real := 1.0 -- Model gain architecture ideal of gain is
); -- declarations
port ( begin
terminal input : electrical; vout == K * vin;
terminal output : electrical end architecture ideal ;
);
end entity gain;
In VHDL-AMS, the “==” sign indicates that
this equation is continuously evaluated during
Generic K is declared as type real, so it can be
simulation, and equality is maintained between
assigned any real number. In this case, it is given
the expressions on either side of the “==” sign at
a default value that will be used by the model if
all times.
the user does not specify a gain value when the
The next step is to declare all undeclared
objects used in the functional equation. In this
3 4
See Section 22.1 of [1] for a complete list of predefined Constant wp can also be assigned to a single element in a
attributes. real_vector using the following syntax: (0=>wp).
6
Thorough VHDL-AMS implementations for both D/A and
A/D converters are discussed in Chapter 8 of [1].