2015 3rd International Conference on Electric Power Equipment - Switching Technology (ICEPE-ST) Oct.
25-28, 2015 Busan, Korea
A Comparative Study on Electrical and Thermal
Stress Distribution across Fundamental Components
of Conventional and Superconducting Hybrid Type
HVDC Circuit Breakers
Umer Amir Khan, Jong-Geon Lee, Sung-Woo Lim,
Bang-Wook Lee
Department of Electronic System Engineering,
HVDC EPL Lab, Hanyang University,
Ansan, South Korea.
bangwook@hanyang.ac.kr
Abstract— Super grids are considered to be the technology of
the future that will allow transmission and trade of huge volumes
of electricity over long distances. HVDC is the preferred choice
for developing super grids as HVAC transmission of bulk power
over long distances is less efficient. However, the key obstacle in
developing HVDC super grids is the absence of HVDC circuit
breakers (DCCB) which can quickly detect and isolate the fault.
The huge electrical and thermal stresses subjected to DCCB
during DC current interruption are one of the primary
challenges in developing DCCB. Especially, IGBT valves in
hybrid DCCB are the most expensive and sensitive part and their
cost drastically increase with their maximum rating. This
research paper presents a comparative study on the electrical
and thermal stress distribution across IGBT valves of
conventional hybrid DCCB (CDCCB) and Superconducting
hybrid DCCB (SDCCB) during fault conditions. Realistic
CDCCB and SDCCB models were developed by considering the
characteristic values of commercially available IGBT module. To
create the electrical and thermal stress profiles, CDCCB and
SDCCB were placed in HVDC test bed model and transient
simulations were performed. The voltage distribution, current
distribution and energy dissipation profiles across IGBT valves
were developed for CDCCB and SDCCB. Comparative analysis
of the profiles showed that the SDCCB components were
subjected to relatively lower electrical and thermal stresses.
Keywords—HVDC Circuit Breaker (DCCB), Hybrid DCCB,
Superconducting DCCB, Superconducting Fault Current Limiter,
IGBT Valves.
I. INTRODUCTION
The annual increase of electric power demand all over the
globe has caused an increase in High Voltage Direct Current
(HVDC) projects and new HVDC projects are being
commissioned every year. Although most of the HVDC
projects are point to point transmission systems, the integration
of these point to point HVDC systems into Multi-terminal
HVDC grid configuration (MTDC) will lead to numerous
advantages. MTDC, also referred to as super grid, is the
technology of the future that will allow transmission of electric
This work was supported by the Human Resources Program in Energy
Technology of the Korea Institute of Energy Technology Evaluation and
Planning (KETEP), granted financial resource from the Ministry of Trade,
Industry & Energy, Republic of Korea. (20154030200730).
The research was also supported by LS Industrial Systems co., ltd.
978-1-4673-7414-9/15/$31.00 ©2015 IEEE
Young-Geun Kim, JungWook Sim
Power Equipment R&D Center
LSIS Co., Ltd.
Cheongju, Korea
youngk@lsis.biz
power from remote renewable resources to the power hungry
load centers and it will also enable the trade of bulk electric
power [1]-[3]. Unfortunately, the development of MTDC is
delayed up till now due to absence of HVDC circuit breaker
(DCCB) technology. With the latest developments in high
power and high voltage IGBT valves, hybrid DCCBs having
IGBT valves and mechanical parts have been developed and
lab tested [4]. However, implementation of the hybrid DCCB
in real HVDC network has still not been reported. This is
mainly due to the cost of IGBT valves which are subjected to
huge stresses in HVDC systems during fault interruption.
In MTDC, the DC fault current rises rapidly and its
magnitude is very large compared to AC network. Breaking
this huge DC fault current results in huge electrical and thermal
stresses subjected to DCCB and these stresses are one of the
primary challenges in developing DCCB [5]-[6]. IGBT valves
in hybrid DCCB are the most expensive and sensitive part and
their cost drastically increase with the increase in their
maximum rating. In our previous research works [7]-[8], we
have proposed a superconducting hybrid DCCB (SDCCB)
which limits the rising DC fault current and significantly
reduces the stress on SDCCB components.
In this research paper we have modelled the conventional
hybrid DCCB (CDCCB) and SDCCB models and performed a
comparative study on the electrical and thermal stresses
subjected to their IGBT valves. CDCCB and SDCCB were
placed in HVDC test bed model and transient simulations were
performed. The voltage distribution, current distribution and
energy dissipation profiles across IGBT valves for CDCCB and
SDCCB were developed. Comparative analyses of these
profiles showed that the SDCCB components were subjected to
relatively lower electrical and thermal stresses.
II. FAULT CURRENTS IN HVDC SYSTEMS
A. DC Fault Current Interruption Methods
AC circuit breakers interrupt AC fault current at its natural
zero crossing, but there is no zero point in DC fault current as
574

Fig. 1 Difference between AC and DC fault current.
(a) (b) (c)
Fig. 2 Waveforms for methods of HVDC fault current interruption in DC
switchgear: (a) Divergent current oscillation method (b) Inverse current
injection method (c) Inverse voltage generation method.
shown in Fig. 1. Therefore, DCCBs require an active method
for reducing the current to zero level before breaking the
circuit. Forcing the huge and rising DC fault current to zero in
HVDC systems require methods which are very different from
conventional AC circuit breakers [9]-[10].
The three methods commonly used to make zero for DC
fault current are shown in Fig. 2 and explained as follows [11]:
(1) Divergent current oscillation method in which the current
zero is made by magnifying the amplitude of the high
frequency oscillating DC fault current until it touches the zero
point as shown in Fig. 2 (a); (2) Inverse current injection
method creates current zero by superimposing a high frequency
inverse current on DC fault current by discharging a
precharged capacitor as shown in Fig. 2 (b); (3) Inverse voltage
generating method reduces the current to zero by making the
arc voltage higher than the source voltage as shown in Fig. 2
(c). The inverse voltage in circuit breaker ignites the parallel
connected surge arresters and the network energy is dissipated
in them resulting in reducing the DC fault current to zero. The
inverse voltage generated must be higher than the normal
HVDC line voltage. Inverse voltage generation method has
been successfully lab tested for interrupting the DC fault
current in CDCCB [4].
B. High Amplitude and Severity of DC Fault Current
In MTDC, DC fault current rises much more rapidly and it
has larger magnitude when compared with point to point
HVDC systems. This is due to multiple power sources and
decreased surge impedance in MTDC. Forcing a large DC fault
current to zero in short duration causes enormous voltage and
energy stresses for DCCB components [9]. IGBT valves in
hybrid DCCB are practically very difficult to develop due to
very large voltage rating, huge energy dissipation requirement,
enlarged size and enormous costs [12]. A fault current limiter
can suppress the large DC fault current in MTDC to breakable
values during response time of DCCB and significantly reduce
the current interruption stress on hybrid DCCB IGBT valves.
Current Limiting Ultrafast Disconnector Line Commutation
Reactor Switch (UDS) Switch (LCS)
a b
Residual I1 IT
Current Main DC Breaker (MCB)
Breaker (RCB)
I2
Surge Arrester Bank (SAB)
Fig. 3 Single line diagram of a conventional hybrid DCCB (HDCCB) as
proposed in [15].
C. Need for Current Limiting
During a fault in MTDC, all the nodes and their
corresponding DCCB experience large currents as normal
power flow is terminated and current rushes towards the fault
point [13]. At a particular node, it is not possible to identify the
faulty line along with the correct DCCB to trip, simply, on the
bases of current and voltage at that particular node. A delay is
required for the identification of the faulty line amongst
multiple HVDC lines connected with the node. The
identification of faulty line may require communication
between MTDC converter stations located at far distances [14].
During this delay, the fast rising DC fault current in MTDC
could rise to very large values. Fault current limiting would
prevent the increasing fault current to reach to unbreakable
values during the delay and reduce the fault current interruption
stress on DCCB components.
III. HVDC CIRCUIT BREAKER MODELS
A. Conventional Hybrid HVDC Circuit Breaker
A prior art CDCCB is shown in Fig. 3 and was proposed in
[15]. This model works on inverse voltage generation method
as explained in Section II.A. In Fig. 3, the Ultrafast
Disconnecter Switch (UDS) is a mechanical switch, Line
Commutation Switch (LCS) is a lower voltage rating IGBT
valve, Main Circuit Breaker (MCB) is a higher voltage rating
IGBT valve, and Residual Circuit Breaker (RCB) is a
conventional AC circuit breaker (ACCB). During normal
operation, UDS, LCS, and RCB are closed and they are
conducting the normal line current. When a DC fault occurs,
MCB is closed and the LCS is opened. Opening of the LCS
commutates the current to the parallel branch containing
MCB. As the current through LCS is decreased to negligible
value, UDS opens with minimum arc and isolates the LCS
from any voltage buildup across the CDCCB. Once the trip
signal is generated, the MCB opens resulting in large inverse
voltage buildup across the CDCCB which ignites the parallel
connected surge arrester bank and forces the DC fault current
to zero. Finally, RCB opens and isolate the HVDC line [15].
CDCCB has a current limiting reactor in series of the
normal current path as shown in Fig. 3. The current limiting in
575
 Ultrafast Disconnector Line Commutation
Switch (UDS) Switch (LCS)
a SFCL b
Residual I1 IT
Current Main DC Breaker (MCB)
Breaker (RCB)

I2

Surge Arrester Bank (SAB)

(a)

Fig. 4 Single line diagram of a superconducting hybrid DCCB (SDCCB) as

proposed in [7] and [8].

the CDCCB is done by pulse mode operation of the MCB by

controlling the voltage drop across the current limiting reactor
to zero [15]. Active current limiting, involving switching of
large IGBT valves, will lead to early failure of the IGBT valves
and it is the major limitation of the CDCCB. Furthermore, the
reactor energy will be discharged during the fault causing an
increased DC fault current [12]. Also, larger inductance in
HVDC network will affect the dynamic response of the system
during fast load shifting because the reactor inductance (b)
opposes any quick change in current [16]. Considering all these Fig. 5 DCCB models developed in Matlab/Simulink/Simpowersystem (a)
limitations, a SDCCB with passive current limiting was Conventional hybrid DCCB model (CDCCB) as proposed in [15], (b)
proposed in [7]-[8] and explained in the next section. Superconducting DCCB model (SDCCB) as proposed in [7].

B. Superconducting Hyrbid HVDC Circuit Breaker
Fig. 4 shows the proposed SDCCB which is modified
CDCCB of Fig. 3. Modifications include: (1) SFCL is placed in
series of main current path (I1); and (2) Series reactor has been
removed as it is not needed anymore for current limiting. The
SDCCB works as follows. After the DC fault, SFCL quenches
and limits the fault current. SDCCB do not interrupt current
instantaneously and the decision to trip SDCCB depends on:
(1) the absence of false triggers; (2) identifying the faulty line;
or (3) crossing the thermal limit of any of the SDCCB
components. Once the trip signal is given to SDCCB, the LCS
located in the main line opens and commutates the current to
the parallel line where DC current is forced to zero by a
combination of MCB IGBTs and surge arresters. This current
interruption method is similar to that of CDCCB [15].
IV. SIMULATION ANALYSIS
The modeling and simulation analysis of the proposed
DCCB models were done in Matlab / Simulink /
Simpowerystems. It was assumed that the DCCBs were
required to limit the fault current for 10 ms after the fault due
to the reasons explained in Section II. Transient simulations of
one DCCB model were done at a time. The fault was generated
at 60 ms and after the 10 ms delay the DCCB was given the
trip signals at 70 ms. After the trip signal, DCCBs interrupted
the DC fault current and isolated the HVDC line.
A. Design and Modeling of IGBT Valves
Fig. 5 shows the CDCCB and SDCCB models used for
simulation analysis. To calculate the energy dissipation across
the IGBT valves, it was critical to determine impedance values
of LCS and MCB valves. An IGBT valve is composed of a
number of series and parallel connected IGBT modules and
Fig. 6 (a) shows the simplified structure of an IGBT valve.
IGBT valve’s basic building block is a single IGBT module
whose maximum blocking voltage (VCES) and maximum peak
current (Icrm) determines critical ratings for an IGBT valve.
IGBT valve critical ratings are its maximum blocking
voltage (VB) and maximum peak current (Iv). In an IGBT
valve, the number of IGBT modules connected in series (Ns) is
determined by the VB and the number of parallel branches
(NBR) is determined by the Iv. NS and NBR can be calculated by
Ns = VB / VCES (1)
NBR = Iv / Icrm (2)
Let Zm be the impedance of single IGBT module in Fig. 6
(a). We can calculate the series impedance of a one branch (ZS)
of the IGBT valve by:
ZS = Ns × Zm (3)
Considering NBR, the total impedance of the valve (ZT) can
be calculated as:

576
 VB
1 Icrm NS Iv
IGBT IGBT
1 V CES

NBR IGBT IGBT

Total IGBTs = NS x NBR

(a) (b)
Fig. 6 (a) Simplified diagram of an IGBT valve with NBR parallel branches
and NS IGBT in a single branch, (b) Characteristic graph of IGBT during
conduction state [17].
TABLE I. IMPEDANCE CALCULATION OF DCCB IGBT VALVES
Valve VB IV NS NBR ZT
LCS 100 V 16 kA 1 7 1 mŸ
MCB 460 kV 40 kA 103 17 25mŸ
ZT = ZS / NBR (4)
During conduction, IGBT valve will dissipate energy across
itself (Evalve) and we can calculate this energy by:
Evalve = œ Iv2 ZT dt (5)
where Iv is the instantaneous valve current. Integration is done
from the start of the fault to the zero current formation of the
DC fault current.
For the DCCB models of Fig. 5, the IGBT valves
parameters were calculated by considering the specifications of
the commercially available IGBT module FZ1200R45KL3_B5
which is developed by Infineon [17]. The single IGBT module
has: VCES = 4.5 kV and Icrm = 2.4 kA. Fig 6 (b) shows the IGBT
characteristic curve between the saturation voltages across
IGBT module (VCE) during conduction state versus the current
flowing through it. Considering Icrm = 2.4 kA, we measured
VCE § 4.5 V. Thus we can calculate Zm by
Zm = VCE / Icrm (6)
and we calculated Zm= 1.875 mŸ.
Table IV shows the expected maximum blocking voltage
and fault current subjected to IGBT valves in Fig. 5 and these
values were used to calculate the impedance of IGBT valves.
Equations (1)-(5) were used to calculate the impedance values
of LCS and MCB IGBT valves and the estimated values are
given in Table IV.
B. Test Bed
A testing setup was developed to perform transient
simulations on the CDCCB and SDCCB models as shown in
Fig. 7. Table II summarizes the general features of the test bed
model. The test bed contains a two-level VSC-HVDC
converter arranged in symmetrical monopole configuration
[13]. Test bed Voltage = 250 kV, Load Current = 2 kA, Normal
Power Flow = 500 MW, and HVDC transmission line length =
100 km as shown in Fig. 7. DC fault was generated and it
results in a DC fault current with di/dt = 10 kA/ms.
After the DC fault in test bed, VSC-HVDC converter
station IGBTs were turned off within microseconds. However,
fault current continued to flow through the IGBT antiparallel
diodes which form an uncontrolled rectifier [5]. Similar to the
Fig. 7 Test bed model designed in Matlab/Simulink/Simpowersystems to
perform simulation analysis for SDCCB.
TABLE II. PARAMETERS OF HVDC TEST BED MODEL
Parameters Specification
VSC HVDC Type Monopolar / Two Level
MTDC Grid Voltage 250 kVdc
DC Fault Current di/dt 10 kA/ms
Normal Load Current 2 kA
Power Consumption 500 MW
AC System Voltage 200 kVrms
AC System Power Rating 2 GVA
AC System X/R 7
real HVDC systems, the DC fault current in the test bed is
composed of: (1) contribution from the AC network; (2) DC
link capacitor discharge current; and (3) discharging of the
transmission line [16].
V. RESULTS AND DISCUSSION
Fig. 8, Fig. 9 and Fig. 10 shows the current, voltage and
energy stress subjected to CDCCB and SDCCB IGBT valves
when applied in test bed model of Fig. 7. At 60 ms, DC fault is
generated and CDCCB immediately diverts the current to the
parallel MCB branch and waits for 10 ms. The current limiting
time is indicated as TLimit in Fig 8 and Fig. 9. At 70 ms the
CDCCB was triggered and the current was forced to zero. On
the contrary, after the DC fault, SDCCB did not immediately
divert the fault current to the parallel branch and SDCCB
SFCL limited the fault current for 10 ms. At 70 ms, SDCCB
diverted the current to the MCB branch where it was
interrupted and forced to zero.
A. Current Stress Subjected to IGBT Valves
Fig. 8 shows the current stress subjected to DCCBs and
their IGBT valves when applied in test bed model of Fig. 7.
Fig. 8 (a) shows the total current flowing through the DCCBs
during the fault. The presence of SFCL in SDCCB significantly
reduced the total current flowing through the SDCCB. Fig. 8
(b) shows the current through LCS valves. CDCCB LCS
conducted for a short duration but SDCCB LCS had to conduct
continuously during the current limiting duration. Therefore,
SDCCB LCS is subjected to larger current stress when
compared with CDCCB LCS. Fig 8 (c) shows the current
flowing through the MCB valve of the CDCCB and SDCCB. A
large DC fault current conduction stress was subjected to
CDCCB MCB during TLimit. Also, MCB had to break the huge
DC fault current which is only limited by the current limiting
reactor in CDCCB. On the contrary, SDCCB significantly
reduced the amplitude and the duration of DC fault current
flowing through the MCB. Moreover, SDCCB MCB had to
break a much smaller fault current which further reduces the

577
 IT for CDCCB IT for SDCCB VT for CDCCB VT for SDCCB
50 500

Total DCCB Voltage (kV)

DCCB Total Current (kA)

40 400

30 300

20 200

10 100

0 0
55 60 65 70 75 80 55 60 65 70 75 80
TLimit Time (ms) TLimit Time (ms)
(a) (a)
ILCS for CDCCB ILCS for SDCCB VLCS for CDCCB VLCS for SDCCB
20 60
LCS Valve Current (kA)

LCS Valve Voltage (kV)

50
15
40

10 30

20
5
10

0 0
55 60 65 70 75 80 55 60 65 70 75 80
TLimit Time (ms)
TLimit Time (ms)
(b) (b)
IMCB for CDCCB IMCB for SDCCB VMCB for CDCCB VMCB for SDCCB
50 500
MCB Valve Current (kA)

MCB Valve Voltage (kV)

40 400

30 300

20 200

10 100

0 0
55 60 65 70 75 80 55 60 65 70 75 80
TLimit Time (ms) TLimit Time (ms)
(c) (c)
Fig. 8 Current stresses for CDCCB and SDCCB (a) Total fault current Fig. 9 Voltage stresses for CDCCB and SDCCB (a) Total voltage buildup
flowing through the two DCCBs, (b) Fault current flowing through the across DCCBs, (b) Voltage buildup across the LCS valves, (c) Voltage
LCS valves, (c) Fault current flowing through the MCB valves. buildup across the MCB valves.

stress for MCB. Thus, SDCCB MCB valve will have smaller
current rating and consequently lesser number of IGBT parallel
branches in the MCB valve. This will significantly decrease the
size and cost of the MCB valve. Table III shows the percentage
change in fault current subjected to the two DCCBs and their
IGBT valves. The positive values of percentage change in
Table III indicate the increase in stress and the negative values
show the decrease in the stress.
B. Voltage Stress Subjected to IGBT Valves
Fig. 9 shows the voltage stress subjected to DCCBs and
their IGBT valves when applied in test bed model of Fig. 7.
Fig. 9 (a) shows the total voltage buildup across the DCCBs
during the fault current interruption. This voltage was
dependent on the activation voltage of the surge arrester bank
and it was not directly related with the amplitude of the DC
fault current. Fig. 9 (b) shows the voltage across the LCS
valve. LCS in both the DCCBs had small voltage drop which
was expected and explained in Section III.A. Fig 9 (c) shows
the voltage across the MCB valves of the CDCCB and
SDCCB. The maximum inverse voltage that will ignite the
surge arrester bank will appear across the MCBs of the
DCCBs. Also, for the SDCCB the SDCCB SFCL voltage drop
appeared across the SDCCB MCB during the TLimit duration as
shown in Fig. 9 (c). However, this voltage buildup is
unimportant as it is lower than the SDCCB MCB voltage rating
and also results in no power loss as SDCCB MCB is not
conducting. Table III shows the percentage change in the
voltage drop across the DCCB IGBT valves.

578
 CDCCB SDCCB
20
CDCCB SDCCB were performed. The voltage distribution, current distribution
6
and energy dissipation profiles across IGBT valves were
5
developed for CDCCB and SDCCB. In SDCCB, the largest

Energy Dissipation (MJ)

Energy Dissipation (kJ)

15
4 and the most expensive IGBT valve (MCB) of hybrid DCCB
3 10 was subjected to significantly lower electrical and thermal
2
stresses. This will significantly decrease the size and cost of the
5 MCB valve. However, there is a need to analyze the stresses
1
subjected to SFCL in SDCCB and it will be presented in our
0 0 future research work.
LCS Valve MCB Valve
(a) (b)

Fig. 10 Energy stresses on IGBT valves in CDCCB and SDCCB (a) Energy
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