Introduction to VLSI and System-on-Chip Design

Combinational Circuit Design

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science
National Chiao Tung University
Taiwan, R.O.C.
Fall, 2009

ldvan@cs.nctu.edu.tw

http://www.cs.nctu.edu.tw/~ldvan/
 Introduction to VLSI and System-on-Chip Design

Outlines Lecture 5

Introduction
Static CMOS Circuits
„ Static Complementary Logic Gates
Š Asymmetric Gate
Š Skewed Gate
Š P/N ratios
„ Ratioed Circuits
Š Pseudo-nMOS Gates
Š Differential Cascode Voltage Switch Logic (DCVSL)
Dynamic CMOS Circuits
„ Domino Logic
Transmission Gate
Conclusion

Lan-Da Van VLSI-05-2

 Introduction to VLSI and System-on-Chip Design

Universal/Complete Lecture 5

A set of functions f1, f2, ..fn is universal/complete iff

every Boolean function can be generated by a
combination of the functions.
{AND, OR, Inverter} is universal/complete. However,
{AND, OR} is not universal/complete.
AOI = and/or/invert; OAI = or/and/invert.
NAND is a universal/complete gate; NOR is a
universal/complete gate. How to prove??
Transmission gates are not universal/complete gate.
If your set of logic gates is not universal/complete,
you can’t design arbitrary logic.

Lan-Da Van VLSI-05-3

 Introduction to VLSI and System-on-Chip Design

Logical Effort Factor Lecture 5

What makes a circuit fast?

„ I=CdV/dt => t pd ∞(C / I )∆V
„ Low capacitance
„ High current
„ Small swing
Logical effort is proportional to C/I
pMOS are the enemy!!
„ High capacitance for a given current
Can we take the pMOS capacitance off the
input?
Various circuit families try to do this…

Lan-Da Van VLSI-05-4

 Introduction to VLSI and System-on-Chip Design

Outlines Lecture 5

Introduction
Static CMOS Circuits
„ Static Complementary Logic Gates
Š Asymmetric Gate
Š Skewed Gate
Š P/N ratios
„ Ratioed Circuits
Š Pseudo-nMOS Gates
Š Differential Cascode Voltage Switch Logic (DCVSL)
Dynamic CMOS Circuits
„ Domino Logic
Transmission Gate
Conclusion

Lan-Da Van VLSI-05-5

 Introduction to VLSI and System-on-Chip Design

Static Complementary Gates Lecture 5

Static: do not rely on the stored charge.

Complementary: have complementary pullup (p-type)
and pulldown (n-type) networks.
Simple, effective, reliable; hence ubiquitous.
VDD

pullup
network
inputs out
pulldown
network
VSS

Lan-Da Van VLSI-05-6

 Introduction to VLSI and System-on-Chip Design

Pullup/Pulldown Network Design

Lecture 5

Pullup and pulldown networks are duals.

To design one gate, first design one network, and
then compute dual to get other network.
Design Steps
„ Step 1: Formulate Boolean function in fully complement form
„ Step 2: Implement the fully complement form using nMOS
(i.e., pull-down network).
„ Step 3: Complement the pull-down network to obtain dual
network (i.e., pull-up network) using pMOS.

Lan-Da Van VLSI-05-7

 Introduction to VLSI and System-on-Chip Design

NAND Gate Lecture 5

Lan-Da Van VLSI-05-8

 Introduction to VLSI and System-on-Chip Design

NOR Gate Lecture 5

Lan-Da Van VLSI-05-9

 Introduction to VLSI and System-on-Chip Design

Compound Gate Lecture 5

An and-or-invert-21 (AOI-21) gate: Dual Network

out = [ab+c]

symbol invert
circuit

or

and

Network
Lan-Da Van VLSI-05-10
 Introduction to VLSI and System-on-Chip Design

Complex CMOS Gate Lecture 5

VDD

B
A
C

D
OUT = D + A• (B+C)
A
D
B C

Lan-Da Van VLSI-05-11

 Introduction to VLSI and System-on-Chip Design

Logical Effort of Compound

Gate Lecture 5

unit inverter AOI21 AOI22 Complex AOI

Y=A Y = A B+C Y = A B+C D Y = A (B + C) + D E

D
A A E
Y
B B A
A Y Y Y
C C B
D C

A 4 B 4 A 4 B 4 B 6
2 C 4 C 4 D 4 C 6 A 3
A Y Y Y
1 A 2 A 2 C 2 D 6 E 6
C 1 Y
B 2 B 2 D 2 E 2 A 2
D 2 B 2 C 2

gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3

p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3
gC = 5/3 gC = 6/3 gC = 8/3
p = 7/3 gD = 6/3 gD = 8/3
p = 12/3 gE = 8/3
p = 16/3
Lan-Da Van VLSI-05-12
 Introduction to VLSI and System-on-Chip Design

Example: Delay Calculation

(1/3) Lecture 5

Calculate the minimum delay of the function F=AB+CD

using the following circuits. Each input has a maximum
of 20 ut of transistor width. The output must drive a load
equivalent to 100 ut of transistor width. Estimate the
transistor sizes to achieve this delay.

H = 100 / 20 = 5
B=1
N=2

Lan-Da Van VLSI-05-13

 Introduction to VLSI and System-on-Chip Design

NAND Solution (2/3) Lecture 5

P = 2+2 = 4
G = (4 / 3) ⋅ (4 / 3) = 16 / 9
F = GBH = (16 / 9) ⋅1 ⋅ 5 = 80 / 9
ˆf = N F = 3.0

D = Nfˆ + P = 10

Lan-Da Van VLSI-05-14

 Introduction to VLSI and System-on-Chip Design

Compound Solution (3/3) Lecture 5

P = 12 / 3 + 1 = 5
G = (6 / 3) ⋅ (1) = 2
F = GBH = 2 ⋅1 ⋅ 5 = 10
ˆf = N F = 3.2

D = Nfˆ + P = 11.4

Lan-Da Van VLSI-05-15

 Introduction to VLSI and System-on-Chip Design

Example: Width Calculation

(1/2) Lecture 5

Annotate your designs with transistor sizes

that achieve this delay.
p1

n1 p2

p1 n2

n1

Cout ,i ⋅ g i Cout ,i ⋅ g i
Cin,i = = 44 Cin,i = = 31
fˆ fˆ
Lan-Da Van VLSI-05-16
 Introduction to VLSI and System-on-Chip Design

Example: Width Calculation

(2/2) Lecture 5

Annotate your designs with transistor sizes

that achieve this delay.

Lan-Da Van VLSI-05-17

 Introduction to VLSI and System-on-Chip Design

Symmetric Gate Lecture 5

Our parasitic delay model was too simple

„ Calculate parasitic delay for Y falling
If input A is critical….
If input B is critical….

Lan-Da Van VLSI-05-18

 Introduction to VLSI and System-on-Chip Design

Asymmetric Gates Lecture 5

Asymmetric gates favor one input over another

Ex: suppose input A of a NAND gate is most critical
„ Use smaller transistor on A (less capacitance)
„ Boost size of noncritical input
„ So total resistance is same
gA = 10/9
greset = 2
gavg = (gA + greset)/2 = 14/9

Asymmetric gate approaches g = 1 on critical input

But total logical effort goes up

Lan-Da Van VLSI-05-19

 Introduction to VLSI and System-on-Chip Design

Skew Definition Lecture 5

Skewed gates favor one edge over another

Lan-Da Van VLSI-05-20
 Introduction to VLSI and System-on-Chip Design

Skewed Gates Lecture 5

Skewed gates favor one edge over another

Ex: suppose rising output of inverter is most critical
„ Downsize noncritical nMOS transistor

Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that edge.
„ gu = 2.5 / 3 = 5/6
„ gd = 2.5 / 1.5 = 5/3

Lan-Da Van VLSI-05-21

 Introduction to VLSI and System-on-Chip Design

Logical Effort for Skew Gate Lecture 5

Def: Logical effort of a skewed gate for a particular

transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed inverter
delivering the same output current for the same
transition.
Skewed gates reduce size of noncritical transistors
„ HI-skew gates favor rising output (small nMOS)
„ LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction; but
larger for the other direction

Lan-Da Van VLSI-05-22

 Introduction to VLSI and System-on-Chip Design

Logical Effort of Skewed Gates Lecture 5

2 2 B 4
Y
2 A 4
A 2
A Y Y
1 gu = 1 B 2 gu = 4/3 1 1 gu = 5/3
gd = 1 gd = 4/3 gd = 5/3
gavg = 1 gavg = 4/3 gavg = 5/3

2 2 B 4
Y
2 A 4
A 1
A Y Y
1/2 gu = 5/6 B 1 gu = 1 1/2 1/2 gu = 3/2
gd = 5/3 gd = 2 gd = 3
gavg = 5/4 gavg = 3/2 gavg = 9/4
1 1 B 2
Y
1 A 2
A 2
A Y Y
1 gu = 4/3 B 2 gu = 2 1 1 gu = 2
gd = 2/3 gd = 1 gd = 1
gavg = 1 gavg = 3/2 gavg = 3/2

Lan-Da Van VLSI-05-23

 Introduction to VLSI and System-on-Chip Design

Best P/N Ratio Lecture 5

Prove that the P/N ratio that gives lowest average delay in
a logic gate is the square root of the ratio that gives equal
rise and fall delays.
Sol: For inverter, we have selected P/N ratio (i.e, k) for unit
rise and fall resistance.
„ Using logical effort => tpdf = (P+1)(1/(I+k))

„ Using logical effort => tpdr = (P+1)(1/(P+P/k))

„ tpd = (P+1)(1+k/P)/(2x(1+k)) = (P + 1 + k + k/P)/)/

(2x(1+k))
„ Differentiate tpd w.r.t. P

„ Least delay is P = k
1/2

Ref. CKT
Lan-Da Van VLSI-05-24
 Introduction to VLSI and System-on-Chip Design

P/N Ratios Lecture 5

In general, best P/N ratio is sqrt of that giving

equal delay.
„ Only improves average delay slightly for inverters
„ But significantly decreases area and power

Lan-Da Van VLSI-05-25

 Introduction to VLSI and System-on-Chip Design

Pseudo-nMOS Lecture 5

In the old days, nMOS processes had no pMOS

„ Instead, use pull-up transistor that is always ON
In CMOS, use a pMOS that is always ON
„ Ratio issue
„ Make pMOS about ¼ effective strength of pulldown network
1.8

1.5

Weak Pull-up 1.2

ds P = 24
Vout 0.9
out
0.6
P = 14

Strong
in 0.3
P=4

Pull-down 0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin

Lan-Da Van VLSI-05-26

 Introduction to VLSI and System-on-Chip Design

Pseudo-nMOS Characteristics Lecture 5

Logic 1 output is always at VDD.

Logic 0 output is above VSS.
„ VOL = 0.25 (VDD - VSS) is one plausible choice.
Consumes static power.
Has much smaller pullup network than static gate.
Asymmetrical response.
Pullup time is longer than pulldown time.

Lan-Da Van VLSI-05-27

 Introduction to VLSI and System-on-Chip Design

Pseudo-nMOS NAND gate Lecture 5

VDD

GND

Lan-Da Van VLSI-05-28

 Introduction to VLSI and System-on-Chip Design

Logical Effort of Pseudo-nMOS

Gates Lecture 5

Design for unit current on output

to compare with unit inverter.
pMOS fights nMOS

Lan-Da Van VLSI-05-29

 Introduction to VLSI and System-on-Chip Design

Pseudo-nMOS Design Lecture 5

Ex: Design a k-input AND gate using pseudo-nMOS.

Estimate the delay driving a fanout of H

G = 1 * 8/9 = 8/9
k
F = GBH = 8H/9
P = 1 + (4+8k)/9 = (8k+13)/9
N=2
4 2 H 8k + 13
1/N
D = NF + P = +
3 9

Lan-Da Van VLSI-05-30

 Introduction to VLSI and System-on-Chip Design

Pseudo-nMOS Power Lecture 5

Pseudo-nMOS draws power whenever Y = 0

„ Called static power P = I•VDD

„ A few mA / gate * 1M gates would be a problem

Use pseudo-nMOS sparingly for wide NORs

Turn off pMOS when not in use

Lan-Da Van VLSI-05-31

 Introduction to VLSI and System-on-Chip Design

DCVS Logic Operation Lecture 5

DCVSL = differential cascode voltage switch logic.

Static logic—consumes no static power.
Uses latch to compute output quickly.
Exactly one of true/complement pulldown networks
will complete a path to the power supply. (i.e.,
requires true/complement inputs, produces
true/complement outputs.)
Pulldown network will lower output voltage, turning on
other p-type, which also turns off p-type for node
which is going down.

Lan-Da Van VLSI-05-32

 Introduction to VLSI and System-on-Chip Design

DCVS Structure Lecture 5

Lan-Da Van VLSI-05-33

 Introduction to VLSI and System-on-Chip Design

Example: DCVSL Lecture 5

Lan-Da Van VLSI-05-34

 Introduction to VLSI and System-on-Chip Design

Outlines Lecture 5

Introduction
Static CMOS Circuits
„ Static Complementary Logic Gates
Š Asymmetric Gate
Š Skewed Gate
Š P/N ratios
„ Ratioed Circuits
Š Pseudo-nMOS Gates
Š Differential Cascode Voltage Switch Logic (DCVSL)
Dynamic CMOS Circuits
„ Domino Logic
Transmission Gate
Conclusion

Lan-Da Van VLSI-05-35

 Introduction to VLSI and System-on-Chip Design

Dynamic Logic Operation Lecture 5

Uses precharge clock to compute output in two phases:

„ Controlled by clock .
„ Precharge: p-type pullup precharges the storage node; inverter
ensures that output goes low.
„ Evaluate: storage node may be pulled down, so output goes up.
Output inverter is needed for two reasons:
„ make sure that outputs start low, go high so that domino output
can be connected to another domino gate (monotonic input rising)
„ protects storage node from outside influence.

Lan-Da Van VLSI-05-36

 Introduction to VLSI and System-on-Chip Design

Comparison of Three Gates Lecture 5

Dynamic gates uses a clocked pMOS pullup

Two modes: precharge and evaluate

gSTATIC=1 gPSEUDO=8/9 gDYNAMIC=1/3

Lan-Da Van VLSI-05-37

 Introduction to VLSI and System-on-Chip Design

Logical Effort of Dynamic Gates Lecture 5

1
Y
1 1
A 2
Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

1
Y
1 1
A 3
Y Y
A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

Lan-Da Van VLSI-05-38

 Introduction to VLSI and System-on-Chip Design

Dynamic Effect with Monotonicity Lecture 5

Gate outputs fall in sequence:

gate 1 gate 2 gate 3

Dynamic gates require monotonically rising inputs (A)

during evaluation
„ 0 -> 0
„ 0 -> 1
„ 1 -> 1
„ But not 1 -> 0

Lan-Da Van VLSI-05-39

 Introduction to VLSI and System-on-Chip Design

Monotonicity Woes Lecture 5

But dynamic gates produce monotonically falling

outputs during evaluation
Illegal for one dynamic gate to drive another!

Lan-Da Van VLSI-05-40

 Introduction to VLSI and System-on-Chip Design

Domino Gates (1/2) Lecture 5

Lan-Da Van VLSI-05-41

 Introduction to VLSI and System-on-Chip Design

Domino Gates (2/2) Lecture 5

Follow dynamic stage with inverting static gate

„ Dynamic / static pair is called domino gate
„ Produces monotonic outputs

domino AND

W X Y Z
A
B C

dynamic static
NAND inverter

Lan-Da Van VLSI-05-42

 Introduction to VLSI and System-on-Chip Design

Dual-Rail Domino Lecture 5

Domino only performs noninverting functions:

„ AND, OR but not NAND, NOR, or XOR
Dual-rail domino solves this problem
„ Takes true and complementary inputs
„ Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged Y_l Y_h

0 1 ‘0’ inputs
f f
1 0 ‘1’
1 1 invalid

Lan-Da Van VLSI-05-43

 Introduction to VLSI and System-on-Chip Design

Example: AND/NAND Lecture 5

Given A_h, A_l, B_h, B_l

Compute Y_h = A * B, Y_l = ~(A * B)
Pulldown networks are conduction complements

Lan-Da Van VLSI-05-44

 Introduction to VLSI and System-on-Chip Design

Example: XOR/XNOR Lecture 5

Sometimes possible to share transistors

Y_l Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h

Lan-Da Van VLSI-05-45

 Introduction to VLSI and System-on-Chip Design

Leakage Lecture 5

Dynamic node floats high during evaluation

„ Transistors are leaky (IOFF ≠ 0)
„ Dynamic value will leak away over time
„ Formerly miliseconds, now nanoseconds!
Use keeper to hold dynamic node
„ Must be weak enough not to fight evaluation

Make Sable state but

power still lose…

Lan-Da Van VLSI-05-46

 Introduction to VLSI and System-on-Chip Design

Charge Sharing Lecture 5

Dynamic gates suffer from charge sharing

A
Y
Y

x Charge sharing noise

CY
Vx = VY = VDD
C x + CY
Lan-Da Van VLSI-05-47
 Introduction to VLSI and System-on-Chip Design

Domino Summary Lecture 5

Domino logic is attractive for high-speed circuits

„ 1.5 – 2x faster than static CMOS
„ But many challenges:
Š Monotonicity
Š Leakage
Š Charge sharing
Š Noise
Widely used in high-performance microprocessors

Lan-Da Van VLSI-05-48

 Introduction to VLSI and System-on-Chip Design

Comparison of Circuit Families Lecture 5

Lan-Da Van VLSI-05-49

 Introduction to VLSI and System-on-Chip Design

Outlines Lecture 5

Introduction: Combinational Logic Functions

Static CMOS Circuits
„ Static Complementary Logic Gates
Š Asymmetric Gate
Š Skewed Gate
Š P/N ratios
„ Ratioed Circuits
Š Pseudo-nMOS Gates
Š Cascode Voltage Switch Logic
Dynamic CMOS Circuits
„ Domino Logic
Transmission Gate
Conclusion

Lan-Da Van VLSI-05-50

 Introduction to VLSI and System-on-Chip Design

Switch Logic Lecture 5

Can implement Boolean formulas as networks of

switches.
Can build switches from MOS transistors—
transmission gates.
Transmission gates do not amplify but have smaller
layouts.

Lan-Da Van VLSI-05-51

 Introduction to VLSI and System-on-Chip Design

Boolean Functions and Switches Lecture 5

Switch network inputs may be connected to power supply

or logic signals.
If switch network output is not connected to power supply
through switch path, output will float.
Pseudo-AND Pseudo-OR

b’

a
b ab’ + a’b

a’ Lan-Da Van VLSI-05-52

 Introduction to VLSI and System-on-Chip Design

Switch Multiplexer Lecture 5

Lan-Da Van VLSI-05-53

 Introduction to VLSI and System-on-Chip Design

Pass Transistor Circuits Lecture 5

Use pass transistors like switches to do logic

Inputs drive diffusion terminals as well as gates
CMOS + Transmission Gates:
„ 2-input multiplexer
„ Gates should be restoring

Lan-Da Van VLSI-05-54

 Introduction to VLSI and System-on-Chip Design

Behavior of n-type Switch Lecture 5

n-type switch has source-drain voltage drop when

conducting:
„ conducts logic 0 perfectly;
„ introduces threshold drop into logic 1.
Voltage drop causes next stage to be turned on
weakly.

VDD VDD VDD - Vt

VDD - Vt

VDD

VDD
Lan-Da Van VLSI-05-55
 Introduction to VLSI and System-on-Chip Design

Behavior of Complementary
Switch Lecture 5

Complementary switch products full-supply voltages

for both logic 0 and logic 1:
„ n-type transistor conducts logic 0;
„ p-type transistor conducts logic 1.
Has two source/drain areas compared to one for
inverter.

Lan-Da Van VLSI-05-56

 Introduction to VLSI and System-on-Chip Design

Charge Sharing Lecture 5

Interior nodes in a switch network may not be driven.

Charge can accumulate on small parasitic
capacitances.
Shared charge can produce erroneous output values.
At undriven nodes, charge is divided according to
capacitance ratio.

Lan-Da Van VLSI-05-57

 Introduction to VLSI and System-on-Chip Design

Example: Charge Sharing Lecture 5

Long chains of switches have intermediate nodes

which may be disconnected from power supplies.

Cia Cab Cbc

Lan-Da Van VLSI-05-58

 Introduction to VLSI and System-on-Chip Design

Charge Over Time Lecture 5

Time i Cia a Cab b Cbc c C

0 1 1 1 1 1 1 1 1

1 0 0 1 0 0 1 0 1

2 0 0 0 1/2 1 1/2 0 1

3 0 0 0 1/2 0 3/4 1 3/4

4 0 0 1 0 0 3/4 0 3/4

5 0 0 0 3/8 1 3/8 0 3/4

Make sure that for every input combination, there is a

path from the power supply to the output.

Lan-Da Van VLSI-05-59

 Introduction to VLSI and System-on-Chip Design

Conclusions Lecture 5

You should learn in depth about the following

topics:
„ Static CMOS Circuits
„ Dynamic CMOS Circuits
„ Transmission Gates

Lan-Da Van VLSI-05-60