Department Electrical, Electronic and Computer Engineering

ERS 220 Digital Systems

Laboratory 3 Guidelines
October 2023

Ping-Pong Game
1. Introduction
This assignment is completed in a group of 3 to 4 persons – remember that smaller groups require
explicit permission to do so. In this laboratory exercise a ping-pong game will be designed using a
finite state machine (FSM) and a controller hardware architecture. The game must be implemented
and demonstrated with a discrete circuit and on the DE0 FPGA board. Figure 1 illustrates what the
game setup should look like.

Figure 1. LED Ping-Pong game setup illustration

The game setup has 8 LEDs flashing in sequence, emulating the movement of a ping-pong ball. The
purpose of the game is to bounce the ball back by pressing a return button when the ball has reached
the last LED in the sequence.

In the basic game, the default start is an automatic serve at the right with the ball moving left from
RLAMP to LLAMP. When the ball reaches LLAMP, a press and hold of the LPB button will hold
the ball at LLAMP till it is bounced back by releasing LPB. The ball will then move from LLAMP
to RLAMP and must be returned by using button RPB, with the same requirements as for LPB.

The game ends when a ball is missed. The ball is missed by pressing the LPB button when the LLAMP
is not lit. Similarly, the ball is missed when RPB is pressed when RLAMP is not lit. A new game
starts with the ball starting from RLAMP in another automatic serve.

2. Assignment
This is a group assignment. Your Lab2 group may continue to work together, but it is allowed that
groups are reconstituted. The Lab 2 groups are copied to the Lab 3 demonstration assessment on the
JAMS, but self-enrolment is open. Partition the work in such a way that all demonstrations can be
accomplished.

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2.1. Fallback game
• The fallback assignment is a simplified unidirectional version of the basic ping-pong game.
There is only one return button, LPB. After a successful bounce from LPB, the ball moves
from LLAMP to RLAMP and the game ends.

2.2. Full game

• The full assignment requires the design of the basic bidirectional game.
• Implement an FPGA mode where the ball direction is automatically reversed on either side
when no button is pressed (automatic alternating serve). An automatic direction reverse then
creates a continuous game with no missed balls. A DIP-switch can be used to select the mode.

2.3. Bonus game

For the FPGA implementation:
• Implement a two-player mode of the bidirectional game with manual serve
• Use DIP-switches to set the frequency of the game clock (4 values)
• Add a counter for the number of consecutive bounces in a rally
• Add a display (LEDs or 7-segment) showing the game frequency and the rally tally (separate
displays or on a single one with time multiplexing)
• You may also reuse your Lab2 best-of-three implementation to keep track of the players’
scores and determine a winner

3. Technical description
The partial state diagram in Figure 2 may be modified to suit the game. The diagram is not complete
and is intended as a starting point only.

Figure 2. Incomplete starting point state diagram for ping-pong game

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3.1. Considerations
• It may be possible to simplify the state diagram in Figure 2 to four states:
− Stopping on the left hand side (STOPL)
− Moving from right to left (RUNR)
− Moving from left to right (RUNL)
− Stopping on the right hand side (STOPR)
• Note that a minimum of four outputs will be required to solve this problem - three to indicate
the specific LED that must be lit, and the last one to indicate the motion direction of the ball.
• Ignore the button presses when an incorrect return (LPB or RPB) button is pressed or when
both return buttons are pressed simultaneously. You may also propose different behaviour.
• How you design the circuit is entirely up to you. However, the game functionality should be
as described in Section 1.
− Use prescribed components - no PICs (or any microprocessor).
− You may choose which I/O resources to use (discrete or on the DE10-Lite board).
− Justify your choice of clock frequency. Name your controller clock CK. You may use
any clock signal source: derived from your FPGA, a function generator, your own
Lab2 ring oscillator, or any other oscillator circuit you want to (if you want to try
another useful component, look at a 555 timer chip).

4. Deliverables
4.1. Functioning discrete circuit
The ping-pong game must be designed and built using the prescribed SSI chips. The technical
arrangements are also similar to those of Lab2.

4.2. Functioning FPGA implementation

You are expected to design and implement the ping-pong game on the DE10-Lite FPGA using
VHDL. Use the top entity name “lab3” and port names as provided in the assignment description
section. Name the clock to your controller CK. For any other ports that are not named, you may
choose arbitrary names.

4.3. Hardware videos

You are required to make videos of your hardware during operation for both the discrete and FPGA
implementations. These videos must be uploaded to the JAMS before the start of the demonstration
evaluation session. All the administrative requirements defined for Lab2 hold.

4.4. Lab book

As for Lab1 and Lab2 (and for all the EECE modules), individual lab books must be used to
continually keep record of your activities for the Lab 3 assignment. Individual lab books must be
available for evaluation during the demonstration.

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4.5. Reporting
Individual lab books must be submitted to the JAMS on the day of the demonstration evaluation
session. The format must follow the EECE and ERS220 guidelines for lab books, but ensure that you
explicitly address the following topics (indicated with clear headings):
• Introduction
• Design outputs
− Clock frequency
− Detailed state diagram
− State encoding
− Complete discrete (hierarchical) circuit diagram
− Complete VHDL block diagram (and upload code and Quartus files)
• Hardware physical setup hierarchy - drawn diagram(s) or photograph(s)
• Conclusions
• References

5. Demonstration
The functional discrete circuit, as well as the FPGA implementation, must be demonstrated at the
practical demo session. It is compulsory to use the bench power supply for the demonstration of your
discrete circuit. The scheduled day for the evaluation of Lab 3 demonstrations can be found in the
module calendar. Your group will be assigned a demonstration time slot and a lab bench. The
schedule will be made available one day ahead of the demo date. Please be ready to demo 15 minutes
prior to your time slot.