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MVP 6100 - 50 1Z306 1000 - 10
MVP 6100 - 50 1Z306 1000 - 10
High Performance
9th Generation Intel® Xeon®/Core™ i7/i5/i3 &
8th Gen Celeron® Processor-Based
Fanless Expandable Computer
MVP-6120/MVP-6140
User’s Manual
Revision History
Revision Release Date Description of Change(s)
1.0 Jan.21, 2020 Initial release
ii
MVP-6100
Preface
Copyright © 2020 ADLINK Technology Inc.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, spe-
cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsi-
bility to global environmental preservation
through compliance with the European Union's
Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental pro-
tection is a top priority for ADLINK. We have
enforced measures to ensure that our products,
manufacturing processes, components, and raw
materials have as little impact on the environment as possible.
When products are at their end of life, our customers are encour-
aged to dispose of them in accordance with the product disposal
and/or recovery programs prescribed by their nation or company.
Battery Labels (for products with battery)
ᘄ㟁ụㄳᅇᨲ
Preface iii
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iv Preface
MVP-6100
Table of Contents
Preface .................................................................................... iii
1 Introduction ........................................................................ 1
1.1 Overview.............................................................................. 1
1.2 Features............................................................................... 1
1.3 Packing List ......................................................................... 2
1.4 Optional Accessories ........................................................... 2
2 Specifications ..................................................................... 3
2.1 MVP-612X/MVP-614X/MVP-612A/MVP-614A .................... 3
2.2 MVP-6121/MVP-6141/MVP-6122/MVP-6142...................... 5
2.3 MVP-6123/MVP-6143/MVP-6124/MVP-6144...................... 7
2.4 MVP-6100 Functional Block Diagram.................................. 9
2.5 Display Options.................................................................. 10
2.6 Mechanical Dimensions..................................................... 11
3 System Layout.................................................................. 17
3.1 Front Panel ........................................................................ 17
3.2 Internal I/O Connectors...................................................... 29
Table of Contents v
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vi Table of Contents
MVP-6100
List of Tables
Table 2-1: Max. Available Resolution Display Configuration ..... 10
Table 3-1: Front Panel I/O Legend ............................................ 17
Table 3-2: LED Indicators .......................................................... 18
Table 3-3: DisplayPort Pin Definition ......................................... 19
Table 3-4: Applicable Cable Types............................................ 19
Table 3-5: Digital Input/Output Connector Pin Definition ........... 20
Table 3-6: DVI-D Connector Pin Definition ................................ 22
Table 3-7: VGA Connector Pin Definition .................................. 23
Table 3-8: Ethernet Port Pin Definition ..................................... 25
Table 3-9: Active/Link LED Indicators........................................ 25
Table 3-10: Speed LED Indicators............................................... 25
Table 3-11: DC Power Input Pin Definition .................................. 26
Table 3-12: D-Sub 9-pin Signal Function of COM Ports.............. 27
Table 3-13: Mainboard Connector Legend .................................. 30
Table 3-14: 2-slot Backplane Board Connector Legend.............. 31
Table 3-15: 4-slot Backplane Board Connector Legend.............. 32
Table 3-16: GPS Module Power Header Pin Definition ............... 33
Table 3-17: 12V Fan Connector Pin Definition ............................ 34
Table 3-18: PWR/RESET Header Pin Definition ......................... 35
Table 3-19: 12V Power Pin Definition.......................................... 35
Table A-1: Power Consumption ................................................. 41
List of Figures
Figure 2-1: MVP-6120 Front View.................................................... 11
Figure 2-2: MVP-6140 Front View.................................................... 12
Figure 2-3: MVP-6120/6140 Left Side View..................................... 13
Figure 2-4: MVP-6120/6140 Right Side View .................................. 14
Figure 2-5: MVP-6120/6140 Top View (incl. wall-mount brackets) .. 15
Figure 3-1: Front Panel I/O .............................................................. 17
Figure 3-2: DisplayPort Connector Pin Definition............................. 19
Figure 3-3: Digital I/O Connector Pin Definition ............................... 20
Figure 3-4: Digital Input Circuit......................................................... 21
Figure 3-5: Digital Output Circuit...................................................... 21
Figure 3-6: DVI-D Connector Pin Definition ..................................... 22
Figure 3-7: VGA Connector Pin Definition ....................................... 23
Figure 3-8: Ethernet Port and LEDs................................................. 25
Figure 3-9: DC Power Input ............................................................. 26
Figure 3-10: COM Port Pin Definition................................................. 27
Figure 3-11: CFast Host Slot.............................................................. 28
Figure 3-12: Mainboard Connectors .................................................. 29
Figure 3-13: 2-slot Backplane Board Connectors .............................. 31
Figure 3-14: 4-slot Backplane Board Connectors .............................. 32
Figure 3-15: GPS Module Power Header Pin Definition .................... 33
Figure 3-16: 12V Fan Connector Pin Definition ................................. 34
Figure 3-17: Clear CMOS Jumper Setting ......................................... 34
Figure 3-18: PWR/RESET Header Pin Definition .............................. 35
Figure 3-19: 12V Power Pin Definition ............................................... 35
List of Figures ix
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x List of Figures
MVP-6100
1 Introduction
1.1 Overview
1.2 Features
Introduction 1
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X AC/DC Adapter
Z 220W (P/N: 31-62149-0000)
Z 280W (P/N: 91-95263-0010)
2 Introduction
MVP-6100
2 Specifications
2.1 MVP-612X/MVP-614X/MVP-612A/MVP-614A
Specifications 3
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4 Specifications
MVP-6100
2.2 MVP-6121/MVP-6141/MVP-6122/MVP-6142
Specifications 5
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6 Specifications
MVP-6100
2.3 MVP-6123/MVP-6143/MVP-6124/MVP-6144
Specifications 7
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8 Specifications
MVP-6100
DMI
Intel PHY PCIe PCIe x4 (C 246 support) BP
RJ45 CN I219
PCIe x4 (C 246 support) Board
Intel LAN PCIe PCIe x1
RJ45 CN I211
SATA x2 (C 246 support)
Intel LAN PCIe USB 2.0 for dongle
RJ45 CN I211
SMBus
M.2 CN PCIe x1 or SATA/USB 2/USB 3 for H310 SATA x2
2280/3042 size PCIe x2 or SATA/USB 2/USB 3 for C246 (Colay with onboard SATA)
Mini PCIe PCIe x1 and USB 2.0
full size Onboard SATA x2
SATA
CFast USB 2.0 USB 3.1 Gen2 Type A x 2
Intelտ USB 3.1 (H310 only supports Gen1)
MIC/HP CN Audio codec
(Cable)
MIC and HP
ALC269
HDA
H310/C246 USB 2.0
USB 3.1 USB 3.1 Gen1 Type A
USB 2.0
4 PCIe x1 (or 2 PCIe x2) USB 2.0 Type A x 3
2 USB 2 and 2 USB 2/USB 3
USB 2.0
SMBus USB 2.0 Dongle
LPC
I2S SPI
BIOS
AFM
SPI
board GPI/O
I2C 8DI/8DO CN (Cable)
DP (Colay with DDI2) I2C
I2C CN x2
Specifications 9
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Port Resolution
Display Option 1 DisplayPort1 4096x2304@60Hz
Display Option 2 DisplayPort2 4096x2304@60Hz
Display Option 3 DVI-D 1920x1200@60Hz
Display Option 4 VGA 1920x1080@60Hz
10 Specifications
MVP-6100
93
186
210
226
239
A
165
178 5.2
191
R5
25.2
units: mm
7.2
5.2
Specifications 11
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93
186
226
210
239
B
206
219
5.2
232
R5
25.2
units: mm
7.2
5.2
12 Specifications
MVP-6100
210
240
units: mm
Specifications 13
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(252)
240
(212)
210
units: mm
14 Specifications
MVP-6100
(254)
242
units: mm
Specifications 15
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16 Specifications
MVP-6100
3 System Layout
3.1 Front Panel
The MVP 6100 Series provides the following front panel access
features.
A B C D E F G H I J K
O N M L
System Layout 17
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18 System Layout
MVP-6100
19 1
20 2
P/N Description
30-01119-0020 Passive DisplayPort to HDMI adapter cable
30-01120-0020 Passive DisplayPort to DVI adapter cable
30-01121-0020 Passive DisplayPort to VGA adapter cable
30-01157-0020 Active DisplayPort to DVI adapter cable
System Layout 19
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26 19
20 System Layout
MVP-6100
2.2Nȍ
Nȍ
2.2Nȍ 200ȍ
System Layout 21
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22 System Layout
MVP-6100
10 6
15 11
Pin Signal
1 G_VGA_R
2 G_VGA_G
3 G_VGA_B
4 N/C
5 GND
6 GND
7 GND
8 GND
9 N/C
10 GND
11 N/C
12 CRT_DDAT_CN
13 G_VGA_HSYNC
14 G_VGA_VSYNC
15 CRT_DCLK_CN
System Layout 23
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24 System Layout
MVP-6100
8 1
10BASE-T/
Pin # 1000BASE-T
100BASE-TX
1 TX+ LAN_TX0+
2 TX- LAN_TX0-
3 RX+ LAN_TX1+
4 — LAN_TX2+
5 — LAN_TX2-
6 RX- LAN_TX1-
7 — LAN_TX3+
8 — LAN_TX3-
System Layout 25
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Pin Signal
1 V+ (DC_IN)
2 V- (DGND)
Voltage Current
DC Power Source 12 to 24VDC 21A to 10.5A min.
AC-to-DC Adapter 24VDC 10.5A min.
26 System Layout
MVP-6100
1 5
6 9
Signal Name
Pin
RS-232 RS-422 RS-485
1 DCD# TXD422- 485DATA-
2 RXD TXD422+ 485DATA+
3 TXD RXD422+ N/S
4 DTR# RXD422- N/S
5 GND N/S N/S
6 DSR# N/S N/S
7 RTS# N/S N/S
8 CTS# N/S N/S
9 RI# N/S N/S
System Layout 27
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28 System Layout
MVP-6100
E
F
I J K V
W
H
M L
N O P Q
System Layout 29
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A Smart Fan
B SATA
C USB 2.0 dongle
D SATA
E DDR4 SODIMM
F PCIe x16 slot for PEG and SATA
G M.2
H Wafer for GPS external power
I SIM for M.2
J SIM for Mini PCIe
K Mini PCIe
L Wafer for I2C sensor
M Wafer for Speaker
N Wafer for COM x2, DI x8, DO x8 Mic in and Line out
O Wafer for COM x4
P Wafer for I2C sensor
Q Internal Power button
R PCIe x16 slot for PCIe and BP Power
S RTC battery
T Board-to-Board for AFM Board
U CFast
V PWR for AFM MXM carrier board (12V)
W Clear CMOS Jumper
Table 3-13: Mainboard Connector Legend
30 System Layout
MVP-6100
G A B C
System Layout 31
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F F H
A SATA power
B SATA signal
C Additional power for PCIe slot (12V)
D USB 2.0 dongle
E Fan
F Direct SATA
G PCI slot
H PCIe x4 slot
I PCIe x16 slot
32 System Layout
MVP-6100
Pin Signal
1 +5V_GPS
2 GND
System Layout 33
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Pin Signal
1 FAN_GND
2 P_+12V_FAN
3 SIO_FAN_IN
4 SIO_FAN_OUT
34 System Layout
MVP-6100
Pin Signal
1 PWR_BTN-L
2 GND
3 GND
4 RESET_BTN-L
System Layout 35
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36 System Layout
MVP-6100
4 Getting Started
4.1 Attach DC Power Connector
Getting Started 37
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wall-mount wall-mount
bracket bracket
38 Getting Started
MVP-6100
keyhole keyhole
opening opening
Getting Started 39
Leading EDGE COMPUTING
Download the Windows 10 drivers for your system from the prod-
uct page at https://www.adlinktech.com/Products/Industrial_PCs_
Fanless_Embedded_PCs/ExpandableFanlessEmbedded
Computers/MVP-6100_Series and install.
The following drivers must be installed:
X Chipset
X Graphics
X Audio
X Ethernet
X Intel ME
X DI/O
40 Getting Started
MVP-6100
System
Power System Processor Recommended
System Full
Off Idle Full Load Power Supply
Load
MVP-610X
4W 24W 130W 160W 220 or 280W
Intel® Xeon® 80W
MVP-610A
3.7W 21W 127W 144W 220 or 280W
Intel® Core™ i7 65W
MVP-6101
3.6W 24W 65W 97W 220 or 280W
Intel® Core™ i7
MVP-6102
3.7W 22W 64W 94W 220 or 280W
Intel® Core™ i5
MVP-6103
3.8W 22W 56W 85W 220 or 280W
Intel® Core™ i3
MVP-6104 Celeron® 4W 20W 41W 69W 220 or 280W
Power Consumption 41
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42 Power Consumption
MVP-6100
BIOS Setup 43
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B.1 Main
BIOS Information
System Information
44 BIOS Setup
MVP-6100
BIOS Setup 45
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B.2 Advanced
46 BIOS Setup
MVP-6100
Hyper-Threading
BIOS Setup 47
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Intel® SpeedStep™
48 BIOS Setup
MVP-6100
State After G3
Ring Wake
PCIe Wake
BIOS Setup 49
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COM1
Console Redirection
Specify how the host computer and the remote computer (in use)
exchange data. Both computers should have the same or compat-
ible settings.
50 BIOS Setup
MVP-6100
Console Redirection
Specify how the host computer and the remote computer (in use)
exchange data. Both computers should have the same or compat-
ible settings.
BIOS Setup 51
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Maximum time the device will take before it properly reports itself
to the Host Controller, where Auto uses default value for Root port
100ms, and for Hub port the delay is taken from Hub descriptor.
52 BIOS Setup
MVP-6100
Pending Operation
Platform Hierarchy
Storage Hierarchy
Endorsement Hierarchy
BIOS Setup 53
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Device Select
TPM 1.2 restricts support to TPM 1.2 devices, TPM 2.0 restricts
support to TPM 2.0 devices, Auto supports both with default TPM
2.0 devices if not found, TPM 1.2 devices will be enumerated.
54 BIOS Setup
MVP-6100
COM1 Control
COM2 Control
BIOS Setup 55
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56 BIOS Setup
MVP-6100
BIOS Setup 57
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Auto Mode
58 BIOS Setup
MVP-6100
SMART FAN IV
Four temperatures and four fan duty cycles, with three avail-
able fan speed presets, can be user-configured.
BIOS Setup 59
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60 BIOS Setup
MVP-6100
BIOS Setup 61
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Network Stack
62 BIOS Setup
MVP-6100
B.3 Chipset
Above 4G Decoding
BIOS Setup 63
Leading EDGE COMPUTING
64 BIOS Setup
MVP-6100
Memory Configuration
BIOS Setup 65
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Primary Display
Internal Graphics
GTT Size
Aperture Size
66 BIOS Setup
MVP-6100
DVMT Pre-Allocated
DMI/OPI Configuration
BIOS Setup 67
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PCH-IO Configuration
68 BIOS Setup
MVP-6100
M.2 Storage
CFast Card
BIOS Setup 69
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Hot Plug
SATA HDD 1
SATA HDD 2
SATA HDD 3
SATA HDD 4
70 BIOS Setup
MVP-6100
BIOS Lock
BIOS Setup 71
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72 BIOS Setup
MVP-6100
BIOS Setup 73
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B.3.4 BP PEG #1
Speed
74 BIOS Setup
MVP-6100
Speed
Speed
BIOS Setup 75
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Speed
76 BIOS Setup
MVP-6100
B.4 Security
Administrator Password
User Password
BIOS Setup 77
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Key Management
78 BIOS Setup
MVP-6100
B.5 Boot
BIOS Setup 79
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Quiet Boot
Option Description
Disabled Directs BIOS to display POST messages
Enabled Directs BIOS to display the OEM logo.
Fast Boot
Option Description
Disabled Directs BIOS to perform all POST tests.
Directs BIOS to skip certain POST tests to boot
Enabled
faster.
While enabling Fast Boot can reduce system ready time, some
prerequisites can reduce effectiveness.
Boot Configuration
Specifies the priority of boot devices, all of which are detected dur-
ing POST and displayed. Target Boot Option # and click to select
the desired device.
80 BIOS Setup
MVP-6100
BIOS Setup 81
Leading EDGE COMPUTING
Save Changes
Discard Changes
Restore Defaults
82 BIOS Setup
MVP-6100
The WDT API library files and a demo program (incl. source code)
can be downloaded from: https://www.adlinktech.com/Products/
Industrial_PCs_Fanless_Embedded_PCs/ExpandableFanless
EmbeddedComputers/MVP-6100_Series
To use the WDT function library for the MVP-6100, include the
header file WDT.h and linkage library WDT.lib in the C++ project.
InitWDT
SetWDT
Sets the timeout value of the watchdog timer. There are two
parameters for this function to indicate the timeout ticks and
unit. ResetWDT or StopWDT should be called before the expi-
ration of watchdog timer, or the system will reset.
Syntax
C/C++
BOOL SetWDT(BYTE tick, BYTE unit)
Parameters
tick
Specify the number of ticks for watchdog timer. A valid value
is 1 - 255.
unit
Specifies the timeout ticks of the watchdog timer.
Value Description
The unit for one tick is one second. For example, when one
0 tick is specified as 100 and the unit as 0, the timeout value is
100 seconds.
The unit for one tick is one minute. For example, whenone
1 tick is specified as 100 and the unit as 1, the timeout value is
100 minutes.
Return codes
TRUE if timeout value of watchdog timer is successfully set.
FALSE if timeout value of watchdog timer is failed to set.
StartWDT
Start the watchdog timer function. Once the StartWDT is
invoked, the watchdog timer starts. ResetWDT or StopWDT
should be called before the expiration of watchdog timer, or the
system will reset.
Syntax
C/C++
BOOL StartWDT()
Parameters
None
Return codes
TRUE if watchdog timer is successfully started.
FALSE if watchdog timer is failed to start.
ResetWDT
Reset the watchdog timer. The invocation of ResetWDT allows
restoration of the watchdog timer to the initial timeout value
specified in SetWDT function. ResetWDT or StopWDT should
be called before the expiration of the watchdog timer, or the
system will reset.
Syntax
C/C++
BOOL ResetWDT()
Parameters
None
Return codes
TRUE if watchdog timer is successfully reset.
FALSE if watchdog timer fails to reset.
StopWDT
Stops the watchdog timer.
Syntax
C/C++
BOOL StopWDT()
Parameters
None
Return codes
TRUE if watchdog timer is successfully stopped.
FALSE if watchdog timer fails to stop.
Under Linux, please program the WDT function using the LPC IO
registers according to the sample program as follows.
#include <dos.h>
#include <stddef.h>
#include <stdio.h>
/* Config LPC IO NCT6102D to enter config mode */
EnterConfig(void)
{
outp(0x4E, 0x87);
outp(0x4E, 0x87);
}
/* Config LPC IO to exit config mode */
ExitConfig(void)
{ outp(0x4E, 0xAA);
}
/* Read byte from LPC IO register */
unsigned char r_reg(unsigned char regoffset)
{ outp(0x4E, regoffset);
return inp(0x4F); }
/* Write byte to LPC IO register */
void w_reg(unsigned char regoffset, unsigned char
data)
{ outp(0x4E, regoffset); outp(0x4F, data);
}
main(void)
{
unsigned int count;
/* print program title */
printf("-----------------MXC-6400 WDT Demo------------
-----\n");
printf("----------------------------------------------
-----\n");
printf("WDT is set and counting down
now.<<<<<<<<<<<<<<<<<<\n");
printf("----------------------------------------------
-----\n");
for(count=30;count!=0;count--)
{ printf("Countdown %2d : .\n",count);
/* reset WDT timeout value to 10 seconds */
/* w_reg(0x73,0x0A); */
sleep(1);
}
/* disable WDT */
/* WDT stop while timeout value is set to zero */
w_reg(0x30,0x00);
Matrix DI/O API library files and a demo program (incl. source
code) can be downloaded from http://www.adlinktech.com.
To use the DI/O function library for MVP-6100 series, include the
header file awl.h and linkage library awl.lib in the C++ project. DI/O
functions are as follows.
AwlDioGetValue
Reads the digital logic state of a digital input line.
Syntax
C/C++
int __stdcall AwlDioGetValue(int Index)
Parameter(s)
Index
Indexes the digital logic state of MVP-6100 digital input chan-
nels 1 to 8 (bit 0 to 7)
Return codes
0: Operation Success
-1: Operation Failed
AwlDioSetValue
Sets the digital logic state of the digital output line.
AwlDioGetValue
Reads the digital logic state of a digital input line.
Syntax
C/C++
int __stdcall AwlDioGetValue(int Index , int
Value)
Parameter(s)
Index
Indexes the digital logic state of MVP-6100 digital input chan-
nels 1 to 8 (bit 0 to 7)
Value
Sets the digital logic state of MVP-6100 digital output channels
1 to 8 (bit 0 to 7) to 0 or 1.
Return codes
0: Operation Success
-1: Operation Failed
BURN HAZARD
RISQUE DE BRÛLURES
Getting Service
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Getting Service 97