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Feng Guo Tao Yang: 978-1-7281-0395-2/19/$31.00 ©2019 IEEE 1852
Feng Guo Tao Yang: 978-1-7281-0395-2/19/$31.00 ©2019 IEEE 1852
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY DELHI. Downloaded on May 18,2022 at 04:51:18 UTC from IEEE Xplore. Restrictions apply.
Phase-C in calculation is needed to execute program in DSP. [15] has
Phase-B
been used g-h frame to simplify dwell time expression. Hence,
Phase-A
idc this modulation strategy is also based on this coordinate for
VTA1 Da1
Vdc1 C1
this purpose.
The configuration of this paper is organized as follows. In
VTA 2
Section II, NTV and NTV2 are briefly reviewed. In addition,
Da2 DZA1
L ic
ec O
ib
e
N b Load CMV of these two types of modulation schemes are analyzed,
ea ia
respectively. A novel NTV2 with NP voltage balancing and
PMSM Vdc2 C2
VTA3 Da3 DZA2
CMV reduction is proposed in Section III. The simulation
results are shown in Section IV and conclusions are drawn
VTA4 Da4 in Section V.
II. NTV AND NTV2 S CHEME IN 3L-NPC P OWER
Fig. 2. The topology of 3L-NPC power converter C ONVERTER
A. NTV
The space vector diagram in Fig.3 shows 27 basic switching
stress on IGBT. Besides, it produces low-order harmonics in states of 3L-NPC power converter topology. Briefly, take
the AC-side. The problem has been studied by researchers for Sector-I for example, when Vref is located in triangle 3, it
many years. Traditional method makes full use of small vector can be composed by nearest three space vectors tagged with
[5]. That is, for the sake of compensating NP current caused position 1, 2 and 3. The switching sequence is POO → PON
by medium vector, choosing nearest-three space vector (NTV) → OON → ONN. By using voltage-second principle, the
with redundant P- and N-type small vector. Or, according dwell time for each vector can be calculated as follow:
to NP unbalanced range, adding a feedback control loop (
to dynamically adjust duty cycle of each small vector. In Vref = V1 d1 + V2 d2 + V3 d3
(1)
contrast, authors firstly proposed the concept of nearest-three dS1 + dS2 + dS3 = 1
virtual space vector (NTV2 ) PWM to balance NP voltage
Similarly, nearest three space vectors tagged with position
[6]. Some modulation schemes based on NTV2 are presented
1, 3 and 4 can synthesize Vref in triangle 5, corresponding
for different targets [7]–[9]. In [10], the authors proposed a
switching sequence is POO→PON→PNN→ONN.
modified SVPWM without using medium vector, it can solve
the NP voltage drift in high-speed drive of ESG system. As
b β
high modulation index (MI) and low power factor (PF) are
Sector-II
worst conditions for traditional NP-voltage balancing control OPN[ia]
NPN[0] 5 PPN[0]
algorithm [4]. This problem should be taken into account for
optimal ESG system as well. Therefore, NTV2 is the best op- Vref
Sector-III 6 Sector-I
tion to be considered. On the other hand, CMV has detrimental NPO[ic] OPO[-ib] PPO[ic]
2 OON[-ic] 3 PON[ib]
NON[ib]
effects on motor due to shaft current, ground leakage and 4
2
electromagnetic interference noise. More precisely, voltage 3 5
stress on motor caused by CMV could lead to premature NPP[0]
OPP[ia]
NNN[0]
PPP[0] 0
1 POO[-ia]
1 ONN[ia] 4
PNN[0] α
NOO[-ia] OOO[0] (2/3Vdc)
a
failure of motor winding insulation. In [11], CMV reduction
method is proposed with virtual space vector modulation,
OOP[-ic] POP[ib]
but it can be only employed in two-level inverter topology. NOP[ib] NNO[ic] ONO[-ib] PNO[ic]
Because medium space vector and zero-vector OOO both Sector-IV sector VI
do not produce CMV in 3L-NPC power converter, reference
NNP[0]
voltage vector can be synthesized by these vectors to attain ONP[ia]
PNP[0]
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low PF is worst characteristic for ESG system, NTV scheme Duty- Cycle
90°
can hardly be used in this application. 105° 1.0 75°
120° 60°
VM's Duty
2
Space vector diagram of NTV is showed in Fig.6 and the 150° 0.5
Cycle
30°
1 1 -0.5
VS's
Duty
VZS1 = VS1(P OO) (−ia ) + VS1(ON N ) (ia ) 210°
Cycle
330°
2 2
1 1 225° 315°
270°
1 1 1
VZM 1 = VS1(ON N ) (ia )+ VM 1(P ON ) (ib )+ VS2(P P O) (ic ) (a) MI=0.7
3 3 3
Duty- Cycle
From definition above, Vref is composed with a series of 105°
90
90° 75°
120° 60°
space vectors that do not induce extra NP current during VM's
Duty
a switching cycle, thereby balancing NP voltage within all 135° Cycle 45°
30°
NTV scheme.
° 0 Duty- Cycle
-0.5 0.5
C. CMV Analysis for NTV and NTV2 Scheme
The CMV generated by power converter is defined by (2). 195° 345°
Vao , Vbo and Vco are the phase voltage with respect to the NP
210° 330°
potential, respectively. -0.5
225° 315°
1 VS's
Vcom =(Vao + Vbo + Vco ) (2) 240°
Duty
300°
3 255° 270°
Cycle
285°
Through the calculation, the corresponding CMV for basic (b) MI=0.8
switching states can be attained. CMV contains a series of DC Duty - Cycle
1.5
120 ° 60 °
1.0
135 ° VM's 45 °
TABLE I Duty
CMV ACCORDING FOR S WITCHING S TATES Cycle
150 ° 30 °
0.5
Type Switching States |Vcom |
165 ° 15 °
OOO 0
Zero Vectors
PPP NNN Vdc /2
180 ° 0 Duty - Cycle
-1.0 -0.5 0.5 1.0 1.5
POO OON OPO NOO OOP ONO Vdc /6
Small Vectors
ONN PPO NON OPP NNO POP Vdc /3 195 ° 345 °
Large Vectors PNN PPN NPN NPP NNP PNP Vdc /6 210 ° VS's 330 °
Duty
225 °
Cycle 315 °
-1.0
255 ° 285 °
BALANCING AND CMV R EDUCTION IN ESG S YSTEM 270 °
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VZ0 = VOOO (0)
VZL1 = VP N N (0)
-3
10 VZL2 = VL2(P P N ) (0)
1.5
1 1
Small-Vector NP-Balancing Capability
VZS2
PNN(0) 5
NPN (0) (1/3,1/3) PON(ib)
4
(0,1/2) VZM1 (1/2,1/2)
VZS2 Vref
PPO (ic) 5 Vh
PON(ib)
1 2
OON(-ic)
4
Vz0 3
VZM1 PPP
VZS1
(0) NNN PPN (0) Vg VZL1 g
Vref OOO PNP (0) PNN(0)
2 (0,0) (1/2,0) (1,0)
1
VZ0 3
PPP
NNN PNO (ic)
OOO POO(-ia)
VZS1ONN VZL1 PNN (0)
(0) (ia)
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Droop Control
I dc*
I q* Edc
DC Link
PI controller Droop controller
I d* Vq* S/G
Starter Mode
*
e I *
q iabc
PI controller Vd* e
Speed Control e PI controller abc
Current Control dq
Ls Ls id iq
d
e
dt
V * Vd* Vq*
Flux-Weakening V dc
Control PWM Signals
3
Proposed modulation
dq scheme base on g-h
coordinator
TABLE II
DWELL T IME OF S PACE V ECTORS IN TRIANGLE 3,4&5 IN S ECTOR -1 TABLE III
ESG S YSTEM PARAMETERS
Division Space Vectors Dwell Time
Simulation Parameter Value
PNP (1-g-2h)Ts
Ld =Lq 99µH
PNO hTs
Pole Pair 3
S1-3 PNN (2g+h-1)Ts
Switching Frequency 16kHz
PON hTs
PM Flux 0.03644Vs /rad
PPN (1-g-2h)Ts
Base Speed 8000rpm
OPN hTs
Capacitor Value(C1 =C2 ) 4500µF
OPN (1-g-h)Ts
DC-link Voltage 270V
PPN (2h+g-1)Ts
S1-4 PON (1-g-h)Ts
PNN (2h+g-1)Ts
PNO (1-g-h)Ts
PNO (1-g-h)Ts
PPN (1-h-2g)Ts
S1-5 PON gTs
PPN (2h+g-1)Ts
OPN gTs
NPN (1-h-2g)Ts
V. CONCLUSIONS
In this paper, NP voltage balancing and CMV reduction
are both achieved based on proposed modulation scheme for
3L-NPC power converter used in high-speed drive system.
Through the analysis, it can be seen that NTV2 have more Fig. 9. PMSM speed diagram in every stage
advantages over NTV in high MI and low PF conditions, which
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Fig. 10. Voltage of upper and lower side capacitor (C1 &C2 )
ACKNOWLEDGMENT
The research has been supported by Clean Sky 2 (Systems
ITD, project EMINEO), European H2020 program. The author
F. Guo would like to thank China Scholarship Council (CSC)
for sponsoring part of his Ph.D studentship.
R EFERENCES
Fig. 11. CMV with traditional NTV2 scheme
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