BACS1024

INTRODUCTION TO
COMPUTER SYSTEMS

Chapter 3: Computer Architecture

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Chapter Outline
3.1 Key Components of a Computer
3.1.1 Computer Hardware
3.1.2 CPU
3.1.3 Memory
3.2 Computer Operation
3.2.1 IPOS Model
3.2.2 Machine Cycle
3.2.3 LMC Model
3.3 Computer buses
3.4 RISC and CISC Architecture

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3.1 Key Components of a Computer
3.1.1 Computer Hardware

Input
Output Devices
Devices

CPU Memory

Communication Storage
Devices Devices

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3.1 Key Components of a Computer
3.1.2 Central Processing Unit (CPU) / Processor
 Vary in design, complexity, performance, capability and computing power.
Intel 8080 AMD
 More example at: https://www.cpu-world.com/
A photo released Oct. 8, 2018,
shows a 9th Gen Intel Core
processor packages. The
processor family is optimized
for gaming, content creation
and productivity. (Source: Intel
Corporation)
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3.1 Key Components of a Computer

3.1.2 Central Processing Unit (CPU) / Processor

 Key components of a CPU:
1. Arithmetic and Logic Unit (ALU) execute *ax,bx,cx,dx

 Perform mathematical arithmetic (+ , - , * , /) and comparison

operations (> , >= , == , != , < , <=) and Boolean logical
calculation (AND, OR, NOT, XOR).
 Temporary hold data / instruction.
 Numbers are transferred from memory into the ALU for
calculation, and the results are sent back into memory.

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 3.1 Key Components of a Computer

3.1.2 Central Processing Unit (CPU) / Processor

2. Control Unit (CU) fetch, store
 Direct and coordinate most of the operations in the computer.
 Move data to and from CPU registers and other hardware
components
 Accesses program instructions and issues command to ALU for
operations.
 For each of the instruction issued, CU performs a fetch/execute
cycle.
3. Interface Unit (IU)
 Served as an interconnection to Move instructions and data
between the CPU and other device such as memory, I/O devices
and other CPUs.

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3.1 Key Components of a Computer

3.1.2 Central Processing Unit (CPU) / Processor

4. Register
 A special, high speed storage area within CPU.
 Hold data temporary for storage, manipulation, and calculations
 Different register serve different purposes.
 Types of register:
 General purpose registers
- Data registers
- Address registers CS, DS, ES , SS, IP, BP, SP, SI, DI
- Status registers ODITSZAPC
 Special purpose registers

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3.1 Key Components of a Computer

3.1.3 Memory
 Also known as working storage / primary storage.

 Hold programs and data to be accessed by CPU.

 Consists of a larger number of storage cells sequentially numbered and
individually addressable.
 The basic size of the cell is typically 8 bit (byte).
 Neighboring cells can be grouped to store complex or large data.
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3.1 Key Components of a Computer
3.1.3 Memory
 Memory cells

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3.1 Key Components of a Computer
CAPACITY
3.1.3 Memory SPEED
COST
 Memory hierarchy

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3.1 Key Components of a Computer

3.1.3 Memory
 Types of memory
Volatile Memory Non-volatile Memory
Hold data temporarily while the Hold data permanently
CPU is processing them

Requires constant power to Does not requires constant

maintain the stored information power to maintain the stored
information
Primary storage Secondary storage
E.g.: RAM e.g.: ROM READ ONLY MEMORY

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 3.2 Computer Operations
3.2.1 IPOS Model
 A computer system is a collection of hardware, software, etc. working
together to perform a computing task.
 The 4 key operations of a computers are: Input, Process Output and
Storage.

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 3.2 Computer Operations
3.2.2 Machine Cycle.
3.2.2.1 Special Purpose registers
 Register is a single, permanent storage location within CPU used to hold
binary value for storage, for manipulation and/or for simple calculations.
 Registers are not addressed as memory location but instead are
manipulated directly by the control unit during execution of instructions.
NORMAL BYTE SEQUENCE, SORT BY NAME

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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.1 Special Purpose registers
Registers Location Function
A Accumulator ALU Holds the data that are used for arithmetic
operations and results
PC Program Counter Holds the address of the current instruction
being executed
IR Instruction CU Holds the actual instruction being executed
Register currently
MAR Memory Address Holds the address of a memory location
Register
MDR Memory Data Holds a data that is being stored to /
Register retrieved from the memory location
currently addressed by the memory address
register
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 EXCHANGE

3.2 Computer Operations INCORRECT:

XCHG CHAR1, CHAR2

CORRECT:
MOV AL, CHAR1 ; AL=X
3.2.2 Machine Cycle. XCHG AL, CHAR2 ;AL=Y, CHAR2=X
MOV CHAR1, AL ;CHAR1=Y
3.2.2.2 The Fetch-Execute Machine / Instruction Cycle
 There are 4 steps performed by CPU for each machine language
instruction received.
Fetch  Fetch: Retrieve an instruction from memory
phase  Decode: Translate the retrieved instruction into computer
------ commands
Execute  Execute: Execute the computer commands
phase
 Store: Send & write the results back to memory

CU: Decode ALU: Execute

CPU
Fetch Store

Memory Provide storage

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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.2 The Fetch-Execute Machine / Instruction Cycle
 During the fetch phase
 Processor fetches instruction from memory location pointed by PC.
 The instruction loaded into IR.
 During the execute phase
 The processor decodes the instruction & perform the required
action.
 Then, perform action execution of operation.
 Increment PC upon completion of 1 cycle.

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3.2 Computer Operations
accumulator
3.2.2 Machine Cycle
3.2.2.3 LMC Model little man
 LMC model uses a simplified but
typical set of instructions
(program) in the computer
operations.
 The execution of these
instructions illustrate the
working model of the computer.
 As programmer’s role is to
produce the exact sequence of
operations to perform a
particular tasks correctly,
therefore it is essential to study
the computer operations in
details.

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3.2 Computer Operations

3.2.2 Machine Cycle.

3.2.2.3 LMC Model Function CPU LMC Model
Decode CU Little Man
Execute ALU Calculator
Storage Memory Mailbox

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3.2 Computer Operations
3.2.2 Machine Cycle.
3.2.2.3 LMC Model
 The Little Man performs an instruction as the machine / instruction
cycle .
 During the fetch phase, the Little Man find out what instruction
he is executed.
 He walk to location counter and reads its value.
 Then, go to mailbox as address specified & reads the three-
digit number stored, which is instruction to be performed.
❑ During the execute phase, the Little Man perform the work
specified in the instruction.
 Perform LOAD, ADD, SUBTRACT or STORE instruction.

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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.3 LMC Model
 LMC models consists of several key components:
Components Function Description
1. Mailboxes To hold a single slip of Each numbered with an address
paper, upon which is written ranges from 00 to 99 (2 digits
a three-digit decimal only)
number
2. Calculator To enter and temporarily The content restricted to 3 digits
hold numbers for
computation
3. Instruction To increment the count With RESET switch, that located
location outside the mailroom, it facilitate
counter communication between LMC and
outside environment
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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.3 LMC Model
 In LMC environment, each instruction consists of a single digit,
which is the first digit of a three-digit number, to tell the Little
Man (computer) which operation to perform.
store 3 at the location 25

3 25
Instruction / Op code | Mailbox Address

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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.3 LMC Model
Op Instruction Operation
code
5 LOAD instruction The Little Man walks to mailbox address
specified, reads the three-digit number &
punches that number to calculator
3 STORE instruction The Little Man walks to calculator, reads the
three-digit number & write that number to
mailbox as addressed
1 ADD instruction The Little Man reads the three-digit numbers in
mailbox & add it in calculator
2 SUBTRACT instruction The Little Man reads the three-digit numbers in
mailbox & subtract it in calculator

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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.3 LMC Model

Memory
 E.g.: The fetch-execute steps for LOAD location instruc

instruction Address Content

30 540 5 = load

1. PC  MAR ; MAR = 30 31 141

2. MDR  IR ; IR = 540 32 340
3. IR[Address]  MAR ; MAR = 40 : :
4. MDR  A ;A = 660 40 660
5. PC + 1  PC ; PC = 31 41 70

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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.3 LMC Model

Memory
 E.g.: The fetch-execute steps for ADD instruction
Address Content

1. PC  MAR ; MAR = 31 30 540

2. MDR  IR ; IR = 141 31 141
3. IR[Address]  MAR ; MAR = 41 32 340
4. A + MDR  A ;A = 660 + 70 : :
5. PC + 1  PC ; PC = 32 40 660
41 70

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3.2 Computer Operations
3.2.2 Machine Cycle
3.2.2.3 LMC Model
Memory
 E.g.: The fetch-execute steps for STORE instruction Address Content
30 540
1. PC  MAR ; MAR = 32
31 141
2. MDR  IR ; IR = 340
32 340
3. IR[Address]  MAR ; MAR = 40
4. A  MDR ; MDR = 730 : :
5. PC + 1  PC ; PC = 33 40 730
41 70

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3.3 Computer Buses
3.3.1 Computer Buses
 Bus is defined as a communication
pathway that connecting two or
more devices.
 It is a shared transmission medium.
 A signal transmitted by one device is
broadcast to all other devices
attached to the bus.
 Signal will overlap and become
garbled if two devices were
transmitted at the same time.
 Therefore, only one device can
successfully transmit data at a time.

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3.3 Computer Buses
3.3.2 Data Transmission
 A bus consists of multiple
communication pathways, known
as lines.
 Each line transmits binary signal.
 Serial bus
 Transmit a sequence of
binary digits across a single
line.
 Parallel bus
 Transmit binary digits
simultaneously across a
several lines.

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3.3 Computer Buses
3.3.3 Types of Buses
 Three types of buses.
 Control bus
 Address bus
 Data bus

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3.3 Computer Buses
3.3.3 Types of Buses
 Three types of buses.
1. Data bus
 Carries “data” among system models.
 Consists of 32 / 64 / 128 / more separate line.
 No. of line = width of data bus.
 Each line carry one bit at a time.
2. Address bus
 Identifies the sources / destination of the data on data bus.
 Bus width determines the maximum memory capacity of the
system.
 E.g.: n bits addressing giving 2n memory locations

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3.3 Computer Buses
3.3.3 Types of Buses
3. Control bus
 Provides control for the proper synchronization and operation of
the bus and the module.
 Transmits both command and timing information among system
modules.
 Command specifies operation to be performed.
 Timing signals indicate the validity of data & address
information.

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3.3 Computer Buses
3.3.4 Bus Architectures

Point-to-Point Bus Multipoint Bus

Characteris A bus carry signals from a A bus that connect several points
tic specific source to a together. The signals produced by
specific location. a source on the bus are ‘broadcast’
to every other point.
Example Computer’s serial port to Ethernet.
a printer.
Diagram
Computer Computer
Serial port Modem

Computer Computer

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3.3 Computer Buses
3.3.5 The Chipsets
 A chipset is a component which routes
data between the computer buses.
 There are two major types of chipset
used in a typical computer:
 North Bridge (memory controller)
 It controls the transfers between
the processor and RAM.
 It is located physically near the
processor.
 South Bridge (I/O controller /
expansion controller)
 It handles communications
between peripheral devices. •AGP: Accelerated Graphics Port (an expansion for video card)
•SCSI: Small Computer System Interface (an interface for devices to connect to a PC)
•LAN: Local Area Network (an interface for network connection.)
•ISA: Instruction Set Architecture (a hardware/software interface)
•USB: Universal Serial Bus (an interface for device connection to a PC).
•IDE: Integrated Development Environment (an interface for connection between a bus
and a disk storage.
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3.4 CPU Architectures
3.4.1 The CPU Architectures
 The CPU is performed its operation based on the architecture of the
instruction set.
 The CPU architecture defines the basic characteristics and core features of
the CPU.
 The characteristics include:
 The number and the types of registers.
 Methods of addressing memory.
 Basic design and layout of the instruction set.
 There are two core instruction set architectures:
 Reduced instruction set computer (RISC)
 Complex instruction set computer (CISC)

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3.4 CPU Architectures

3.4.2 CISC
 Characterized by:
 Few general purpose registers.
 Many addressing techniques.
 Large number of specialized and complex
instructions.
 Instruction are of varying length.
 E.g.: zSeries, Intel x86 family

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3.4 CPU Architectures
3.4.3 RISC
 Characterized by:
 32 general purpose registers.
 Limited addressing modes.
 Limited and simple instruction set.
 Fixed b-byte instruction word size.
 E.g.: Power PC
 Attempt to produce more CPU power by eliminating 2 major
bottlenecks to instruction execution speed.
 Reduce the number of data memory accessed by using register
more effectively.
 Simplify the instruction set by eliminating rarely used
instructions.

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3.4 CPU Architectures
3.4.4 Comparison between CISC and RISC

CISC RISC
 Consists of many instructions, mostly  Simplify the instructions set of CPU.
are not frequently used.  Emphasize on frequently used
 Requires additional complex hardware instruction.
 Long execution time.  Shorter execution time.

 CISC requires more steps to complete a  RISC executed with the same time
simple instruction. clock interval for a simple instruction.

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3.4 CPU Architectures
3.4.4 Comparison between CISC and RISC
5 major features of RISC over CISC:
1. Limited and simple instruction set
2. Register-oriented
3. A fixed length / format instruction word
4. Limited addressing mode
5. A large bank of registers

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3.4 CPU Architectures

3.4.4 Comparison between CISC and RISC

5 major features of RISC over CISC
1. Limited and simple instruction set
 Execute faster at high clock speed.
 Do not require complex hardware.
2. Register-oriented
 Reduce memory access.
 Use registers to operate / hold frequently used instruction (except for
LOAD and STORE).

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3.4 CPU Architectures
3.4.4 Comparison between CISC and RISC
3. A fixed length / format instruction word
 Easy to identify.
 Can be fetched and decoded independently  pipelining.
4. Limited addressing mode
 Provide single address mode.
 Speed up instruction executions.
5. A large bank of registers
 Registers are applied widely.
 Reduce memory access.

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 Chapter 3: Computer Architecture
Self-review

3.1 Key Components of a Computer 3.3.4 Bus Architectures

3.1.1 Computer Hardware 3.3.5 The Chipsets
3.1.2 CPU 3.4 CPU Architecture
3.1.3 Memory 3.4.1 The CPU Architecture
3.2 Computer Operation 3.4.2 CISC
3.2.1 IPOS Model 3.4.2 RISC
3.2.2 Machine Cycle 3.4.4 Comparison between CISC & RISC
3.2.2.1 Special purpose registers
3.2.2.2 Fetch-Execute Cycle
3.2.2.3 LMC Model
3.3 Computer buses
3.3.1 Computer Buses
3.3.2 Data Transmission
3.3.3 Types of Buses

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