Slide (9-12)

SIMD

Exception and Interrupts

Interrupts - Generally asynchronous hardware related and caused by it, like push button
pressed
Exception - Generally synchronous instruction related and caused by attempted
execution of instruction, normal sequential instruction is modified and the return address
provides the details of the instruction that caused it
Exception Examples: Reset, Undefined Instruction, {Prefetch abort, Data abort}-Illegal
Address
NMI Interrupt - Hardware
ARM Processor Modes
USR, SVC, SYS
Fast Interrupt (FIQ) mode supports a data transfer or channel process
 Interrupt (IRQ) mode is used for general-purpose interrupt handling

ISR or Interrupt Handler

Default implementation of most ISRs is simply a dead loop

The keyword weak means that another non-weak subroutine with the same name defined
elsewhere can override this one
Does not return anything as called by hardware and ISRs (excluding SVC_Handler) do not
take any input argument
IVT address = 0x00000004

Booting Process of Cortex M

This low memory address can be mapped to different regions to allow boot from various
memory regions
Interrupts
IVT - 256 Interrupts

NVIC
The nested vectored interrupt controller (NVIC) is built into Cortex-M cores to manage all
interrupts
Enable and disable interrupts
Configure the preemption priority and sub-priority of a specific interrupt
Set and clear the handing bit of a specific interrupt
ISER - Enable bit, ICER - Disable bit
 32bit 8 registers for both above

Cortex M4 Operating Mode

Execution

Peripherals IRQs > 0, CPU exception IRQs < 0

IRQ priorities -> user programmable
NMI & Hard Fault priorities fixed
CMSIS
Core Peripheral Access Layer
Device Peripheral Access Layer (MCU Specific)
Access Functions for Peripherals (MCU Specific and optional)

SPI and UART

DTE - Mainframe computer, DCE - Modem
8 bit word length with start and stop bit
Coding Questions

USART (Universal Synchronous Asynchronous Reception

Transmission)
PIN
TX, RX, RTS, CTS
TX, RX -> Used to transmit and receive data
RTS, CTS -> Hardware flow control
Register
Two data registers to achieve full duplex communication
Each data register has its associated shift register
Some control registers to control transmission and receiver block
USART_BRR register must be configured properly with mantissa and fraction fields to
produce the desired baud rate
USART_BRR

USART_CR1
Bit 13 UE: USART enable
Bit 12 M: Word length, 0: 1 Start bit, 8 Data bits, n Stop bit 1: 1: 1 Start bit, 9 Data bits, n
Stop bit
Bit 3 TE: Transmitter enable
Bit 2 RE: Receiver enable
USART_SR
Bit 7 TXE: Transmit data register empty (E for EMPTY)
 Bit 5 RXNE: Read data register not empty (NE for NOT EMPTY)
Bit 6 TC: After writing the last data into the USART_DR register, wait until TC=1. This
indicates that the transmission of the last frame is complete

Need for UART

Eliminate clock requirement with UART (asynchronous transmission) and have stop, start bit
as markers
Calculation
If over8 = 0, oversampling by 16 is used
If over8 = 1, the frac3 bit is not considered and must be kept 0

CODE
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