ISSCC 2023 / SESSION 4 / FREQUENCY SYNTHESIZERS / 4.

1
4.1 A 16GHz, 41kHzrms Frequency Error, Background-Calibrated, the POC-DTC noise is not critical for the LMS algorithms, a small inverter driving a
Duty-Cycled FMCW Charge-Pump PLL moderate-size capacitor is used to reduce dynamic power consumption. The fine-POC-
DTC inherent delay is several orders more than the phase offset, and it varies over PVT.
A 7-cell thermometric, 50ps-step coarse POC-DTC compensates such delay variations
Pratap Tumkur Renukaswamy1,2, Kristof Vaesen1, Nereo Markulic1, with sufficient overlap. A MOS switch in series with the tail resistor (see Fig. 4.1.3)
Veerle Derudder1, Dae-Woong Park 1, Piet Wambacq1,2, Jan Craninckx1 enables/disables the VCO during duty-cycled-mode operation, as controlled by the
DC_Start signal from the FMCW controller. To increase the varactor linear-tuning range
1
imec, Heverlee, Belgium, 2Vrije Universiteit Brussel, Brussels, Belgium and to reduce the QDAC resolution, MOS varactors with different threshold voltages are
combined both in the Vtune1 and Vtune2 VCO tuning inputs. A 10b IDAC and a 7b, 1pF-step
FMCW radars are the key components for contactless range and motion sensing in
capacitor are used for the QDAC. The MMD is implemented as a cascade of a ÷2/3 dual-
industrial and healthcare applications. The radar-sensor performance, such as chirp
modulus prescaler. Its first two stages are implemented as a true single-phase clock
bandwidth (BWchirp), chirp slope, and frequency-modulation (FM) linearity, are determined
(TSPC) ÷2/3 prescaler, as shown in Fig. 4.1.3. Compared to [5], the added transistors
by the FMCW chirp generator. When battery powered, the radar should be able to operate
Mp1-3 reduce the short-circuit current during switching and disable DFF-1 latch in ÷2
in a duty-cycled mode with minimal overhead, i.e., fast startup, fast lock at the start of
mode, which reduces the MMD power consumption by 40%. A replica bias and opamp-
every chirp burst, and minimal reset time in-between chirps, without degrading the radar
based feedback loop in the CP reduces the UP/DOWN mismatch currents, which leads
range and Doppler performance. This work presents a robust fast-lock-acquisition
to the reduction in the fine POC-DTC resolution and minimizes the reference/fractional
charge-pump (CP)-PLL with a PFD for duty-cycled chirp generation. A fractional-N
spurs. Together with gear shifting, the coarse-lock-monitor output further speeds-up the
CP-PLL in a two-point-modulation (TPM) architecture breaks the trade-off between the
QDAC digital-code-to-output-frequency (DFC)-INL calibration convergence, by stopping
PLL bandwidth and fast-chirp synthesis [1,2]. A time-domain sign-extraction by using a
the look-up table (LUT) updates and re-starting the chirp when the PLL loses lock.
1b TDC [3] enables the background calibration. A phase-offset-compensating digital-to-
time converter (POC-DTC) assists the sign-extraction by compensating the Figure 4.1.2 shows the timing diagram of the duty-cycled-PLL operation. The DC_Start
2023 IEEE International Solid- State Circuits Conference (ISSCC) | 978-1-6654-9016-0/23/$31.00 ©2023 IEEE | DOI: 10.1109/ISSCC42615.2023.10067404

positive/negative phase offsets generated within the type-II PLL loop. signal from the controller defines the burst and power-down modes of operation. During
the burst mode, the PLL synthesizes Nchirps, each with a duration of Tchirp+Treset. After the
The implemented CP-PLL FMCW chirp generator is shown in Fig. 4.1.1. The capability
burst mode, all PLL blocks are powered down, clocking to most digital blocks is turned
of PFD and CP combination to detect the phase and frequency errors simultaneously
OFF, and only the bandgap and wake-up logic remain active. The LUT coefficients of the
enables robust and fast PLL locking in a duty-cycled environment. A ΔΣ division-modulus
DTC gain, Poc[k] and DFC INL are held. Upon enabling the burst mode, the lock detector
control adds the lowpass modulation signal. A 0.5ps-step DTC in the reference path
output (PLL_Lock) is monitored by the controller to determine if the PLL is locked before
reduces the ΔΣ-shaped multi-modulus-divider (MMD) quantization noise [3]. For
starting the chirp. All LUT coefficient values (DTC gain, DFC INL and Poc[k]) are updated
modulating the sensitive high-gain (KVCO2) VCO-tuning input in the highpass modulation
in the background to track PVT variations during burst mode.
path, a low-power and low-noise charge-integrating DAC (QDAC) is used [2]. During
FMCW modulation, the VCO output frequency (fVCO) is continuously increased by the The FMCW generator was fabricated in a 28nm CMOS process. Figure 4.1.7 shows the
voltage ramp at the QDAC output. The division ratio of the MMD is correspondingly die micrograph. The active core area of the synthesizer is below 0.6mm2 excluding
increased such that the divider output frequency is kept constant, and no modulation decoupling capacitors and test structures. The fractional-N CP-PLL synthesizes
signal propagates through the loop. At the end of the chirp ramp, the QDAC capacitor frequencies from 15 to 18.5GHz with an 80MHz reference. The measured near-integer
and divider ΔΣ modulator are reset. The divider ΔΣ modulator must be reset to ensure fractional-N CP-PLL (with 14mW power) phase-noise spectrum around 16GHz is shown
a fixed phase for every chirp ramp, which otherwise creates radar ghost Doppler spurs. in Fig. 4.1.5. The measured fractional- and reference-spur levels are -53 and -56dBc,
respectively. The integrated jitter from 10kHz to 100MHz is 156fs including all spurs
Nonlinearities in the two-point data injection, such as varactor nonlinear voltage-to-
(FoM=-244.7dB) with a phase noise of -105dBc/Hz at a 1MHz offset. The synthesizer
capacitance conversion, intrinsic 1/√LC nonlinearity, finite current-source output
dissipates 16.5mW of total power during the FMCW modulation, with the modulation
impedance, and the DTC nonlinearity, impact the chirp linearity and need to be calibrated.
frequency ranging from 16 to 17.5GHz. Starting from an empty LUT, all three calibration
Errors due to such nonlinearities induce correlated instantaneous charge error (Icp×Tpulse)
loops converge within less than 250μs. The measured FMCW-chirp spectrum and
at the CP output, and this information can be used for an adaptive background calibration.
linearity across the supply and temperature variations are shown in Fig. 4.1.4. With a
However, an unreliable charge-error sign detection in the CP-PLL causes calibration
1.5GHz BWchirp, the measured rms-FM-error of a 50μs (29.3MHz/μs) chirp is 41kHz. A
failures. For example, if the UP/DOWN PFD outputs are applied to an auxiliary CP, for
1μs chirp reset time (Treset) is set, which is sufficiently long enough for the PLL to re-
charge-error sign extraction, mismatch between both CPs leads to inaccurate calibration
acquire phase-lock following the QDAC and divider-ΔΣ-modulator reset at the end of the
or even the LMS algorithm divergence. In [4], the loop-filter-voltage (Vtune1) drift due to
chirp. Figure 4.1.5 shows the performance of the chirp synthesizer in a 50% duty-cycled-
charge errors is measured using a 1b ΔΣ ADC. But the DC voltage mismatch between
mode (9.2mW power) operation. The measured CP-PLL locking time starting from a
the Vtune1 and ADC common-mode input causes calibration inaccuracies, which are further
power-down mode is below 1μs. The rms-FM-error of the first chirp synthesized
exacerbated by the Vtune1 dependency on fVCO. The sign information can also be extracted
following a power-down mode is also below 41kHz for the same chirp parameters.
at low-power by measuring the time-difference between ‘Ref’ and ‘Div’ edges using a 1b
TDC [3]. However, a fixed phase offset between ‘Ref’ and ‘Div’ edges in a locked loop, Figure 4.1.6 highlights the performance of this work in-terms of chirp parameters and
induced by, e.g., UP/DOWN current mismatch, skew, and pulse width mismatch, causes compared to prior designs. The robust CP-PLL enhanced by an efficient digital calibration
erroneous sign-extraction and inaccurate calibration or even divergence. engine improves chirp linearity, reduces overhead in chirp reset time, and guarantees
reliable and fast re-locking for heavily duty-cycled environments essential for power
When the type-II CP-PLL is locked, the charge output has a zero mean, and, hence, the
savings in industrial radars.
Error_Sign[k] should also be a zero-mean signal. Offsets in PFD, CP, and 1b TDC, create
a non-zero-mean Error_Sign[k] even in a locked loop. As shown in Fig. 4.1.1, a POC- Acknowledgement:
DTC is added in the ‘Ref’ path to compensate for such phase offsets. To generate negative The authors would like to thank EUROPRACTICE for the MPW fabrication services, H.
delays with this technique, a fixed delay is added in the ‘Div’ path. The POC-DTC delay Suys for the PCB design, L. Pauwels and M. Glassee for measurement support.
needs to be background calibrated for proper operation of sign extraction, such that
References:
Error_Sign[k] faithfully represents the sign of the net charge injected into the loop filter.
[1] Z. Shen et al., “A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01%
The phase offset compensation mechanism is depicted in Fig. 4.1.2. Both the ‘Ref’ and
rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope,” ISSCC, pp.
‘Div’ signals are delayed by Tdelay before the sign extraction. The POC-DTC, which is
450-451, Feb. 2021.
initialized at mid-code, generates Tdelay between ‘Ref’ (‘Div’) and ‘Refdel’ (‘Divdel’). In the
[2] P. Renukaswamy et al., “A 12mW 10GHz FMCW PLL Based on an Integrating DAC
presence of a phase offset, non-zero-mean Error_sign[k] generated at the TDC output is
with 90kHz rms Frequency Error for 23MHz/μs Slope and 1.2GHz Chirp Bandwidth,”
scaled and accumulated to adjust the scaling factor POC[k] in the background, to adapt
ISSCC, pp. 278-279, Feb. 2020.
the POC-DTC delay and cancel the phase offset. For example, in the presence of a
[3] M. Mercandelli et al., “A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs
negative phase offset (-ΔTof), the POC-DTC code is decreased to delay the ‘Ref’ edge by
Integrated Jitter,” ISSCC, pp. 274-275, Feb. 2020.
Tdelay-ΔTof. Compared to [3], the proposed technique can compensate for both positive
[4] M. Gupta et al., “A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer with
or negative phase offsets and the inherent POC-DTC-delay (Tdelay) variations over PVT.
LMS-Based DAC Gain Calibration,” IEEE JSSC, vol. 41, no. 12, pp. 2842-2851, Dec. 2006.
Once the POC-DTC-delay algorithm is settled, the Error_Sign[k] information can be used
[5] M. V. Krishna et al., “A 1V 2mW 17GHz Multi-Modulus Frequency Divider Based on
to compensate for the DTC gain [3] and KVCO2 nonlinearity [2].
TSPC Logic Using 65nm CMOS,” ESSCIRC, pp. 431-434, Sep. 2014.
The POC-DTC implementation is split into coarse and fine DTCs as shown in Fig. 4.1.3. [6] H. Shanan et al., “A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter,
A 7b fine POC-DTC can compensate up to ±32ps of phase offset. Its LSB is set close to -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling
the phase modulating DTC LSB, such that its impact on sign extraction is negligible. As Time,” ISSCC, pp. 146-147, Feb. 2022

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 ISSCC 2023 / February 20, 2023 / 1:30 PM

Figure 4.1.2: Phase-error sign extraction in the presence of the charge-pump current
Figure 4.1.1: Block diagram of the CP-PLL FMCW synthesizer. mismatch (top). Chirp duty-cycling scheme (bottom).

Figure 4.1.3: Coarse and fine POC-DTC (top). The QDAC, VCO, and TSPC divide by Figure 4.1.4: FMCW chirp spectrum and FM-error measured across supply and
2/3 prescaler (bottom). temperature variations.

Figure 4.1.5: Measured CP-PLL re-lock time and FM-error during 50% duty-cycling.
CP-PLL phase noise spectrum in fractional-N mode (bottom). Figure 4.1.6: Performance comparison with previously published designs.
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Figure 4.1.7: Die micrograph.

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