2019 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)
Design of 6T SRAM Cell Using Optimized 20 nm
SOI Junctionless Transistor
Muhammad Faris Md Noor, Nurul Ezaila Alias*, Afiq Hamzah, Zaharah Johari and Michael Tan Loong Peng
School of Electrical Engineering, Faculty of Engineering, Universiti Teknologi Malaysia, 81310 Johor Bahru, Malaysia
email: ezaila@utm.my
Abstract— The semiconductor industry has shifted to the
System-On-Chip (SoC) platform. The short channel effects
(SCEs) turns out to be noticeable with the transistor scaling.
Consequently, deteriorating the transistor performance. The
severe SCE degrades the performance of Static-Random-
Access-Memory (SRAM) in SoC chip. The 6T SRAM suffers
from the read stability problem (RSNM), which the data might
be wrongly retrieved during read operation. In this paper, the
designs of 6T SRAM cell using 20 nm Silicon-on-Insulator (SOI)
Junctionless transistor (JLT) is proposed. The introduction of
SOI technology is to isolate the bulk substrate from the gate,
thereby, reducing the junction parasitic capacitance. Hence,
higher speed performance could be achieved. The device
structure of 20 nm SOI-JLT is simulated by using Sentaurus
Device Editor (SDE) module of the Synopsys Sentaurus TCAD
tool. Then, the optimization of SOI-JLT device is performed
through the L9 Taguchi method. Predictive Technology Model
(PTM) SPICE model generator tool is used to generate the
SPICE model of the SOI-JLT. Then, the simulation of SOI-JLT
based 6T SRAM cells are carried out. The static noise margin
(SNM) of 6T SRAM cells are extracted and compared with the
published data. The significant findings of this work show that
the proposed 20nm SOI-JLT based 6T SRAM cells has
enhanced the retention SNM by more than 100% from other’s
6T SRAM cell (published data). It also shows that the read and
write stability of the proposed 20nm SOI-JLT based 6T SRAM
cell is improved by more than 20% from the published data.
Keywords—6T SRAM, RSNM, SCE, SPICE model, SOI-JLT,
SNM, Taguchi
I. INTRODUCTION
Today gadgets are heavily depend on the battery
power; thereby, the power consumption is one of the main
criteria that need to be given special attention. SRAMs are
mainly used for caches on the processor microchip. The
caches system always consumed high amount of power on a
chip. Researchers constantly conduct the research in order to
minimize the caches power consumption. One of the
important characteristics of SRAM architecture is the
threshold voltage, Vth. Due to the extreme downscaling of
the transistor, the supply voltage in digital circuit need to be
reduced to bring the dynamic power consumption under
control. This triggers the need to scale down the Vth in order
to maintain high drive current and high performance [1].
Besides, drain-induced-barrier-lowering (DIBL) can also be
important in SRAM circuit. DIBL refers to the reduction of
Vth at higher drain voltage. DIBL variability in one of the
factors that limit the SRAM functionality, which could result
in asymmetric electrical characteristic between write and read
operation of access transistors of SRAM [2].
In SRAM, there are three modes, which are write,
read, and retention (hold/standby) [3]. SRAM important
criteria is the static-noise-margin (SNM). SNM provide the
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141
means of measuring how much the SRAM circuit can tolerate
external noise before the stable data formed during write
operation or data lost during retention and read operation.
In simple term, SNM is a mean to measure the
stability of an SRAM cell. The cell stability of an SRAM
extremely difficult to control when process node enters 100
nm regime [4]. The conventional SRAM cell is the 6T
SRAM, which consists of six transistors. There are many
other SRAM cell topologies such as 5T, 7T, 8T, and 9T
configurations. However, among all of these topologies, 6T
SRAM has the lowest read stability (RSNM) which denotes
the cell is most vulnerable to noise during read operation.
This could introduce the possibility of wrong data retrieved
when the cell changes state [5].
The proper operation of an SRAM cell may not be
possible in the subthreshold regime that need low power
consumption, high-speed performance, and high cell
stability. Thus, in this work, we introduce the construction of
6T SRAM cell based on the 20 nm silicon-on-insulator (SOI)
junctionless transistor (JLT). JLT proven by researcher to
have better short-channel-effects (SCE) than conventional
MOSFET. The idea is to combine the JLT advantage with
SOI technology which isolate the gate from the body to
reduce parasitic junction capacitance. Hence, higher speed
performance could be achieved for the SRAM. Further, this
paper will focus on RSNM of 6T SRAM. Other SNM will be
compared against other literatures.
II. PREVIOUS WORKS
SRAM has been downscaled over the years.
Because of the extreme scaling process, SRAM has become
sensitive to the variation of device. SRAM must function
correctly according to the specification. Since the read and
write mode are influenced by the variation of device, the
reduction of supply voltage limited causes larger variation of
Vth. Different techniques have been implemented to
overcome the variability problem for 6T SRAM cell, for
instance introducing higher supply voltage, allowing
sufficient margin in write and read operations [6].
In the past, Jin-Yuan Lee and H.Chu, US Patent,
(No: 5,751,044) have proposed a 4T SRAM cell in which
resistor used as the SRAM load. The problems arise are
related to inefficient area and power consumption. Next,
Boaz Eitan et al., US Patent, (No: 5,453,636) has proposed
the SRAM cell similar to Jin-Yuan Lee and H.Chu, but
replace the resistor with bipolar junction transistor (BJT). The
problems appear related to leakage power problem, and
instability during read and write operations.
To overcome such problems, researchers developed
the idea of 6T SRAM cell, which has become the standard
configuration of SRAM nowadays. The term 6T denote that
 the SRAM cells contain six main transistors. Based on Fig. 1,
there are four transistors are n-type metal-oxide-
semiconductor (NMOS) and remaining two transistors are of
p-type (PMOS). NMOS M1 and M5 act as the pull-down
transistors while PMOS M2 and M4 act as the pull-up
transistors. NMOS M5 and M6 function as the pass-gate
transistors to form the path for read and write operation. The
mismatched size between pull-down and pass-gate transistors
have made the 6T SRAM cell susceptible to reliability defects
caused by slight deviation during the fabrication [7].
Fig. 1. Configuration of 6T SRAM cell architecture [8]
Another approach, researchers have proposed the
SRAM cell based on the fin field-effect-transistors (FinFET).
But, the problem associated are the complex fabrication
process and the area consumption since FinFET does not
comply with Moore’s Law. Afterwards, the researchers move
to full depleted silicon-on-insulator (FDSOI) based SRAM
cell. The complications arise due to the formation of junction
capacitance in the drain and source that increases the SRAM
delay. Another device proposed is by using the junctionless
transistors that exhibits better electrical performance
compared to conventional MOSFET [7]. In this paper, the
SRAM development are based on work of V. K. Mishra and
R. K. Chauhan which uses SOI-JLT to form 6T
SRAM. But, this work optimize the SOI-JLT by using
Taguchi method, and focus on the RSNM analysis.
III. METHOD OF DESIGN AND SIMULATION
This paper will be scattered into four different
stages. The first stage is the design of 20 nm n-type and p-
type SOI-JLT by using the Sentaurus Device Editor (SDE)
module of Synopsys Sentaurus. The design will only cover
2D simulation. The second stage is the optimization of 20 nm
SOI-JLT by using L9 Taguchi method. It involves the
optimization of electrical characteristics such as on-to-off
current ratio (Ion/Ioff), Vth, subthreshold swing (SS), and
DIBL. Minitab software used to assist in performing the
device optimization. Based on the optimized electrical
characteristics of n-type and p-type SOI-JLT, the values will
be used to approximate the SPICE model of SOI-JLT by
using Predictive Technology Model (PTM) online tool. This
tool provides the flexibility in approximating the SPICE
model of transistor. The approximation used because the
SOI-JLT structure is still a novel idea and the information
regarding the experiment hardly found on the internet.
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142
The last stage involves the development of 6T
SRAM. The approximated SPICE model of 20 nm SOI-JLT
will be used to construct the 6T SRAM. Here, LtSpice
software used to construct the 6T SRAM cell and perform the
SNM evaluation. The evaluation of SNM performed through
the plotting of voltage-transfer-characteristics (VTC) curves
or simply called ‘Butterfly Curve’. Butterfly curve is the DC
analysis used to measure SRAM stability. It illustrate how big
is the square that be fitted between the two butterfly curves
as shown in Fig. 2 below. The bigger the square, the higher
the stability. This paper will focus on stability during read
operation. But, other SNM will also be considered when
comparing against other work of literatures.
Fig. 2. Illustration of Butterfly Curve analysis to measure SRAM
stability [9]
IV. RESULTS AND DISCUSSION
A. Structure of n-type and p-type SOI-JLT
Fig. 3 represents the structure of 20 nm SOI-JLT
with its doping profile and Table I shows the device
parameters of n- and p-channel of SOI-JLT, which are used
for the simulation. The entire device layer was intensely doped
with n-type dopants. The two-dimensional creation of the
SOI-JLT was completed by SDE module. Since the structure
comprise of high-k metal gate stack, the direct gate tunneling
was excluded [10-11]. The Shockley-Read-Hall (SRH)
component was incorporated into the reproduction. The
mobility models consider both the transverse-field reliance
and the doping reliance. On account of the exceptionally high
doping exist in the channel layer, the mobility would be
deteriorated [10]. In view of the device structure, one of the
fundamental factors that influenced the electrical
characteristics is the concentration of doping. It is significant
in changing the anticipated Vth. It likewise ensures that the
device is working appropriately with the improved control of
the gate and negligible leakage current through the
implementation of SOI concept [12].
 The next step involves the approximation of SPICE
model of SOI-JLT. Based on electrical characteristics in Table
II, the data inserted into PTM SPICE model generator. Based
on the generated SPICE model for SOI-JLT, the models for
NMOS and PMOS SOI-JLT simulated using LtSpice. The
result of the simulation is shown in Table III below. In terms
of Vth, the approximation gives values that is approximate to
the Sentaurus simulation. The other important criteria is SS,
which is critical for fast switching performance for SRAM.
Since approximated SS lies below than 100 mV/decade, the
Fig. 3. Structure of NMOS 20 nm SOI-JLT generated by SDE module of SS value considered near-ideal SS. However, the Ion/Ioff ratio
Sentaurus
fall by two orders. Nevertheless, the ratio is still high for such
devices. Thus, low leakage current. All approximated data are
TABLE I. DEVICE PARAMETERS FOR SIMULATION suitable for SRAM cell application.
Device Parameters n-type p-type
Gate Length, Lg 20 nm 20 nm TABLE III. ELECTRICAL PERFORMANCE AFTER APPROXIMATION
Gate Height, Hg 15 nm 15 nm
Spacer Length , Lsp 25 nm 25 nm
Characteristics n-channel p-channel
Channel Thickness, 3 nm 3 nm
Hepi Vds (V) 0.05 1.0 0.05 1.0
BOX Thickness, Hbox 10 nm 10 nm
Vth (V) 0.314 0.29 0.30 0.27
Substrate Thickness, 30 nm 30 nm
Hsub Ion (A) ×10−4 3.05 0.37
Oxide Thickness, tox 2 nm 2 nm −10
Ioff (A) ×10 7.82 3.66
Total Length, Ltot 100 nm 100 nm
3x1018 3 x1018 Ratio ×105 3.9 1.01
Substrate Doping
(Boron) (Arsenic) SS (mV/dec) 98.76 104
2 x1019 2 x1019 DIBL (mV/V) 25 35
Channel Doping
(Arsenic) (Boron)
Gate Material Gold Tungsten
C. Performance Evaluation of SOI-JLT Based 6T SRAM
The final part involves the construction of 6T SRAM
B. Optimization of SOI-JLT by Taguchi Method based on the approximated SPICE model. The simulation of
After the structure of SOI-JLT NMOS and PMOS 6T SRAM performed by using LtSpice. Fig. 4 demonstrate the
have been generated by using SDE module of Sentaurus, the Butterfly curve of 6T SRAM cell in retention, write, and read
SOI-JLT optimized by using Taguchi Method. Table II shows operation. Table IV summarize the comparison of SOI-JLT
the electrical performance of SOI-JLT after Taguchi based 6T SRAM cell. Based on the table, in terms of retention
optimization. The Vth is considered to be nominal. The SNM, the SOI-JLT based 6T SRAM shows higher stability
Subthreshold Swing (SS) is near to the ideal SS which is 60 compared to [14] that uses conventional SOI technology. This
mV/dec. The value of drain-induced-barrier-lowering (DIBL) indicated the 6T SRAM stable during holding the data inside
small enough, thereby, decrease the variability is SRAM cell. the storage nodes. In terms of write static noise margin,
The Ion/Ioff is at the order of ninth, indicates SOI- JLT has low proposed work exhibits better stability compared to [13] that
leakage current. Data in Table II simulated by using SDevice used FinFET technology. This indicate that the proposed
module of Sentaurus. SRAM cell has better stability during writing into the storage
node. In terms of RSNM, proposed work shows better read
TABLE II. ELECTRICAL PERFORMANCE AFTER TAGUCHI stability compared to [14]. However, slightly less than [13]
that uses FinFET based SRAM. This indicate that the read
Parameters n-channel p-channel stability of proposed cell could retain the correct data easier
Vds (V) 0.05 1.0 0.05 1.0 compared to [13].
Vth (V) 0.32 0.21 0.35 0.32
−4
Ion (A) ×10 2.32 0.57
Ioff (A) ×10−10 1.94 0.27
Ratio ×105 1.2 2.1
SS (mV/dec) 78.71 83
DIBL (mV/V) 21 28.1

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143
 Q.J130000.3551.07G45. Besides, thanks to the Research
SNM=390mV RSNM=194mV Management Center (RMC) of University Teknologi
Malaysia (UTM) for accommodating an excellent research
1.0
1.0

1st Inverter
1st Inverter
2nd Inverter environment to accomplish this work.
2nd Inverter
0.8 0.8

0.6
REFERENCES
0.6

V QB (V)
VQB (V)

0.4 0.4
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TABLE IV. VALIDATION AGAINST OTHERS’ WORKS
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V. CONCLUSION
In conclusion, the proposed SOI-JLT exhibits better
electrical performance compared to the conventional
MOSFET. The use of SOI technology is to separate between
the body and gate of the transistor so that the parasitic
junction capacitance would be minimized. The electrical
characteristics of the 20 nm SOI-JLT for both n-channel and
p-channel device structures have been successfully designed
and simulated by using Synopsys Sentaurus TCAD Tools.
The electrical characteristics of the both n-channel and p-
channel of 20 nm SOI-JLT have been successfully optimized
by using L9 Taguchi method. The proposed SOI-JLT based
6T SRAM cell shows better in retention SNM than the others’
6T SRAM cell (published data) for more than 100%
improvement. On top of that, the results have been validated
with the published data and it shows that the proposed SOI-
JLT based 6T SRAM cells are at least 20% better in RSNM
and WSNM than the others’ published work.
ACKNOWLEDGMENT
Authors would like to acknowledge the Ministry of
Higher Education (MOHE), Malaysia for the financial
support under the University Grant project number
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