Superlattices and Microstructures 112 (2017) 143e150

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Study of 6T SRAM cell using High-K gate dielectric based

junctionless silicon nanotube FET
Shubham Tayal a, *, Ashutosh Nandi b
a
School of VLSI Design & Embedded System, NIT Kurukshetra, Haryana, India
b
Department of Electronics and Communication Engineering, NIT Kurukshetra, Haryana, India

a r t i c l e i n f o a b s t r a c t

Article history: This paper investigates the performance of 6 T SRAM cell using high-K gate dielectric based
Received 5 August 2017 junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate
Received in revised form 5 August 2017 dielectric enhances the delay performance of the JLSiNTFET based 6 T SRAM cell. Read
Accepted 29 August 2017
access time (RAT) and write access time (WAT) improves by ~18% and ~20% when TiO2 is
Available online 12 September 2017
used as gate dielectric instead of SiO2. The hold, read, and write SNMs (static noise margin)
of the 6 T SRAM cell also improves marginally by the use of high-K gate dielectric.
Keywords:
Furthermore, it is also observed that the improvement in hold SNM (HSNM), read SNM
Gate stack
SiNT FET
(RSNM), and write SNM (WSNM) can be boosted by using higher interfacial layer thickness
Interfacial layer thickness (TI). However, the improvement in read access times (RAT) & write access time (WAT)
6T SRAM degrades at higher TI. Thus, high-K gate dielectrics with high interfacial layer thickness are
more suitable for JLSiNT-FET based 6 T SRAM cell.
© 2017 Elsevier Ltd. All rights reserved.

1. Introduction

Silicon nanotube FET (SiNT-FET) is a promising candidate for extreme scaling of multigate devices and has excellent
immunity to short channel effects (SCEs) as compared to other multigate structures like FinFETs and gate-all-around
structures. The SiNT-FETs have two surrounding gates (one from outside the channel surrounding the gate and other from
inside the channel making the core) to control the channel [1e5]. Furthermore, the tunneling operation in SiNT-FET has been
investigated by Hossain et al. [6]. Junctionless transistors as a solution to the problem of making the abrupt junctions in
extremely scaled devices are first proposed by Colinge et al. [7] and further investigated by Gnani et al. [8]. Gnani et al. [8]
reported that junctionless transistors are also effective in reducing SCEs. The junctionless silicon nanotube FET structure
has also been studied by Tayal et al. [9] and Ambika et al. [10].
The feasibility of junctionless silicon nanotube FET (JLSiNT-FET) based digital/analog circuits and their behavior is of
current interest to the researchers. Modern microprocessors utilize on-chip caches, which can adequately reduce the speed
gap between the processor and main memory to boost system performance. These on-chip caches are usually implemented
using arrays of SRAM cells. Consequently, we can conclude that SRAMs comprise an inexorably substantial part of present day
VLSI circuits [11e13]. Recently, for the first time, SiNT-FET based 6 T-SRAM has been investigated by Jayakumar et al. [14]. They
demonstrated the SiNT-FET based 6 T-SRAM operation and also studies the Hold, Write, and Read SNMs (static noise margin)
of the cell. The study of junctionless silicon nanotube FET based 6 T-SRAM cell is yet to be reported in the literature.

* Corresponding author.
E-mail addresses: Shubhamtayal999@gmail.com (S. Tayal), ashutosh.chl@gmail.com (A. Nandi).

http://dx.doi.org/10.1016/j.spmi.2017.08.061
0749-6036/© 2017 Elsevier Ltd. All rights reserved.
144 S. Tayal, A. Nandi / Superlattices and Microstructures 112 (2017) 143e150

Furthermore, the researchers investigated that high-K gate dielectric also affects the performance of the digital circuits
[15e17]. Pravin et al. [18] investigated the 6 T-SRAM cell using high-K dielectrics based junctionless transistors. They reported
that read SNM, write SNM, and hold SNM of 6 T-SRAM cell can be improved by using HfO2 instead of SiO2 as a gate dielectric.
However, the effect of high-K gate dielectric on the performance of JLSiNT-FET based 6 T-SRAM cell is yet to be investigated.
Subsequently, in this paper, we have demonstrated the effect of high-K gate dielectric on the performance of JLSiNT-FET based
6 T-SRAM cell. Moreover, high-K dielectrics when deposited directly on silicon could deteriorate the device performance due
to poor interface quality and process compatibility. Therefore, to improve the device performance, gate-stack (GS) configu-
ration has been investigated by researchers [19,20]. In GS configuration, a very thin layer of SiO2 (known as interfacial layer) is
first deposited on the silicon substrate and then high-K dielectrics are deposited over SiO2. We have also used the GS-
configuration for investigating the JLSiNT-FET based 6 T-SRAM cell.
In the present work, extended 3D simulations have been carried out on the Sentaurus TCAD mixed mode simulator to
study the impact of high-K gate dielectrics on the performance of junctionless silicon nanotube FET based 6 T SRAM cell. The
rest of this paper is organized as follows: in Section 2, the device architecture and setup used in the simulation to study the
SRAM performance is outlined. Section 3 shows the effect of high-K gate dielectrics and interfacial layer thickness on the
performance metrics of 6 T SRAM. Finally, the conclusion of the simulation study is discussed in section 4.

2. Device architecture and simulation setup

Fig. 1 shows the schematic diagram of n-channel junctionless silicon nanotube FET (JLSiNT-FET) structure. 3D Sentaurus
TCAD mixed-mode simulator [21] is used to simulate the device and SRAM cell. The source/drain extension length (LEXT) and
channel length (Lg) both are set at 15 nm. Source/Drain regions are uniformly doped with arsenic for n-type (boron for p-type)
at 1019 cm
3. To make the device junctionless, the channel doping concentration (arsenic for n-type and boron for p-type) is
also set to 1019 cm
3. The simulated JLSiNT-FETs has an outer diameter D (¼2TSi) of 10 nm and an inner oxide thickness (IEOT)
of 2 nm [2]. As gate side-wall spacers are crucial for the formation of the SiNT-FETs, the SiO2 spacer is used in all devices [3].

(a)
Lg Spacer

Inner Gate

LEXT TSi

(b)
3.0E-03 N-JLSiNT-FET 5.0E-03
P-JLSiNT-FET
Drain Current Id (A/μm)

2.0E-03 5.0E-06
Log(Id) (A/μm)

1.0E-03 5.0E-09

0.0E+00 5.0E-12
-1 0 1
Gate-Source Voltage (VGS) (V)

Fig. 1. (a) Schematic view of n-channel JLSiNT-FET (b) simulated ID-Vgs characteristics of N/P JLSiNT-FETs.
 S. Tayal, A. Nandi / Superlattices and Microstructures 112 (2017) 143e150 145

Table 1
JLSiNT-FET device details.

Parameters JLSiNT-FET
Channel Length 15 nm
Interfacial Layer Thickness 0.2e0.7 nm
IEOT 2 nm
OEOT 1 nm
Metal Work-function 4.8 eV
Gate Dielectric Constant (K) 40
Source/Drain Doping 1  1019 atoms/cm
3
Source/Drain Extension Length (LEXT) 15 nm
Channel Doping 1  1019 atoms/cm
3

The TiO2 (K ¼ 40) is considered as high-K gate dielectric to study the impact of high-K gate dielectrics on SRAM perfor-
mance. Interfacial layer thickness (TI) is set at 0.2 nm (unless specified otherwise) when high-K gate dielectric is used [20]. The
physical thickness of the TiO2 layer is set at (1-TI)  K/3.9 to maintain Effective oxide thickness (EOT) ¼ 1 nm for all the
considered devices. Simulated ID e Vgs characteristics of N/P JLSiNT-FET is shown in Fig. 1 (b). The parameters used for JLSiNT-
FET devices used in the simulation are tabulated in Table 1.
Metal gate technology is preferred over the poly-silicon gate to avoid the poly-depletion effects [22]. Simulation models
used during simulation are Drift-Diffusion model, Philip unified mobility model, Lombardi mobility model, band to band

(a) (b)
Drain Drain

Outer Inner Outer Inner

Gate N-FET Gate P-FET
Gate Gate

Source Source

(c) WL

VDD

BL BL

P1 P2

V2

A1 V1 A2

N1 N2

GND
Fig. 2. (a) Symbol used for N-JLSiNT-FET (b) Symbol used for P-JLSiNT-FET (c) Schematic of 6 T SRAM circuit built with N/P JLSiNT-FET.
146 S. Tayal, A. Nandi / Superlattices and Microstructures 112 (2017) 143e150

auger recombination, MLDA quantization model, old slotboom bandgap narrowing phenomenon and SRH recombination/
generation model [20] [23].

3. 6 T SRAM cell design and analysis

Fig. 2 shows the symbol used for JLSiNT-FET device and schematic of JLSiNT-FET based six-transistor (6 T) SRAM cell. SiO2
(K ¼ 3.9) is used as a gate dielectric in the N/P JLSiNT-FETs. Cell ratio (CR) and pull-ratio (PR) are crucial parameters for a SRAM
cell and should be carefully set for SRAM cell to be stable. The size of pull-up transistors (P1 or P2) and access transistors (A1
or A2) are kept same to set PR ¼ 1, whereas, CR is set to 2 [24].
The stability of a SRAM cell is quantified in terms of its static noise margin (SNM). SRAM cell works mainly in three modes:
Write mode, Hold mode, and Read mode. The data is first written in the cell by using bit lines (BL & BL ) followed by the Hold
mode in which the cell holds the written data and then finally when the data required to read, the SRAM cell works in Read
mode. The stability of a SRAM cell to keep the data unaltered during the hold mode is measured in terms of Hold SNM
(HSNM). Similarly, the stability of the cell during Read and Write mode are measured in terms of Read SNM (RSNM) and Write
SNM (WSNM) respectively. Butterfly curves are used to measure the SNM in all the three modes. Butterfly curves are obtained
by superimposing the voltage transfer characteristic of both the inverters. The butterfly curve obtained for different mode of
operation of SRAM cell are shown in Fig. 3.

(a) (b) 1.0

1.0

0.8
0.8

0.6
0.6
V1 (V)
V1 (V)

0.4 0.4

0.2 0.2

0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
V2 (V) V2 (V)

(c)
1.0

0.8

0.6
V1 (V)

0.4

0.2

0.0
0.0 0.2 0.4 0.6 0.8 1.0
V2 (V)
Fig. 3. Butterfly curves of JLSiNT-FET based 6 T SRAM cell during (a) Write mode (b) Hold mode (c) Read mode.
 S. Tayal, A. Nandi / Superlattices and Microstructures 112 (2017) 143e150 147

During Write mode, the bit to be write in the cell is applied at BL line and its complementary bit is applied at BL line. Word
line (WL) is kept at VDD. The butterfly curve obtained during write mode is shown in Fig. 3(a). For hold mode, the butterfly
curve is plotted by keeping the signal voltage at word line (WL) at ground (GND) voltage (Fig. 3(b)). During Read mode, to
obtain the butterfly curve (Fig. 3(c)), both the bit lines (BL & BL ) are precharged to a high voltage while keeping the WL at
VDD ¼ 1 V. The length of the longest diagonal of largest square that can be fit into lobes of butterfly curve divided by √2 is
known as the SNM value [25]. The measured value of WSNM, RSNM, and HSNM are 282 mV, 142 mV, and 325 mV respectively.
Furthermore, the access time in Read mode, i.e. read access time (RAT), is an important metric, which depends on read cell
current through the access and pull-down transistors. Similarly, the write access time (WAT) during the Write mode is
measured between the time when WL reaches to 50% of VDD and node V2 reaches to switching threshold voltage of the other
inverter [26]. The measured value of RAT and WAT is 4.3 pS & 10.2 pS respectively for JLSiNT-FET based 6 T SRAM cell.

3.1. Effect of high-K gate dielectric on JLSiNT-FET based 6 T SRAM cell

The use of high-K gate dielectrics is of current interest in the research industry. High-K gate dielectrics are used to
overcome the problem of direct tunneling current associated with SiO2 at scaled dimensions. The use of high-K gate dielectric
provides a thicker physical layer of gate dielectric while keeping the same effective oxide thickness (EOT). This subsection
describes the effect of high-K gate dielectric on the performance of JLSiNT-FET based 6 T SRAM cell. Pravin et al. [18] reported
that the use of high-K gate dielectric improves the static noise margin of the 6 T SRAM in dual material surrounding gate

(a) (b)
1.0 1.0
K=3.9
K=3.9
K=40
0.8 K=40 0.8

0.6 0.6
V1 (V)
V1 (V)

0.4 0.4

0.2 0.2

0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
V2 (V) V2 (V)

(c)
1.0

K=3.9
0.8 K=40

0.6
V1 (V)

0.4

0.2

0.0
0.0 0.2 0.4 0.6 0.8 1.0
V2 (V)
Fig. 4. Comparison of SRAM butterfly curves for different value of K during (a) Write mode (b) Hold mode (c) Read mode.
148 S. Tayal, A. Nandi / Superlattices and Microstructures 112 (2017) 143e150

junctionless transistor. We observed the same trend in junctionless silicon nanotube FET based 6 T SRAM cell. The interfacial
layer thickness (TI) of 0.2 nm is used for the study. Fig. 4 compares the butterfly curve of gate-stacked JLSiNT-FET based 6 T
SRAM cell implemented with SiO2 and TiO2 (K ¼ 40) as a gate dielectric for all the three modes of operation. It is observed that,
with the use of TiO2 as a gate dielectric, the SNM during all the three modes (Hold, Read and Write) of the cell improves. This
may be attributed to improved DIBL of pull-up and pull-down transistors [24].
The WSNM, HSNM, and RSNM are improved by approximately 6%, 11%, and 17% respectively for TiO2 gate dielectric as
compared to SiO2 gate dielectric. Furthermore, the use of high-K gate dielectric improves the delay performance of the SRAM
cell as well. The read access time (RAT) and write access time (WAT) is improved by 18% and 20% respectively when TiO2 is
used as gate dielectric instead of SiO2.

3.2. Effect of interfacial layer thickness (TI) on JLSiNT-FET based 6 T SRAM cell

As discussed in the earlier subsection that use of high-K gate dielectric improves the performance of the JLSiNT-FET based
6 T SRAM cell. However, the improvement in WSNM, HSNM, and RSNM are marginal and can further be improved by using
thicker interfacial layer. The effect of interfacial layer thickness (TI) on the performance of JLSiNT-FET based 6 T SRAM cell is
discussed in this subsection. The outer gate length (Lg) and source/drain extension length (LEXT) both are set as 15 nm. Fig. 5
depicts the butterfly curves of Write, Hold and Read modes for different value of TI. It is observed that when the interfacial

(a) (b)
1.0 1.0
Ti=0.7 TI=0.7

0.8 Ti=0.2 0.8 TI=0.2

0.6 0.6
V1 (V)

V1 (V)

0.4 0.4

0.2 0.2

0.0 0.0
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
V2 (V) V2 (V)

(c)
1.0
TI=0.7
0.8 TI=0.2

0.6
V1 (V)

0.4

0.2

0.0
0.0 0.2 0.4 0.6 0.8 1.0
V2 (V)
Fig. 5. Comparison of SRAM butterfly curves for different value of TI during (a) Write mode (b) Hold mode (c) Read mode.
 S. Tayal, A. Nandi / Superlattices and Microstructures 112 (2017) 143e150 149

Table 2
Comparison of performance metrics of JLSiNT-FET based 6 T SRAM cell for different value of TI.

TI (nm) Ion (mA) WSNM (mV) HSNM (mV) RSNM (mV) RAT (pS) WAT (pS)
0.2 10.2 288 336 159 3.5 8.3
0.5 15.1 289 343 164 3.6 8.5
0.7 21 308 406 211 4.9 10.1

layer thickness (TI) is increased from 0.2 nm to 0.7 nm, the static noise margin of the SRAM cell improves which may be
attributed to higher on current (Ion) at TI ¼ 0.7 nm [24].
The value of WSNM, HSNM, and RSNM are increased by ~7%, ~21%, and ~33% respectively at TI ¼ 0.7 nm as compared to at
TI ¼ 0.2 nm. However, the delay performance of the JLSiNT-FET based 6 T SRAM cell degrades with the increase in TI [24]. The
performance metrics of SRAM cell for different value of TI are compared in Table 2. The read access time (RAT) and write
access time (WAT) increases by approximately 40% & 21% respectively when TI is increased from 0.2 nm to 0.7 nm. Clearly, for
the stability of the SRAM cell, higher TI is beneficial.

4. Conclusion

In this paper simulation study of junctionless silicon nanotube FET (JLSiNT-FET) based 6 T SRAM cell has been carried out.
The impact of high-K gate dielectric on the performance of 6 T SRAM cell built with gate-stacked based JLSiNT-FET devices has
been studied via extensive device simulations. We observed that the performance (stability and delay) of JLSINT- FET based
6 T SRAM can be improved by using high-K gate dielectrics in gate-stack configuration instead of SiO2 as a gate oxide. The
write SNM (WSNM), hold SNM (HSNM) and read SNM (RSNM) are improved from 282 mV, 325 mV, and 142 mV for SiO2 gate
dielectric to 288 mV, 336 mV, and 159 mV for TiO2 (K ¼ 40) as a gate dielectric. The read access time (RAT) and write access
time (WAT) is improved by ~ 0.8 pS & ~ 1.9 pS respectively when TiO2 is used as gate dielectric against the SiO2 as a gate
dielectric. Furthermore, it is also observed that the static noise margins of JLSiNT-FET based SRAM cell can further be boosted
by using the higher value of interfacial layer thickness (TI). The value of WSNM, HSNM, and RSNM are increased from 288 mV,
336 mV, and 159 mV respectively for TI ¼ 0.2 nm to 308 mV, 406 mV, and 211 mV respectively for TI ¼ 0.7 nm. This
enhancement in SNM of SRAM cell can be attributed to higher on current at TI ¼ 0.7 nm as compared to at TI ¼ 0.2 nm. Thus,
we can conclude that the for memory applications, high-K gate dielectric based JLSiNT-FET devices are more suitable. Sub-
sequently, memory circuits will show better stability when the thicker interfacial layer is used while designing gate-stack
based JLSiNT-FETs for 6 T SRAM cell.

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