21-12-2023

Module 3 – Number System &

Boolean Algebra

By:
Prof. Akshatha Bhat
ECE

Number System Boolean Algebra

• Theorems, De Morgan's theorem. Digital
• Decimal, Binary and Hexadecimal
Circuits: Logic gates, NOT, AND, OR
number systems,
• XOR, NAND, NOR and X-NOR gates,
• Converting from Decimal to
algebraic simplification, NAND and
Binary/Hexadecimal,
• NOR implementation: NAND
• Converting Binary to
implementation, NOR implementation,
Decimal/Hexadecimal,
Half adder, Full adder.
• Converting Hexadecimal to
• Flip Flops: Introduction to Flip-Flops,
Binary/Decimal, Complement of
NAND gate latch/NOR gate latch, RS Flip-
Binary Numbers.
Flop.
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1. Number Systems

• The Decimal number system is what we use everyday.

• In Digital Systems, such as COMPUTERS, combination of the
TWO STATES called CODES are used to represent
information. This is Binary number system.
• The Hexa-decimal number system is used for conversion of
binary data for easiness.

2a. Decimal Number System

• Has 10 digits
• 0 through 9
• Ten distinct digits
• Base(radix) 10 system

• Representation [𝑁𝑢𝑚𝑏𝑒𝑟]
• Ex: [2]
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2b. Binary Number System

• Has 2 digits
• 0 and 1 [LOW and HIGH]
• Two distinct digits
• Base 2 system

• Representation [𝑁𝑢𝑚𝑏𝑒𝑟]
• Ex: [10110]

2c. Hexa-Decimal Number System

• Has 16 digits
• 0 through 9 and ‘A’ through ‘F’
• Sixteen distinct states
• Base 16 system

• Representation [𝑁𝑢𝑚𝑏𝑒𝑟]
• Ex: [8𝐶]
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2d. Summary

3a. (i) Conversion from Decimal to Binary

Repeated division by 2 method:

The decimal number is repeatedly divided by 2 and writing
down the remainder after each division until a quotient of ‘1’ is
obtained.

Ex: 25 = 11001
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3a. (i) Conversion from Decimal to Binary

• Try Yourself !

1. 7 =[ ]
2. 45 =[ ]
3. 170 =[ ]

3a. (ii) Conversion from Decimal to Hexa

Repeated division by 16 method:

The decimal number is repeatedly divided by 16 and writing
down the remainder after each division.

• Ex: 423 = 1𝐴7

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3a. (ii) Conversion from Decimal to Hexa

• Try Yourself !

1. 27 =[ ]
2. 415 =[ ]
3. 1470 =[ ]

3b. (i) Conversion from Binary to Decimal

• By summing together, the weights of the various positions in

the binary number that contain a 1.

• Ex: 11011 = 2 + 2 + 0 + 2 + 2
• = 16 + 8 + 0 + 2 + 1

• = 27
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3b. (i) Conversion from Binary to Decimal

• Try Yourself !

1. 100110 = [ ]
2. 0010101 = [ ]
3. 101101 = [ ]

3b. (ii) Conversion from Binary to Hexa

• The binary number is grouped into groups of 4-bits and each

group is converted to its equivalent hexa-digit.
• Zeros are added as needed to complete 4-bit group (on LHS).

• Ex: 110010010 = 1 1001 0010

= 0001 1001 0010
= 1 9 2
= 192
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3b. (ii) Conversion from Binary to Hexa

• Try Yourself !

1. 100110 = [ ]
2. 0010101 = [ ]
3. 101101 = [ ]

3c. (i) Conversion from Hexa to Binary

• Each Hexa-digit is converted to its 4-bit binary equivalent.

• Ex: 9𝐹2 = 1001 1111 0010

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3c. (i) Conversion from Hexa to Binary

• Try Yourself !

1. 192 = [ ]
2. 𝐴2𝐵 = [ ]
3. 𝐹𝐹𝐸 = [ ]

3c. (ii) Conversion from Hexa to Decimal

• Each Hexa-digit position is multiplied by the weight that is a

power of 16.

• Ex: 356 = 3×16 + 5 × 16 + 6 × 16

= 768 + 80 + 6
= 854
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3c. (ii) Conversion from Hexa to Decimal

• Try Yourself !

1. 192 = [ ]
2. 𝐴2𝐵 = [ ]
3. 𝐹𝐹𝐸 = [ ]

Complements of Binary Numbers

1. 1’s complement of binary numbers

Change all 1s to 0s and all 0s to 1s.
Ex: 0010 = 1101

Try !
Examples given by students
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Complements of Binary Numbers

2. 2’s complement of binary numbers

by adding 1 to the LSB of the 1’s complement.
Ex: 0010 = 1101
= +1
= 1110

Key Words: Binary Addition

1. Logic Gates

• Logic is the realm of human reasoning that tells you a certain

proposition is TRUE if certain conditions are TRUE.
• The term logic is applied to DIGITAL ELECTRONICS which
form the basic building blocks of DIGITAL SYSTEMS.
• These form the basic elements of digital systems.
• THREE basic logic operations (NOT – AND – OR) form the
basic elements of a digital system.
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1a. NOT Operation

• Changes one logic level to the opposite logic level.

• When the input is HIGH (1), the output is LOW (0) and vice-
versa.
• Implemented by an INVERTER Gate.
• Available as: IC 7404

Key Words: Symbol and Truth Table

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1b. AND Operation

• Produces a HIGH output only if
ALL the inputs are HIGH.
• When any (or) all inputs are
LOW, the output is LOW.
• Implemented by an AND Gate.
• AND Gate performs logical
multiplication

• Ex: IC 7408

• Produces a HIGH output when any of the inputs is HIGH.

1c. OR Operation • When both inputs are LOW, the output is LOW.
• Implemented by an OR Gate.
• OR Gate performs logical addition.

• Ex: IC 7432
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2. Universal Logic Operations

• NAND and NOR operations are universal.

• Universality means that both of them can be used for,
1. Inverter (NOT)
2. AND
3. OR

2a. NAND Operation

• It is the contraction of NOT-AND.

• Implies an AND function with a
complimented output.

• Ex: IC 7400
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2b. NOR Operation

• It is the contraction of NOT-OR.

• Implies an OR function with a
complimented output.

• Ex: IC 7402

3a. EX-OR Operation

• The output is HIGH only when the
TWO inputs are at OPPOSITE logic
levels.
• The output is LOW only when the
TWO inputs are HIGH or when the
TWO inputs are LOW.
• Implemented by a XOR Gate.

• Ex: IC 7486
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• The output is LOW only when the TWO inputs

3b. EX-NOR Operation are at opposite logic levels.
• The output is HIGH only when the TWO inputs
are HIGH or when the TWO inputs are LOW.
• Implemented by a XNOR Gate.

• Ex: IC 74266

Summary
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Summary

Demorgan’s Theorem

We use De Morgan’s theorems to solve the

expressions of Boolean Algebra. It is a very
powerful tool used in digital design.
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Demorgan’s Theorem

Demorgan’s Theorem
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Theorems/Rules of
Boolean Algebra/
Boolean
Logic/Binary Logic
Useful in manipulating and
simplifying Boolean
expressions.

Laws of Boolean Algebra

• Basic Laws:

1. Commutative Law (a) A + B = B + A (b) A.B = B.A

2. Associative Law (a) A+(B+C)=(A+B)+C (b) A.(B.C)=(A.B).C
3. Distributive Law (a) A.(B+C)=A.B+A.C
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2a. (i) NAND Implementation

2b. (i) NOR Implementation

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4. Algebraic Simplification

• A Boolean expression is translated to another form with less

number of terms and operations.
• A logic circuit for the simplified Boolean expression performs
the identical function with fewer logic components as
compared to its original form.
• Additionally, the simplified Boolean expression when
implemented to a logic circuit is reliable with a reduced cost.

Examples
(REFER NOTES)
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Summary

Combinational Logic Circuits

• Circuit whose OUTPUT is dependent only on the state of its
input. The OUTPUT is a pure function of the present input.
Does not depend on the past values.
• Examples: Adders (Half & Full), Multiplexer and Decoder
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Adder
An adder is a device that will add together two bits and give the
result as the output.

There are two kinds of adders - half adders and full adders.

A half adder just adds two bits together and gives a two-bit output.

A full adder adds two inputs and a carried input from another adder,
and also gives a two-bit output.

• Forms an arithmetic SUM of TWO bits.

Half - Adder • The circuit adds two binary variables, yields a carry but
does not accept carry from another circuit(adder).
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Full Adder
• Forms the arithmetic sum of THREE bits.
• Full Adder is the adder which adds three inputs and produces
two outputs.
• The first two inputs are A and B and the third input is an input carry, Ci.
• The output carry is given as Co and the normal output as S which is SUM.

Full - Adder
It is observed from the truth table that C0=1 for rows which
have two 1’s otherwise it is 0.

Its Boolean Function is

S =A B C
C0=AB+BCi+CiA
It can be implemented by three AND and one OR gates. S=1
for rows with one 1 and three 1’s., i.e odd number of 1’s. its
implemented by a three input XOR.
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LATCH:
Latches are constructed from Logic gates
•

Memory element
•

Stores ‘1’ bit of data

•

No clock
•

NAND – SR Latch

• The NAND gate latch or simply latch is a basic FF.

• The inputs are set and clear (reset) and complementary
outputs Q and 𝑸
• The inputs are active low, that is, the output will change
when the input is pulsed low.
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NAND- SR Latch (If Any input = 0, Output =1)

1 1
0 0
1

1 0 1
0 1
If S= 1 & R=0 If S= 1 & R=1
then Q= 0; 𝑸 = 1 then Q= 0; 𝑸 = 1(No change)
0 1
1 0 1

1 0 0

1 1
If S= 0 & R=1 If S= 1 & R=1
then Q=1; 𝑸 = 0 then Q=1; 𝑸 = 0 (No change)

NAND- SR Latch (If Any input = 0, Output =1)

0

1
If S= 0 & R=0
then Q=1; 𝑸 = 𝟏 (Invalid condition)

1 1

0
TRUTH TABLE

NAND SR LATCH
S R Q 𝐐
0 0 Invalid condition
0 1 1 0
1 0 0 1
1 1 No Change (Memory)
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Summary NAND- SR Latch

– SET = RESET = 1. Normal resting state, outputs remain in state prior to input.
– SET = 0, RESET = 1. Q will go high and remain high even if the SET input goes low.
– SET = 1, RESET = 0. Q will go low and remain low even if the RESET input goes low.
– SET = RESET = 0. Output is unpredictable because the latch is being set and reset at the
same time.
NAND SR LATCH
S R Q 𝐐
0 0 Invalid condition
0 1 1 0
1 0 0 1
1 1 No Change (Memory)

NOR- SR Latch
• The NOR latch is similar to the NAND latch except that the Q and Q’
outputs can be reversed or SET & RESET can be reversed.
• The SET and RESET inputs are active high, that is, the output will
change when the input is pulsed high.
• In order to ensure that a FF begins operation at a known level, a pulse
may be applied to the SET or RESET inputs when a device is powered
up.
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NOR- SR Latch (If any input=1, the Output=0)

1 0 0 0
1

0 1
0
0 1
If R= 1 & S=0 If R= 0 & S=0
then Q= 0; 𝑸 = 1 then Q= 0; 𝑸 = 1(No change)
0 1 0 1
0

1
1 0 0
0
If R= 0 & S=1 If R= 0 & S=0
then Q= 1; 𝑸 = 0 then Q= 1; 𝑸 = 0 (No change)

NOR- SR Latch (If any input=1, the Output=0)

TRUTH TABLE
1 0 NOR SR LATCH
S R Q 𝐐
0 0 No Change (Memory)
0 0 1 0 1
1 0 1 0 1 0
If R= 1 & S=1 1 1 Invalid condition
then Q= 0; 𝑸 = 0 (Invalid)

• The above analysis yields contradictory results

• Hence, R=1, S=1 is an invalid and forbidden state
• R-S cannot be used when both the input are at logic 1
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Summary NOR- SR Latch

– SET = RESET = 1. Normal resting state, outputs remain
in state prior to input.
– SET = 0, RESET = 1. Q will go low and remain high
even if the SET input goes low.
– SET = 1, RESET = 0. Q will go high and remain low even
if the RESET input goes low.
– SET = RESET = 0. Output is unpredictable because the
latch is being set and reset at the same time.
NOR SR LATCH
S R Q 𝐐
0 0 No Change (Memory)
0 1 0 1
1 0 1 0
1 1 Invalid condition

Sequential Circuits
A circuit whose output depends on the order or the timing of the inputs.

• Is a combinational circuit to which

storage elements are connected
to form a feedback path.
• The outputs are a function NOT
ONLY of the inputs, but also of the
PRESENT state of the storage
elements.
• Eg: flip-flop, register, counter,
clocks, etc.
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FLIPFLOP:
Are always clocked.
•

Constructed from latches from along with an

•

additional clock signal.

Slow compared to Latches.
•

RS Flip Flop

• RS Flipflop with NAND gates

• Flipflops are clock edge
triggered.
• SR Latch with a control input
‘CLOCK’ is called a SR flip flop.
• ‘CLK’ acts as an ENABLE Signal.
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RS Flip Flop 1

NAND SR LATCH
S* R* Q 𝐐 − 𝐛𝐚𝐫
0 0 Invalid condition
If CLK = 0; S = X, R = X
0 1 1 0 Q & 𝐐 = No Change(Memory)
1 0 0 1
1 1 No Change (Memory)

RS Flip Flop 0 1

0 1

NAND SR LATCH
S* R* Q 𝐐 − 𝐛𝐚𝐫
0 0 Invalid condition
If CLK = 1; S = 0, R = 0
0 1 1 0 Q & 𝐐 = No Change(Memory)
1 0 0 1
1 1 No Change (Memory)
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RS Flip Flop 0 1

1 0

NAND SR LATCH
S* R* Q 𝐐 − 𝐛𝐚𝐫
0 0 Invalid condition
If CLK = 1; S = 0, R = 1
0 1 1 0 Q =0 & 𝐐 =1
1 0 0 1
1 1 No Change (Memory)

RS Flip Flop 1 0

0 1

NAND SR LATCH
S* R* Q 𝐐 − 𝐛𝐚𝐫
0 0 Invalid condition
If CLK = 1; S = 1, R =0
0 1 1 0 Q =1& 𝐐 =0
1 0 0 1
1 1 No Change (Memory)
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RS Flip Flop 1 0

1 0

NAND SR LATCH
S* R* Q 𝐐 − 𝐛𝐚𝐫
0 0 Invalid condition
If CLK = 1; S = 1, R =1
0 1 1 0 Q & 𝐐 = Invalid Condition
1 0 0 1
1 1 No Change (Memory)

RS Flip Flop TRUTH TABLE

CLOCK S R Q 𝐐

0 x x No change
(Memory)
1 0 0 No change
(Memory)
1 0 1 0 1
1 1 0 1 0
1 1 1 Invalid

– SET = RESET = 0, CLK is not applied- Output do not change(Memory)

– SET = RESET = 0 , CLK is applied- Output do not change(Memory)
– SET = 0, RESET = 1, CLK is applied- Q will go low and Q- bar will go high
– SET = 1, RESET = 0, CLK is applied- Q will go high and Q- bar will go low
SET = RESET = 1, CLK is applied referred to Invalid conditions.
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