This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TBCAS.2019.2947694, IEEE
Transactions on Biomedical Circuits and Systems
Electrocardiogram and Phonocardiogram
Monitoring System for Cardiac Auscultation
Shuenn-Yuh Lee, Senior Member, IEEE, Peng-Wei Huang, Student Member, IEEE, Jia-Ren Chiou,
Chieh Tsou, Student Member, IEEE, Yu-Yi Liao, and Ju-Yi Chen
Abstract—Heart-sound auscultation is a rapid and fundamental
technique used for examining the cardiovascular system. The main
components of heart sounds are the first and second heart sounds.
Discriminating these heart sounds under the presence of additional
heart sounds and murmurs will be difficult. To recognize these
signals efficiently, this study proposes a monitoring system with
phonocardiogram and electrocardiogram. This system has two key
points. The first is chip implementation, including capacitor coupled
amplifier, transimpedance amplifier, high-pass sigma–delta
modulator, and digital signal processing block. The chip in the
system is fabricated in 0.18 µm standard complementary metal–
oxide–semiconductor process. The second is a software application
on smartphones for heart-related physiological signal recording,
display, and identification. A wavelet-based QRS complex detection
algorithm verified by MIT/BIH Arrhythmia Database is also
proposed. The overall measured positive prediction, sensitivity, and
error rate of the proposed algorithm are 99.90%, 99.82%, and
0.28%, respectively. During auscultation, doctors may refer to these
physiological signals displayed on the smartphone and
simultaneously listen to the heart sounds to diagnose the potential
heart disease. By taking advantage of signal visualization and
keeping the original diagnosis procedure, the uncertainty existing in
heart sounds can be eliminated, and the training period to acquire
auscultation skills can be reduced.
Index Terms—Bio-signal acquisition, QRS complex detection,
phonocardiogram, electrocardiogram, system on chip, cardiac
auscultation, wearable device
I. INTRODUCTION
CARDIOVASCULAR diseases (CVDs) are the leading
cause of death globally. According to reports [1] from the
World Health Organization, an estimated 17.9 million people
died from CVDs in 2016. It is a horrible amount because it
exceeded 30% of all global deaths. To prevent such a
worldwide killer, regular physical examination is important.
Typically, heart-sound auscultation is a rapid and common
method used in examining the cardiovascular system. As
illustrated in Fig. 1, the aortic, pulmonic, tricuspid, and mitral
areas are four main regions of interest for cardiac auscultation
This research was supported in part by the Taiwan Semiconductor
Research Institute and the Ministry of Science and Technology (MOST),
Taiwan, R.O.C., under Grants MOST 107-2218-E-006-034, MOST 108-
2622-8-006-004-TE2, and MOST 107-2514-S-006-008 and South Taiwan
Smart Biomedical Industrial Clusters under Grant AZ-13-05-28-107.
(Corresponding authors: Shuenn-Yuh Lee and Ju-Yi Chen)
S. Y. Lee, P. W. Huang, J. R. Chiou, C. Tsou, and Y. Y. Liao are with the
Electrical Engineering Department of National Cheng Kung University, No.
1 University Rd., Tainan, 70101, Taiwan (e-mail: ieesyl@mail.ncku.edu.tw,
lookonthebrightside_j@hotmail.com).
J. Y. Chen is with National Cheng Kung University Hospital, Tainan,
Taiwan (e-mail: juyi@mail.ncku.edu.tw).
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Aortic area Pulmonic area
Second intercostal space
Tricuspid area
Fourth intercostal space
Fifth intercostal space
Mitral area
Right of the Left of the
sternum sternum
Fig. 1. Four main regions of cardiac auscultation [2].
[2]. Given that heart sounds are caused by the closure of
different valves, heart murmurs indicate several valvular heart
diseases such as valvular stenosis and regurgitation.
The heart sounds mainly comprise the first (S1) and second
heart sounds (S2). Efficiently recognizing S1 and S2 under the
influences of additional heart sounds and murmurs is difficult.
After the discrimination of S1 and S2, the diseases related to the
additional heart sounds and murmurs can be diagnosed.
Therefore, the accuracy of auscultation relies on the doctor’s
experience. However, there exist some obstacles to the
accumulation of experience and education. For example,
individuals may have different auditory sensitivity. Moreover,
the distinction between various kinds of heart murmurs is hard
to describe.
To assist doctors in making diagnoses more rapid and
accurate, this study proposes a system capable of measuring the
phonocardiogram (PCG), heart-sound waveform, and
electrocardiogram (ECG) simultaneously. The reason why
ECG measurement is adopted in the proposed smart
stethoscope system is because the systolic and diastolic phases
of the heart can be easily distinguished. Therefore, the
recognition of S1 and S2 is more reliable. During auscultation,
doctors may refer to these two signals displayed on the
smartphone to diagnose the potential heart disease. The
smartphone will concurrently play the heart sounds for keeping
the original diagnosis procedure. By taking advantage of signal
visualization, the uncertainty of heart sounds can be eliminated,
and the training period to acquire auscultation skills can be
reduced. Furthermore, the measured signals can be stored on
the smartphone and uploaded to a cloud server. These materials
can be utilized as educational resources to improve the learning
efficiency by replaying the recorded waveforms and heart-
sound audio.
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Transactions on Biomedical Circuits and Systems
CHIP
ECG CCIA HPSDM UART Clock
Interface Divider
Decimation Filter
PCG TIA HPSDM
Digital
Signal Acquisition Block Processing Block
Bluetooth
Software-based
User
Signal
Processing
Interface
Software Design Smart Phone
Fig. 2. System diagram of the smart stethoscope.
The block diagram of the whole system is shown in Fig. 2.
In the chip implementation, it is a sensing circuit for the
synchronization of ECG and PCG measurements. According to
the integration of PCB system board, the real-time monitoring
function can be achieved with the wireless transmission of BLE
module. At the software side, a wavelet-based beat detection
algorithm with good performance is proposed. The mechanism
of peak insertion and deletion based on the detection of the
possible P and T waves according to advice by cardiologist in
NCKU hospital is added in the proposed algorithm. In addition,
the ultimate application scenario of the proposed system is
different from the existing product. Combining the ECG
sensing patch with the microphone-equipped stethoscope, the
reliability and quality of auscultation can be improved. Also,
detaching the stethoscope, the ECG patch itself can be applied
to the patients who needs long-term monitoring. Since a low
power and wearable device is required for long-term healthcare,
the chip implementation is beneficial to such applications. The
miniaturization of system can make the sensing device easier to
wear. The reduction of power consumption accomplishes a
better battery life. For the chip design in the proposed system,
the 2-channel signal acquisition consumes about 800 µW. Also,
the power consumption is only 60 µW in the single-lead ECG
channel. In contrast with the chip implementation, ECG sensing
circuits integrated from discrete components often cost about
several mWs depending on the specification. These advantages
gained from chip design help to enhance the feasibility of long-
term healthcare and to minimize the inconvenience brought
from the consecutive monitoring. For offline data collection,
switching off the BLE transmission function and adding a SD
card on the PCB system board can further extend the battery
life.
For designing such a wearable monitoring system,
establishing the appropriate and efficient specification is the
first but fundamental step. It may directly influence the finished
products in terms of performance, practicability, and battery
selection. Hence, investigating the properties of input signals is
the primary task. The main frequency band of heart sounds
ranges between 20 Hz and 150 Hz [3]. Furthermore, on the basis
of frequency distribution analysis in several types of heart
sounds [4], most frequency components are under 200 Hz. On
the other hand, the ECG bandwidth is around 0.01–250 Hz with
0.5–4 mV amplitude range [5]. Another analysis [6] shows that
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the ECG band in clinical usage is between 0.05 Hz and 100 Hz.
To reduce the system design’s complexity, the acquisition
bandwidth of the proposed system for heart-related signals is
Bluetooth set as 200 Hz. The sampling and transmission for both signals
Module are all synchronized. If the bandwidth and the sample rate are
set differently for each signal, solving the problems of clock
domain crossing and transmission will make the system more
complicated. Moreover, the IP reuse in the same specification
of two HPSDMs can reduce the effort on system-level design.
The ECG sensing channel can suppress the influences of DC
Module offset and common mode AC interference. The removal of
baseline wander and motion artifacts are primarily implemented
in the software side.
The rest of the paper is organized as follows. Section II
describes the major concerns of on-chip circuit design. Section
III discusses the implementation of the whole system and the
beat detection algorithm in software application. Section IV
elaborates the results of algorithm testing and system
measurement. Finally, Section V draws the conclusions.
II. ON-CHIP CIRCUIT DESIGN
The analog front end (AFE) in this system has two channels
that can acquire ECG and PCG signals simultaneously. The
main difference between these channels is the front-end
amplifier. The first channel uses capacitor coupled
instrumentational amplifier (CCIA) to magnify the voltage-type
ECG signal from the body appropriately. The second channel
uses transimpedance amplifier (TIA) to convert the heart-sound
current-type signals received from microphone to voltage-type
signals. These amplified signals will then be digitalized by an
analog-to-digital converter (ADC) and sent into the digital
circuit for further processing. Chopper stabilization technique
is applied on each of the amplifiers to prevent low-frequency
noise during the complementary metal–oxide–semiconductor
(CMOS) process. The whole chip can be organized as a CCIA,
TIA, high-pass sigma–delta modulator (HPSDM), decimation
filter, and universal asynchronous receiver/transmitter (UART)
transmission interface.
A. Capacitor Coupled Amplifier
The block diagram of the capacitor coupled amplifier
employed in the proposed system is shown in Fig. 3(a). In this
CCIA, the operational amplifier is realized in the form of
differential difference amplifier (DDA) illustrated in Fig. 3(b).
The DDA contains two inputs that can separate the input signal
path from the feedback path; thus, the input of CCIA would not
suffer from large loading caused by the feedback capacitor.
The two feedback capacitors C1 and C2 define the signal gain
of the CCIA, and the feedback resistor Mr in parallel with C2 is
used to determine the DC point of the feedback input pair.
However, this feedback resistor results in a low-frequency pole
and zero in the closed-loop transfer function. The transfer
function is derived as follows:
 1 
Gm1  s  
 Rpseu  C1  C2  
ACL  s    (1)
G C Gm 2
Cc s 2  m 2 2 s 
C1  C2 Rpseu  C1  C2 
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Transactions on Biomedical Circuits and Systems

C1 C2 On Chip
Rf
Pseudo
Resistor Rb
Cu

CME-1539-100LB
Mr Vout+
Mr
Vcm Vout-

C1 C2
Rf
Vout+ (a)
Vb1
Vin-
Vout-
+
Vin
Vin+ Vin-
(a)

Vb1 Vout+ Cc Cc Vout-

Vb2
Vi1+ Vi1- Vi2+ Vi2-
M1 M2 M3 M4

Vout+ Cc Cc Vout-
Vb2 Rf Rf

(b)
Fig. 5. (a) Block diagram of TIA, (b) schematic of TIA without chopper.
C2 C2
C1 band frequency range of CCIA is from 100 Hz to 60 kHz.
According to process corners simulation with five models, the
Rpseu Rpseu
simulated CMRR is higher than 68 dB and the PSRR is higher
(b) than 54 dB.
Fig. 3. (a) Block diagram of CCIA, (b) schematic of CCIA without B. TIA
chopper.
Unlike the ECG signal, the heart-sound signals are first
received by the microphone, which transforms the acoustic
|ACL(s)| signal into electronic signal. In this system, the electret
Gm1  C1  condenser microphone (CME-1538-100LB) fabricated by CUI
1  
Gm 2  C2  Inc. is utilized. The electret condenser microphone consists of
a microelectromechanical system (MEMS) microphone and a
Midband
Gm1 field-effect transistor (FET) impedance converter. Driven by
Gm 2 the MEMS microphone, the FET impedance converter extracts
f the current from output loading. Accordingly, a TIA should be
fz fp1 fp2
used to convert the current-type signals from the microphone
Fig. 4. Frequency response of CCIA. into voltage-type signals, so that the following HPSDM can
TABLE I operate normally.
POLE ZERO LOCATION OF CCIA The adopted microphone is single-ended; however, the
f zero , 𝑓 f pole ,low , 𝑓 f pole,high , 𝑓 conventional amplifier in CMOS process is in fully differential
1 1 1 1 1 Gm 2 C2 mode. Fig. 5(a) shows the implementation of the microphone
incorporated with TIA, where Rb is the bias resistor of
2 R pseu  C1  C 2  2 R pseu C 2 2 Cc C1  C2
microphone, Cu is the DC block capacitor, and Rf is the
feedback resistor of TIA. The conventional two-stage
where Gm1 and Gm2 are the transconductance of input pair M1,2
operational amplifier is used in this TIA as shown in Fig. 5(b).
and M3,4, respectively, Cc is the compensation capacitor of the
One of the input terminals is connected to the microphone, and
DDA, and Rpseu is the resistance of the feedback resistance. The
the other terminal is connected to the common mode reference
frequency response is shown in Fig. 4, and the location of poles
voltage. Similarly, a chopper is inserted between the
and zeros are listed in Table I. After chopping, the signal
microphone and the TIA to reject the low-frequency noise in
frequency is located within the mid-band region. The low-
TIA. Such connection can receive single-ended current signal
frequency pole–zero pair caused by the feedback resistor should
from the microphone by a fully differential TIA, and the gain is
be designed low enough to avoid affecting the signal band.
2Rf instead of Rf.
Therefore, the feedback resistor is implemented by pseudo
Fig. 6 shows the diagram of TIA for derivation of frequency
resistor [7] to realize extremely large resistor without using a
response, where Cp is the parasitic capacitor of TIA. Assuming
large area resistor. According to the simulation results, the mid

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Transactions on Biomedical Circuits and Systems

CP Rf Zf Second Stage

b1
Ix First Stage

Vout+ X(z) g1 H(z) g2 H(z) g3 H(z)

Iin A(s)
Vout- a1 a2 a3
Ix

CP Rf Zf Summing Stage
1-bit
fs=2fchopper
Fig. 6. Circuit diagram of TIA for derivation of frequency response. quantizer
DAC Y(z)

TABLE II
Fig. 7. System block of the SDM.
POLE LOCATION OF TIA
f p1 f p2 TABLE III
1 1 1 1 COEFFICIENTS OF EACH PATH
2 2Cp R f 2 (1  A0 )0 a1 2.5 g1 0.333
a2 1.25 g2 0.667
that the operational amplifier is designed appropriately, the a3 1.25 g3 0.179
open-loop transfer function is listed below:
b1 0.01
A0
Aopen  s  
s (2) CH
1 Φ2 Φ1
0
where A0 is the DC gain and ω0 is the dominant pole. The value Φ1 Φ2
of unity-gain bandwidth (UGB) ωt is the transconductance of -1
input pair divided by the compensation capacitor Cc. According CI
to the above assumption, the closed-loop transfer function of
TIA in Fig. 6 can then be derived as follows:
CS
  Φ1 Φ2
Vin
2R f  A 1  Vout
ACL  s    0  (3) Φ2 Φ1
1  s 2C p R f 1  A0 1  s 
 1  A0  0 
 Fig. 8. First-order high-pass integrator.
Because the feedback resistor is not in parallel with a capacitor,
the transfer function does not contain any zeros but has two effective number of bits increases by 0.5 bits when the OSR
poles fp1 and fp2 associated with parasitic capacitor and UGB of doubles. Except for the oversampling, the SDM behaves as a
the operational amplifier, respectively. The pole location is filter, so that the quantization noise can be suppressed in the
listed in Table II. Given that the TIA is operated in low signal band but increased in the out-of-signal band. In this way,
frequency and the compensation capacitor is usually larger than the in-band quantization noise would be exponentially inversely
parasitic capacitor, fp2 is considered as the dominant pole that is proportional to the OSR.
controlled by the UGB of operational amplifier to achieve the Fig. 7 shows the system block of the 3rd multi-feedforward
compensation effectively. In the simulation results, the cutoff SDM with a local feedback, and the noise transfer function is
frequency range is about 100 kHz which is much higher than listed below. The related coefficients of each path are illustrated
the chopper frequency 25.6 kHz. The PSRR can achieve greater in Table III.
than 135 dB under the single-ended TIA. 𝑌 𝑧 1 𝑏𝑔 𝑔 𝐻
𝑋 𝑧 1 𝑎 𝑔𝐻 𝑎 𝑔𝑔 𝑏𝑔 𝑔 𝐻 𝑔𝑔 𝑔 𝑎 𝑎 𝑏 𝐻
C. HPSDM
(4)
The sigma–delta modulator (SDM) is widely used in ADC
with high resolution. It is especially suitable for low- and mid- If the signal is chopped back to the original frequency before
band-frequency application. Moreover, the specifications of ADC, the offset and flicker noise of pre-amp would be
circuits such as operational amplifier and quantizer realized in modulated to the chopping frequency, and additional analog
the SDM can be much more relaxed. filter is required. Under the circumstances, the utility of signal
The ability of noise shaping is the main difference between bandwidth is inefficient. Therefore, the HPSDM is more
SDM and conventional Nyquist rate ADC. Given that the attractive in such application to digitalize the chopped signal
quantization noise is normally distributed between the half and retain bandwidth efficiency. The high-pass noise transfer
sampling frequency, the in-band quantization noise is linearly function is obtained by turning the variable in the low-pass
inversely proportional to the over sampling ratio (OSR), and the noise transfer function from z to −z. Thus, the central frequency
is shifted from 0 to fs/2. Accordingly, the low-pass integrator

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Transactions on Biomedical Circuits and Systems
CI
Cp CS
Φ1 CS VX
Φ2
Vin
Vout
Φ2 kCS Φ2 Φ1
Fig. 9. Capacitive-T integrator.
should be transformed into high-pass integrator [8] shown in
Fig. 8, and the transfer function is derived as follows:
𝐻 𝑧
where the capacitance of CH and CI are identical in this design.
From Table III, the coefficient b1 is much smaller than other
coefficients. This will lead to a very small capacitor to become
severely influenced by the parasitic capacitors. Fig. 9 shows a
capacitive-T integrator that can implement a very small
coefficient in an integrator and reduce the effect of parasitic
capacitor. The transfer function is shown below:
C 1  z  1
H  z   s  1 
CI k  2  P  1  z 
C (6)
Cs
where k is the capacitance ratio in the T capacitor network and
Cp is the parasitic capacitor. This result reveals that the
corresponding sampling capacitor Cs is reduced by k+2+Cp/Cs
times.
To sum up, the main features in the overall AFE architecture
are flicker noise suppression, low power consumption and high
bandwidth usage efficiency. First of all, in order to resist the
flicker noise, the chopper mechanism is adopted in the design
of AFE. In the conventional chopper-based architecture used in
LPSDM system, a severe problem of ripple effect is
encountered when adding the output chopper stage of pre-
amplifier. This ripple may make the sensed bio-signal saturated.
In general, a well-designed filter needs to be inserted afterward
to solve this problem in the conventional structure. Such a
solution leads to extra efforts and power consumption. On the
other hand, if the LPSDM is implemented between the pre-amp
and output chopper stage, the extra requirement for its
bandwidth is at least twice the frequency of chopper. To
simplify the conditions mentioned above, several adjustments
are required for AFE structure optimization. In the proposed
system, the output chopper stage is implemented in digital
signal processing block to avoid the design of high-end analog
filter. In addition, the HPSDM architecture is directly utilized
to analyze the output signal of CCIA for better efficiency in
bandwidth usage. Since the input bio-signal is chopped to high
frequency to prevent the interference of flicker noise, the
modulated-signal band is completely reserved by the HPSDM
with the bandwidth of 200 Hz. Compared with LPSDM system,
the output chopper stage and corresponding analog filter are no
longer needed in this architecture. The proposed AFE system
can suppress the DC offset and flicker noise through a simpler
architecture. From the viewpoint of overall sensing channel, the
chopper-based pre-amplifier with HPSDM providing high-pass
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614.4
Clock Divider
kHz
Cascaded
2-ch
Chopper
Integrator- Compensation
IIR Filter Equalizer
SDM Data Comb Filter
Filter
Decimation Filter
FIFO
UART Digital Biosignal
UART TX
Interface
Baud Rate (38400)
Fig. 10. Block diagram of DSP block.
noise transfer function is therefore much easily implemented
and still provides sufficient accuracy as compared with
(5) conventional AFE structure. The complete design flow [9] from
system stability to circuit implementation is introduced. Other
nonideal effects such as finite and nonlinear gain, bandwidth of
operation amplifier, thermal noise of switch, and coefficients of
variation in the modulator should be carefully considered.
Following the design flow, the modulator can be optimized by
applying the minimum specification of the operational
amplifier.
D. Digital Signal Processing (DSP) Block
The proposed DSP unit mainly serves as the clock divider,
decimation filters, and UART package generator. The detailed
block diagram is shown in Fig. 10. The clock divider triggered
by the on-board voltage-controlled oscillator derives all the
clocks for the demand of AFE and DSP blocks. Given that the
HPSDM in AFE plays the role of ADC, the digital circuit will
then start to receive the single-bit digital stream after the clock
divider is functioning. Two following decimation filters are
applied for different bio-signals: ECG and PCG. These two
decimation filters are identical because the target specifications
for each application are the same. However, how do we
implement these decimation filters considering that many
approaches are available? A cascade structure is adopted to
achieve the goal of low power consumption. The four stages are
as follows: a cascaded integrator–comb (CIC) filter, a
compensation filter, an infinite impulse response (IIR) filter,
and an equalizer [10]-[13]. A CIC filter is the first stage because
it can fulfill the high decimation ratio in a simple concept. The
z-domain transfer function is listed below [10]:
1 𝑍
H z 2 , 𝑃 𝑀 𝑙𝑜𝑔 𝑅 (7)
1 𝑍
where M represents the order of CIC filter and R is the
decimation ratio. The whole down sampling ratio (DSR) of the
proposed decimation filter is 128; thus, the decimation ratio (R)
of the CIC filter is set at 32. The remaining four DSRs are
accomplished by the following filter stages. To attain sufficient
attenuation of stopband, the order M is set at 4. Although the
CIC filter can achieve high decimation ratio, the passband will
have some gain loss. The compensation filter is applied to
compensate the loss and make the passband much flatter. The
compensation filter is realized by equiripple finite impulse
response (FIR) filter. After placing the signal frequency much
closer to the destination, a sharp transition band filter should be
constructed. Therefore, the third stage is an IIR filter. The IIR
filter has lesser coefficients and shorter delay time than the FIR
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1 0 LSB MSB
Start
8-bit Data
Bit
Fig. 11. UART 8-N-1 format transmission diagram.
filter when achieving the same specification. However, the non-
linear phase is a problem for the IIR filter. The solution to this
phase problem is to append an equalizer behind the IIR filter.
The equalizer compensates and minimizes the max difference
in group delay. The structure of the decimation filter is marked
in the blue block of Fig. 10. After passing through several stages
of signal down sampling and processing, the digitized ECG and
PCG signals are finally acquired.
For the purpose of transmitting the physiological information
to the on-board Bluetooth module, the data should be
rearranged into a common communication standard. These 2-
channel 16-bit signals mentioned above are sampled
synchronously. After adding an 8-bit trailer, the whole data
length is 40 bits. The data rate from the output of decimation
filter is 400 Hz; thus, the equivalent bit rate is 16 Kb/s. To
minimize the number of total output pads, the UART approach
is selected to transmit the data. The UART package generator
is implemented to divide the output data into a UART 8-N-1
format [14], signifying that a start bit 0 and a stop bit 1 will be
added for each packet (byte). That is, the data rate is now
increased by 25% and reaches 20 Kb/s. The UART
transmission diagram is shown in Fig. 11. Given that the
common baud rates are 9600, 19200, 38400, 57600, and 115200
Hz, it is adequate to choose 38400 in the proposed system in
accordance with the preceding calculation. When waiting for
transmission, the data at each sample point needs to be reserved
temporarily. A circular first input first output (FIFO) buffer
rather than shifting register is introduced to save the
unnecessary dynamic power dissipation.
The 2-channel equivalent data bit rates of HPSDMs and
decimation filters are 102.4 and 16 Kb/s, respectively. Both
these digital signals can be packaged into UART format. Why
are the outputs of decimation filters eventually selected? If the
outputs of HPSDMs are adopted, the decimation filter can be
removed. Under these circumstances, the power consumption
of the chip is certainly lower. However, from the perspective of
the system level, higher bit rate infers higher RF transmission
power. The transmission power commonly dominates the
power consumption of the overall system. It is a more
economical decision to the system when the decimation filter is
employed. Ignoring the 25% increment of transmission
overhead, it can save up to 6.4 times the bandwidth than using
the output of HPSDMs.
III. APPLICATION IMPLEMENTATION
A. Firmware Design
After setting the baud rate, the on-board Bluetooth module
successfully receives the ECG and PCG signals via UART
packages. Given that the total bit rate of the proposed system is
only up to 16 Kb/s, Bluetooth Low Energy (BLE) is the best
option to this application. Compared with Bluetooth Basic
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Transactions on Biomedical Circuits and Systems
TABLE IV
1 BLUETOOTH VERSION COMPARISON [15][16]
Bluetooth Bluetooth
Stop Low energy BR/EDR
Bit
Setup time <6 ms 100 ms
Data rate 125 Kb/s to 2 Mb/s 1 Mb/s to 3 Mb/s
~0.01x to 0.5x
Power consumption 1 (reference value)
of reference
Point-to-point
Network topologies Broadcast Point-to-point
Mesh
Rate/Enhanced Data Rate (BR/EDR), low power consumption
and short connecting latency are characteristic of BLE. Some
key features of the two different technologies are listed in Table
IV [15][16]. The communication range is not a primary issue to
this system because the distance between the proposed device
and smartphone is only a few meters, and both technologies can
meet the need. Although BLE has lower data rate, its theoretical
value is still far beyond the least demand to keep persistence of
vision. In this case, the transmission period needs to be
determined properly in order to correspond with the signal data
rate, communication firmware standard, and acceptable user
experience.
A firmware operation routine and a custom BLE profile are
implemented to serve as stable bridge of communication.
Playing the role of a peripheral/server, the proposed hardware
system needs to push the processed data to the client. The
notification operation is chosen and given that this application
works at higher transfer rate. A BLE setting parameter called
maximum transmission unit (MTU) size directly affects the
data length of package per notification operation. The MTU
size remains at its default setting of 23 for wider device support.
Each notification package length is 20 bytes. According to the
previous calculation, the physiological signals fill the package
every 10 ms. However, this interval may not be an appropriate
value for establishing every connection stably. To determine the
suitable connection interval matching with data rate is the main
concern of firmware implementation. The minimum connection
interval varies from the adopted BLE chips in smartphones to
the different mobile operating systems. Some mobile operating
systems have several listed rules [17][18] to assist in
establishing and retaining the connection successfully. These
rules may be changed or updated at intervals. After many
practical experiments, the minimum connection interval needs
to be greater than 20 ms for the phones tested. A small buffer is
needed to hold the data and waits for the next notification. After
converting the UART transmitter data into the corresponding
characteristic value attributes of custom BLE profile, the BLE
module can send all the information to smartphones by
complying with the setting suggestion of connection parameters.
Through smartphones, real-time bio-signal monitoring, offline
data storage, and further physiological condition analysis can
then be conducted.
B. Software Signal Processing and Beat Detection Algorithm
Developing real-time mobile applications for wearable
sensors has become a popular topic since the concept of mobile
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TBCAS.2019.2947694, IEEE
Transactions on Biomedical Circuits and Systems
BLE
Receiver
Wavelet
Transform
Data Median
Formatting Filter
PCG signal Filtering
Filtering
ECG signal Window-based
Max Searching
Heart Possible QRS
Sound Display
Beat
Detection
P/T Wave Configuration
R-R Interval
Analysis
Player Detection Extraction
Recording
/
QRS
Confirmation
Uploading
Software Main Functions Beat Detection Algorithm
Fig. 12. Block diagram of software application.
healthcare and telemedicine has been widely discussed and
researched during recent years. However, it is never an easy
task. First, signal monitoring with real-time data analysis is a
fundamental capability. Furthermore, noise interference is an
unavoidable challenge to all portable and wearable applications.
The tolerable noise level determines the requirement of
suppression efforts. Both hardware circuits and mobile software
have their limitations. Choosing the suitable system structures
and filtering methods can reach the balance economically. In
addition, the operation complexity of signal discrimination is
also an important index. Pursuing a simpler approach and better
analysis results are the ultimate goal, but it often turns out to be
a trade-off. Last but not least, a good user experience including
friendly application interface, short operation latency, and
robust analysis is the comprehensive score of the system.
The concise signal processing flow of software based on the
mobile operating system is shown in the left side of Fig. 12.
After receiving the 2-channel heart-related physiological
information, the data format is first rearranged into readable
values. Then, low-pass and band-pass FIR filters are added to
retain the major frequency band of ECG and PCG signals,
respectively, and reduce the interference of out-of-band noise.
The filter parameters are set adequately for signal monitoring
[6]. The cleaner ECG/PCG signals are displayed
simultaneously and synchronously on the screen for doctors to
read. These waveforms are stored in the smartphone’s file
system, and the data files can be uploaded to a cloud server
when a network is available. During monitoring, the PCG signal
is written into the audio buffer and played; thus, the integration
of hearing and vision is accomplished. At the same time, the
proposed ECG beat detection algorithm is carried out. Once the
QRS complex is detected, the systolic and diastolic phases of a
heart are distinguishable. The method of 2-channel cross-
reference is beneficial for a rapid diagnosis.
Given that R peak detection is fundamental to arrhythmia
classification, a reliable and efficient discrimination method is
essential to heart-related healthcare system. The block diagram
of the proposed beat detection algorithm is shown in the right
side of Fig. 12. The 1-D Haar discrete wavelet transform (DWT)
is adopted in the main preprocessing stage for its low
complexity. DWT uses the scaling and wavelet filter to
decompose the signal into low- and high-frequency components.
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The time and frequency resolutions are affected by the
decomposition level of wavelet. In the proposed system, the
ECG signal is decomposed by a 4-level Haar DWT operation.
The output wavelet coefficient W4 is fed into a median filter for
further noise suppression. Then, a window-based maximum
value searching is employed to select the R peak candidates.
The window length is determined by the maximum heart beats
per minute (BPM) value of adults. For a digital ECG signal with
400 Hz sampling rate, a 109-point window is enough to detect
the heartbeats under 220 BPM [19]. Given that the window-
based maximum value searching serves as the beat candidate
selection, the adaptive threshold mechanism is involved. The
location and value of the maximum larger than threshold are
output as the features of the candidate. Only these selected
candidates can participate in the updating of adaptive threshold.
If two continuous windows both detect its local max value, the
comparison between these two candidates will then be triggered.
The former will be output if the interval is longer than a window
length, and the output decision of the latter will be held over
until the next window is analyzed. However, if the interval
between these two candidates is smaller than a window length,
only the larger value will be output eventually. The detailed
procedures are presented in our previous work [20].
The MIT-BIH arrhythmia database [21], a prevailing
standard benchmark, is used to evaluate the proposed beat
detection algorithm. It is the excerpts of ambulatory ECG
recordings. The overall detection results are passable in most
conditions when original algorithm is applied. But the
performance decreases under the noisy coupling. In these
regions, if the noise can pass the threshold mechanism, the non-
R-peak noise will be recognized as R peak. So, the number of
false positives (FP) increases. Therefore, the endurance of noise
and artifacts is more essential when applying to a patient who
needs long-term monitoring. The proposed algorithm in this
manuscript is based on the previous work and the mechanism
of peak insertion and deletion is added. Trying to find the
possible P or T wave between R-R intervals is the fundamental
concept of the proposed method. Since the relations of P, R and
T waves can present the cardiac physiology, the duration and
interval reasonably need to follow some medical rules.
According to each output of the window-based maximum
searching, the current P wave and the former T wave can be
found between the current R peak and the former one in general
condition. Similarly, the following current T wave will appear
in a certain range. During the searching procedures, the
configuration of the current peak can be extracted. The peak
configuration, including the locations and the values of start
point, peak, wave trough, and end point, is recorded.
Combining the foregoing features with several past RR interval
(RRI), the decision, on whether the peak is a real QRS complex,
is made. If the current chosen peak is really a true R peak, some
physiology-oriented requirements, such as PR interval, QRS
duration or QT interval, should be satisfied. When the searching
on both P and T waves for current peak fails, this peak will then
be removed because it is determined as a large non-R-peak
artifact or a sharper T wave. Moreover, the missing R peak,
filtered by the adaptive threshold in original algorithm, may be
discovered during the P wave searching procedure. The
mentioned procedure is basically implemented by peak
searching with threshold method. For each discovered peak,
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Transactions on Biomedical Circuits and Systems

TABLE V TABLE VI
MIT-BIH DATABASE TESTING RESULTS PERFORMANCE COMPARISON WITH RECENT BEAT DETECTION SYSTEMS
AND METHODS
Record P+ Se ERR
TP FP FN Method Se (%) P+ (%)
No. (%) (%) (%)
100 2273 0 0 100 100 0 Gutiérrez-Rivas et al. (2015) [23] 99.54 99.74
101 1863 2 2 99.89 99.89 0.21 Phukpattaranont (2015)* [24] 99.82 99.81
102 2187 0 0 100 100 0 Sahoo et al. (2016)* [25] 99.71 99.72
103 2084 0 0 100 100 0
104 2228 4 1 99.82 99.96 0.22
Li et al. (2017) [26] 99.60 99.77
105 2562 27 10 98.96 99.61 1.42 Hou et al. (2018) [27] 99.32 99.45
106 2022 2 5 99.9 99.75 0.34 Lee et al. (2018) [20] 99.44 99.40
107 2133 0 4 100 99.81 0.19 Bashar et al. (2019)* [22] 99.94 99.95
108 1760 10 3 99.44 99.83 0.73
The proposed algorithm 99.82 99.90
109 2532 0 0 100 100 0
111 2123 1 1 99.95 99.95 0.09
*
Pure algorithm development
112 2539 0 0 100 100 0
113 1795 0 0 100 100 0
114 1877 5 2 99.73 99.89 0.37
115 1953 0 0 100 100 0
116 2390 1 22 99.96 99.09 0.95
117 1535 0 0 100 100 0 CCIA HPSDM
118 2278 2 0 99.91 100 0.09

1.99 mm
119 1987 1 0 99.95 100 0.05
121
122
1863
2476
0
0
0
0
100
100
100
100
0
0 DSP
123 1518 0 0 100 100 0
124 1619 0 0 100 100 0
200 2599 3 2 99.88 99.92 0.19 TIA HPSDM
201 1949 0 14 100 99.29 0.71
202 2135 0 1 100 99.95 0.05
203 2925 12 55 99.59 98.15 2.24
205 2645 2 11 99.92 99.59 0.49
207 1847 0 13 100 99.3 0.7 2.44 mm
208 2945 3 10 99.9 99.66 0.44 Fig. 13. Microphotograph of the proposed system.
209 3005 1 0 99.97 100 0.03
210 2640 1 10 99.96 99.62 0.41
212 2748 0 0 100 100 0
213 3251 0 0 100 100 0
214 2262 1 0 99.96 100 0.04 IV. E XPERIMENT RESULT
215 3362 0 1 100 99.97 0.03
217 2201 1 7 99.95 99.68 0.36 A. Testing Results on MIT-BIH Arrhythmia Database
219 2154 0 0 100 100 0 After the testing on the first channel in MIT-BIH arrhythmia
220 2048 0 0 100 100 0
221 2423 1 4 99.96 99.84 0.21
database, the experiment results are listed in Table V. Of note,
222 2479 14 4 99.44 99.84 0.72 the regions of ventricular flutter wave in record no. 207 are
223 2604 0 1 100 99.96 0.04 excluded because they are not annotated [22]. The performance
228 2048 11 5 99.47 99.76 0.78 measures, such as p ositive prediction (P+), sensitivity (Se), and
230 2256 0 0 100 100 0
231 1570 0 1 100 99.94 0.06
error rate (ERR) are calculated using the following equations:
232 1778 6 2 99.66 99.89 0.45 P+ = TP/(TP+FP) (8)
233 3073 0 6 100 99.81 0.19
234 2753 0 0 100 100 0 Se = TP/(TP+FN) (9)
Total 109297 111 197 99.9 99.82 0.28
ERR = (FP+FN)/(TP+FP+FN) (10)
whether it is a P wave, T wave, missing R wave or even an
where TP represents true positive detection, FP means false
artifact, is estimated in accordance with its value and location.
positive detection, and FN is false negative detection. The
Since the proposed algorithm contains peak confirmation with
overall measured P+, Se, and ERR values of the proposed beat
insertion and deletion, the FP and false negative (FN) can be
detection algorithm are 99.90%, 99.82%, and 0.28%
further reduced to achieve better results as compared to our
respectively.
previous work [20]. Although the noise interference and
Table VI summarizes the performance measurements of
arrhythmia increase the difficulty in P/T wave detection, some
several different algorithms [20] and [22]-[27]. The proposed
conditions are added in practice to enhance the tolerance level.
algorithm shows a good result. Some algorithms can be
In addition, the above-mentioned features involve some extra
implemented in real-time detection systems and even in chip.
purposes. For example, the historical amplitudes of P/T waves
Although the proposed beat detection algorithm cannot achieve
may provide reference for reducing the influence of noise.
such high performance as the variable frequency complex
Furthermore, several types of arrhythmias can be classified by
demodulation-based ECG detection method [22], it is still an
linking up the configuration of QRS complex with historical
efficient approach that can be employed in real-time detection
RRI. The proposed algorithm is verified by MIT-BIH
systems. This method is currently realized in smartphones and
arrhythmia database and human study.

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Transactions on Biomedical Circuits and Systems

TABLE VII
CHIP PERFORMANCE SUMMARY
General specifications
Technology TSMC 0.18 µm 1P6M CMOS process
Chip Area 2.44×1.99 mm2
Supply voltage 1.2 V / 1.8 V / 3.3V
Analog front-end circuit (a)
Chopper frequency 25.6 kHz
Max input voltage 20 mVpp
CCIA Mid-band gain 16/20/27 dB
Input referred noise 1.84 µVrms
Max input current 40 µA
TIA Mid-band gain 800 Ω
Input referred noise 1.95 nArms
Bandwidth 200 Hz
HPSDM Sampling frequency 51.2 kHz
SFDR >72 dB
Power consumption 0.8 mW (b)
Digital signal processor
Signal bandwidth 200 Hz
Decimation filter
Word length 16 bits S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2
Power consumption 30 µW

has promising potential to be integrated in hardware given that R

peak
R
peak
R
peak
R
peak
R
peak
R
peak
R
peak
the mathematics used are not complex. (c)
B. Measurement Results of the Proposed System Fig. 14. Proposed smart stethoscope system. (a) Appearance of the PCB
board. (b) Measurement scenario. (c) Measured signals from Lead II ECG
The bio-signal acquisition chip is fabricated in the 0.18 µm and pulmonic area PCG.
standard CMOS process. The microphotograph of the chip is
shown in Fig. 13. The performance is also summarized in Table TABLE VIII
VII. The power consumption of the whole chip is COMPARISON WITH RECENT BIO-SIGNAL ACQUISITION SYSTEMS AND
approximately 0.8 mW. The TIA accounts for around 90% of PRODUCTS
the power in this chip. It is necessary to endure the current up [29] [30] [31]
[32] This
to 40 µA, which is as high as the total current of CCIA and [33] work
HPSDM; moreover, the linearity of TIA should be retained CMOS1
Tech CMOS1 COTS2 COTS2 -
COTS
under such severe condition. Even so, the overall chip power is 1.2 V4
still much lower than that of the BLE module. Supply
1.2 V 3.7 V 3 V3 - 1.8 V4
voltage
On the basis of the designed chip, the proposed smart 3.3 V4
stethoscope circuits comprise the required peripherals that are ECG
BioZ
integrated in a printed circuit board (PCB). A photograph of the Measured
GSR ECG PCG
ECG ECG
PCB is shown in Fig. 14(a). The PCB has an area of 2.6×1.85 signal PCG PCG
PPG
cm2 and weight of 1.65 g. Fig. 14(b) shows the practical GPA
measurement scenario. The wet ECG electrodes are attached to Signal
R- R- R-
analysis N/A S1/S2
the front side of the human body around the chest surface. The Peak Peak Peak
stethoscope is placed near the region of the second intercostal Power
26.6 25 87 45.54
space to the left of the sternum. The Lead II channel ECG and consumption
µW5 mW5 mW3,6
-
mW6
pulmonic area PCG from the volunteer subject are measured.
Wireless N/A HBC7 Bluetooth 4.0 BLE BLE
These two signals are displayed on the smartphone. When Battery life N/A N/A N/A 9h >24 h8
measuring the PCG signal, the subject needs to hold the breath Certification N/A N/A N/A FDA TFDA
for seconds to avoid the mixing of breathing sounds. Typically, 1: 0.18 µm 1P6M standard CMOS process
2. COTS: commercially available off-the-shelf
the closure of mitral and tricuspid valves is the cause of S1; 3: Using 3V to estimate the possible power
meanwhile, S2 results from the closure of the aortic and 4: 1.2 V for AFE, 1.8 V for digital core, 3.3 V for BLE module
pulmonic valves. According to the relationship between ECG 5: Average channel power (without wireless transmission power)
6: With wireless transmission power
and PCG stated in [28], the position of S1 is approximately 7: Human body communication
0.04–0.06 s after the start of the QRS complex, and S2 occurs 8: Using a 360 mAh Li-ion battery
near the end of the T wave. The measured signals reveal such a
estimation should be introduced into the proposed system to
cross-reference relation as illustrated in Fig. 14(c). To improve
filter out the unidentifiable regions.
the efficiency of ECG analysis in practical use, the noise level

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TBCAS.2019.2947694, IEEE
Transactions on Biomedical Circuits and Systems
[1]
[2]
[3]
[4]
[5]
[6]
Fig. 15. Ultimate application scenario of the proposed system.
[7]
V. CONCLUSION
This work proposes a PCG and ECG synchronously [8]
monitoring system. The implemented chip comprises CCIA,
TIA, HPSDMs, and DSP blocks. A software application on
smartphone for PCG and ECG signal recording, display, and [9]
detection is developed. A wavelet-based QRS complex
detection algorithm is also proposed. The beat detection
accuracy in terms of sensitivity and positive prediction on the [10]
basis of the MIT-BIH arrhythmia database are 99.82% and
99.90%, respectively. According to recent studies listed in
Table VIII, heart-related signal sensing systems, including the [11]
multi-channel AFE for cardiovascular and respiratory signal
recording [29], acquisition system with level crossing sampling
[30], and PCG sensing system [31], have been developed. Some
works focus on chip implementation only, achieve the [12]
completeness of the system with large power consumption, or
sacrifice the quality of signal to reduce power consumption and [13]
chip area. The products [32][33] similar to the proposed system
has been invented. It is integrated into a stick-type handheld [14]
device to improve the convenience when measuring, but the
signal quality may be affected because of the dry electrodes. [15]
Furthermore, it is hard to keep both PCG and ECG signals
measured at their standard positions and leads simultaneously. [16]
Since the human body is not flat, the curved surface will make [17]
the measurement more difficult especially for females. Fig. 15
illustrates the ultimate application scenario of the proposed
system. The ECG patch with wet electrodes can sense the ECG [18]
signal stably at a specific lead. Meanwhile, the use of traditional [19]
stethoscope head can retain the original habit of auscultation.
Through the operation of stethoscope, four main regions of
cardiac auscultation can all be checked. After detaching the [20]
stethoscope, the ECG patch itself can be applied to the patients
for long-term monitoring. Therefore, our proposed system is [21]
more complete and flexible, and the power consumption is
reasonable and relatively low. The high resolution of the system [22]
is beneficial to further analysis and disease classification. In the
future, doctors can use this system to improve the efficiency of [23]
cardiac auscultation. By establishing a database containing
PCG and ECG signals, the educational environment and
learning efficiency will be improved.
[24]
ACKNOWLEDGMENT [25]
The authors would like to acknowledge the support of
Taiwan Semiconductor Research Institute, Taiwan.
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Shuenn-Yuh Lee (M’98-SM’15) was born in
Taichung, Taiwan, in 1966. He received the B.S.
degree from the National Taiwan Ocean University,
Keelung, Taiwan, in 1988, and the M.S. and Ph.D.
degrees from the National Cheng Kung University,
Tainan, Taiwan, in 1994 and 1999, respectively.
He is currently a Professor at the Department of
Electrical Engineering, National Cheng Kung
University, Tainan, Taiwan. He served as the
Technical Program Chair (TPC) of the 2014/2015
International Symposium on Bioelectronics &
Bioinformatics (ISBB), and the 2015 Taiwan and Japan Conference on Circuits
and Systems (TJCAS). From 2013 to 2016, he serves as the Chairman of IEEE
Solid-State Circuits Society Tainan Chapter. From 2016 to 2017, he serves as
the Vice Chairman of IEEE Tainan Section. From 2016, he serves as the
Associate Editor of IEEE Transaction on Biomedical Circuits and Systems.
His present research activities involve the design of analog and mixed-signal
integrated circuits, biomedical circuits and systems, low-power and low-voltage
analog circuits, and RF front-end integrated circuits for wireless
communications. Dr. Lee now is a member of Circuits and Systems (CAS)
Society, Solid-State Circuits Society, and Medicine and Biology Society of
IEEE. He is also a member of IEICE.
Chieh Tsou (S’18) was born in Kaohsiung, Taiwan,
in 1992. He received the B.S. degree and currently
study for the Ph.D. degree in Electrical Engineering
from National Cheng Kung University, Tainan,
Taiwan, in 2014.
His research interests include the design of
baseband modulation ASIC, MCU with peripheral
interface, memory verification, decimation filter,
bio-signal detection algorithm with hardware design,
SOC integration, software design, firmware design,
biomedical system platform setup and PCB design,
and animal testing.
Mr. Tsou awards and accepted papers include excellent work in 2014 cell-based
digital circuit design hold by CIC, Taiwan, excellent work in 2015 Silicon
Awards held by Macronix, Taiwan, attend 2015 ISBB, 2019 ISSCC, and 2019
AICAS.
Yu-Yi Liao was born in Changhua, Taiwan, in 1993.
He received the B.S. degree from National Cheng
Kung University, Taiwan, in 2016. He is currently
pursuing the M.S. degree from the Institute of
Electrical Engineering, National Cheng Kung
University, Tainan, Taiwan.
His research interests include the design of digital
integrated circuits, software development, and
machine learning.
Ju-Yi Chen was born in Tainan, Taiwan, in 1974.
He received the M.S. degree from the Chang Gung
University, Taoyuan City, Taiwan, in 1999, and the
Ph.D. degrees from the National Cheng Kung
University, Tainan, Taiwan, in 2013.
He is currently an Associate Professor from 2013, at
the Department of Internal Medicine, National
Cheng Kung University, Tainan, Taiwan.
His present research activities involve the
cardiovascular diseases, including arrhythmias,
hypertension, arterial stiffness, and cardiac
implantable electric devices.

Peng-Wei Huang (S’19) was born in Tainan,

Taiwan, R.O.C., in 1990. He received the B.S.
degree from National Cheng Kung University,
Taiwan, in 2013. He is currently pursuing the Ph.D.
degree from the Institute of Electrical Engineering,
National Cheng Kung University, Tainan, Taiwan.
His research interests include the design of digital
integrated circuits, software development, and
biomedical circuits and systems.
His awards and accepted papers include excellent
work in 2014 cell-based digital circuit design hold
by CIC, Taiwan, excellent work in 2015 Silicon Awards held by Macronix,
Taiwan, and attended 2015 ISBB.

Jia-Ren Chiou was born in Kaohsiung, Taiwan,

R.O.C., in 1991. He received the B.S. degree from
National Cheng Kung University, Taiwan, in 2014.
He is currently pursuing the M.S. degree from the
Institute of Electrical Engineering, National Cheng
Kung University, Tainan, Taiwan.
His research interests include the design of
baseband analog front end and sigma-delta
modulator.

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