Digital Payload Modeling for

Space Applications

Bradford S. Watson
Staff Engineer
Advanced Algorithm Development Group

Copyright 2008. Lockheed Martin Corporation. All rights reserved. 0000.PPT 5/9/2008 1
Overview
• In recent years in the commercial or government space businesses,
there has been a movement away from RF analog payloads for pure
“bent-pipe,” or “transponder” applications.
• Up until even the recent past, these payloads have been fixed
band plan, implemented with all analog electronics.
• Today’s customers are looking towards all digital payloads that utilize
digital signal processing (DSP) to accomplish the same goals while
providing enhanced mission capability and flexibility.

“Bent Pipe” transponder satellite at

Geostationary Orbit (35,786 km)

Location A Location B

2
The Challenge
• Design a Modular Agile digital Payload (MAP) to take the place of
the traditional analog communications satellite payload.
• The payload must have the following characteristics:
• Be spaceworthy; i.e., highly reliable, and highly tolerant of
radiation effects.
• Be reconfigurable; that is, able to be altered on-orbit for different
functions as business conditions change.
• Be highly flexible and agile with respect to bandplan and
channelization, so that bandwidth for users can be assigned “on-
demand,” and spectrum can be arbitrarily allocated anywhere
within the full bandwidth of a beam.
• Be modular, and re-useable for many different programs, all with
different requirements.

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The Early Days
• Early on in the program, it was a complete unknown what this system
would look like.
• Requirements from numerous programs were flying around, and they
were often incompatible with each other, particular their bandplans:
• AMC: 4, 8, 36, and 72 MHz wide channels.
• MMSI: 24 and 32 MHz wide channels.
• JSAT: 27 MHz wide channels.
• AsiaSAT: 8 and 36 MHZ wide channels.
• and many others…
• These unknown requirements not only made it very difficult to design
the hardware, but put a tremendous amount of work on the DSP
engineer designing algorithms.
• As the lead DSP engineer, I found myself re-writing the algorithms
almost daily, in order to demonstrate the various bandplans.
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The Hardware Solution

Digital Channelizer Unit (DCU):

• A modular, space-worthy payload composed of the following
building blocks:
• CIO – Channelizer I/O Module
• Composed of 5 Field Programmable Gate Arrays (FPGAs),
three of which are voted for extremely high reliability.
• Handles all of the signal processing, real-time.
• DRM – Data Routing Module
• Multi-gigabit, non-blocking data routing in rad tolerant FPGAs.
• RIO – RF Input/Output Modules
• Power Converters

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 System Level DCU Architecture
Each input port (RIO): CIO modules: DRM module: CIO modules: RIO modules:
125 MHz anti alias filter Digitize Spectrum Multi-Gigabit Reconstruct Spectrum Reconstruction
RF power optimized for ADC Divide Channels Routing Dig. to RF conversion Filtering
SPARE SPARE SPARE SPARE SPARE
Beam 4 SPARE Beam 4
Beam 3 Beam 3
Beam 2
Beam 1 Beam 2
Beam 1
RF RF RF ADC Dig Dig Dig Dig DAC RF RF

BCA Control

SCB Controller Serial Command Bus

EPC & Intermediate Power

MIL-STD 1553 B

Frequency Generation RIO – RF Input/Output Module

Spacecraft TT&C Bus
CIO – Channelizer Input/Output Module
5 for 4 Processing Modules Spacecraft RIU

2 For 1 Router/Controllers DRM – Data Routing Module

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DCU on MAP Spacecraft
MAP – type
Spacecraft

Active Arrays

Channelization in CIO
Digital Channelizer Unit
(DCU) CIO DRM
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DCU Algorithm
Algorithm Overview
• The DCU algorithm is defined as the mathematical manipulation (via fixed point
arithmetic implemented in the DCU FPGAs) of data samples to perform the following
tasks:
– Process a total digitized analog frequency bandwidth of 500 MHz (which may or
may not be contiguous).
– Break up this bandwidth into narrowband “subchannels” (i.e., “channelize”)
– Have the ability to re-arrange the subchannels in any arbitrary order.
– Have the ability to alter the subchannel gains arbitrarily, in multiple modes.
– Have the ability to measure and report the average and peak signal power level at
the input and output of the DCU, as well as at the subchannel level.
– Recombine the subchannels (i.e., "reconstruct" them) into a composite bandwidth of
the same size as the input.
– Transform the recombined spectrum so that it can be converted back into the
analog domain for further processing.
– Be arbitrarily reconfigurable in signal processing function.
• The functional data flow for a 4 port DCU is depicted here:

Port 0 Port 0
Port 1
ADC Channelize Reconstuct DAC Port 1
Port 2
ADC Channelize Reconstuct DAC Port 2
ADC Channelize Reconstuct DAC
Port 3
ADC Channelize Route Reconstuct DAC Port 3

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 DCU Algorithm
Matlab Algorithmic Model
Input IF Preprocess
• A floating point model of the DCU Two - Sided Input Signal Spectrum After Sampling (Possibly Aliased Spectrum)

-10
0

-10
Input Signal Spectrum After Quarter Band Filtering

algorithm has been developed in the -20

-30
-20

Amplitude (dB)
-30

Amplitude (dB)
-40 -40

-50

Matlab environment.
-50

-60 -60

-70 -70

-80 -80
-250 -200 -150 -100 -50 0 50 100 150 200 250 -60 -40 -20 0 20 40 60
Frequency (MHz) Frequency (MHz)

• This model is designed to be very

routing_table,
flexible, allowing the user to specify a Channelize
gain_table

wide range of arguments. 0

subch 0, port 0
0
subch 1, port 0
0
subch 2, port 0
0
subch 3, port 0
0
subch 4, port 0
0
subch 5, port 0

dB

dB

dB

dB

dB

dB
-50 -50 -50 -50 -50 -50

-100 -100 -100 -100 -100 -100

-2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2

0
MHz
subch 6, port 0
0
MHz
subch 7, port 0
0
MHz
subch 8, port 0
0
MHz
subch 9, port 0
0
MHz
subch 10, port 0
0
MHz
subch 11, port 0

Route,
Route,

dB

dB

dB

dB

dB

dB
-50 -50 -50 -50 -50 -50

-100 -100 -100 -100 -100 -100

• This makes the Matlab model useful for functionally

-2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2

Gain
MHz MHz MHz MHz MHz MHz
subch 12, port 0 subch 13, port 0 subch 14, port 0 subch 15, port 0 subch 16, port 0 subch 17, port 0
0 0 0 0 0 0

Gain

dB

dB

dB

dB

dB

dB
-50 -50 -50 -50 -50 -50

-100 -100 -100 -100 -100 -100

verifying various channelization schemes quickly and

-2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2
MHz MHz MHz MHz MHz MHz
subch 18, port 0 subch 19, port 0 subch 20, port 0 subch 21, port 0 subch 22, port 0 subch 23, port 0
0 0 0 0 0 0

dB

dB

dB

dB

dB

dB
-50 -50 -50 -50 -50 -50

-100 -100 -100 -100 -100 -100

efficiently. The user simply needs to pick the right

-2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2 -2 0 2
MHz MHz MHz MHz MHz MHz
subch 24, port 0 subch 25, port 0 subch 26, port 0
0 0 0

dB

dB

dB
-50 -50 -50

-100 -100 -100

parameters (filter coefficients, FFT length,

-2 0 2 -2 0 2 -2 0 2
MHz MHz MHz

decimation/interpolation factors), etc.

• The DCU algorithm function can be Reconstruct

Reconstructed Function Output
Output IF
Passband Output Spectrum

0 0

called from the Matlab command line, or -10

-20

-30
-10

-20

Amplitude (dB)
-30

Amplitude (dB)
as part of a script file.
-40 -40

-50
-50

-60
-60

-70
-70
-80
-80
-60 -40 -20 0 20 40 60
Frequency (MHz) -400 -300 -200 -100 0 100 200 300 400
Frequency (MHz)

• This function is composed of lower level

functions that do arbitrary channelization
and reconstruction.

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 DCU Algorithm
Simulink Structural Model

The next step in the development was

to build a structural model of the DCU Simulink Block Diagram
algorithm in the Simulink environment.
• This model is designed to test implementation
assumptions about the DCU Algorithm and
provide a model that is very similar to what the
real gateware will look like.

Once the Simulink model works

properly, another Simulink model is
developed by replacing the blocks with
components from another vendor’s
blockset in order to generate VHDL.

Simulink to Hardware Development

FPGA SynDSP Blockset Model HDL Synthesis
Simulink Model

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DCU Algorithm
Model Verification
Once VHDL for the various pieces of the DCU algorithm have been developed, tested in
the Simulink environment, and stitched together in the Mentor HDL environment, the
next step is functional simulation and verification.
For this task, we choose the EDA Simulator Link MQ tool (formerly known as “Link for
Modelsim”).
• This tool allows us to make use of all of the signal generation and visualization tools available to us in the
Simulink environment, while still simulating the VHDL at the bit level.
• In fact, we can use the exact same test-benches for VHDL test and verification that we used during the
development phase.
• This tool was immensely helpful in finding bugs in the code that were not apparent in the Simulink
environment alone.

Pull the generated code Bring into Simulink

together with HDL Designer Environment Simulate with ModelSim

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Conclusion
• Using advanced tools and methods, we took a program from concept
through functional, space-worthy hardware in about 1½ years.
• Estimated reduction in development time 8 months over
traditional (hand coding) methods.
• Process flow and tools:
• Concept – Matlab (Signal Processing Toolbox)
• Structural Model – Simulink (Signal Processing and
Communications Blockset)
• VHDL Model – SynDSP Blockset in Simulink Environment
• VHDL Code Integration – HDL Designer
• Functional Verification and Degugging - EDA Simulator Link
MQ tool in Simulink Environment

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