Lesson 6

⚫ Discrete poles, overshoot & settling time

⚫ Discrete root locus

⚫ Lead compensation

⚫ Lag compensation

1
Introduction
One way to design a discrete controller for a continuous plant is to
design the controller in the s-domain and then convert the transfer
function of the controller (Hc(s)) to a discrete one using Euler, Tustin or
the impulse invariance method.
If you follow this strategy, you should include the transfer function of
the sample & hold circuit. For instance, the total overall system equals:

𝑯𝒄 𝒔 ∙ 𝑯𝒑 𝒔 ∙ 𝑯𝑺&𝑯 (𝒔) 𝑻
−𝒔∙ 𝟐𝒔 𝟏
𝑯 𝒔 = 𝒘𝒉𝒆𝒓𝒆: 𝑯𝑺&𝑯 𝒔 ≈ 𝒆 ≈
𝟏 + 𝑯𝒄 𝒔 ∙ 𝑯𝒑 𝒔 ∙ 𝑯𝑺&𝑯 (𝒔) 𝑻
𝟏 + 𝒔 ∙ 𝟐𝒔

The transfer function of the sample & hold circuit is determined

by the assumption that a sample & hold circuit causes an
average delay of Ts/2 (the delay by the sampling time is
neglected).

2
Introduction
It is also possible to convert the transfer function of the plant to a
discrete function and then use discrete controller design methods.
In this lesson we explain how this works.
We first relate the discrete pole location to the overshoot and settling
time of a system.
Then we show how to use the discrete root locus as a tool to find a
suited gain of the feedback loop.
And finally, we show how a discrete lead and lag compensation can be
applied to help meeting the requirements related to overshoot and
settling time.

3
 Poles, overshoot and settling time
Given a system with damping x and natural resonance frequency wn.
In the s-domain, the complex poles s1,2, overshoot (os) and settling time at
a tolerance fraction e relate to each other as:

𝒔𝟏,𝟐 = 𝝈 ± 𝒋 ∙ 𝝎𝒅 𝒘𝒉𝒆𝒓𝒆: 𝝈 = −𝝃 ∙ 𝝎𝒏 𝒂𝒏𝒅 𝝎𝒅 = 𝝎𝒏 ∙ 𝟏 − 𝝃𝟐

−𝝅∙𝝃
𝒍𝒏 𝜺 ∙ 𝟏 − 𝝃𝟐
𝒐𝒔 = 𝐞 𝟏−𝝃𝟐 𝒂𝒏𝒅 𝒕𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈 =
𝝈
In the z-domain, the following relations apply at a sample time of Ts:

𝒑𝒐𝒍𝒆𝒔: 𝒑𝟏,𝟐 = 𝒆𝒔𝟏,𝟐 ∙𝑻𝒔 = 𝒆 𝝈±𝒋∙𝝎𝒅 ∙𝑻𝒔

= 𝒓 ∙ 𝒆±𝒋∙𝛀𝟎 𝒘𝒉𝒆𝒓𝒆: 𝒓 = 𝒆𝝈∙𝑻𝒔 𝒂𝒏𝒅 𝛀𝟎 = 𝝎𝒅 ∙ 𝑻𝒔

We can use these equations to find the relationship between overshoot and
settling time with the discrete poles of a system.

4
Discrete poles, overshoot and settling time

The radius of a discrete pole can be found as follows:

−𝝅∙𝝃
𝟏−𝝃𝟐
−𝝅 ∙ 𝝃 −𝒍𝒏(𝒐𝒔)
𝒐𝒔 = 𝐞 → = 𝒍𝒏 𝒐𝒔 → 𝝃=
𝟏 − 𝝃𝟐 𝝅𝟐 + 𝒍𝒏𝟐 (𝒐𝒔)
𝜺∙𝝅
𝒍𝒏
𝒍𝒏 𝜺 ∙ 𝟏 − 𝝃𝟐 𝝅𝟐 + 𝒍𝒏𝟐 (𝒐𝒔)
𝝈= = . 𝐈𝐭 𝒂𝒑𝒑𝒍𝒊𝒆𝒔: 𝒓 = 𝒆𝝈∙𝑻𝒔 →
𝒕𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈 𝒕𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈

𝟏
𝜺∙𝝅 𝒏𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈 𝒕𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈
𝒓= 𝒘𝒉𝒆𝒓𝒆: 𝒏𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈 =
𝝅𝟐 + 𝒍𝒏𝟐 𝒐𝒔 𝑻𝒔

Once the radius is known, the angle of a discrete pole can be calculated as
follows:

𝝅 𝝅 𝝅
𝝈∙𝝎 𝝈∙𝑻𝒔 ∙𝝎
𝛀
𝒍𝒏(𝒓)
𝒐𝒔 = 𝐞 𝒅 =𝐞 𝒅∙𝑻𝒔 = 𝒓 𝟎 → 𝛀𝟎 = 𝝅 ∙
𝒍𝒏(𝒐𝒔)

5
 Example

Question: Calculate the dominant poles of a system that has 15%

overshoot and after 40 samples, the step-response remains within 5%
bandwidth of its steady-state value (so, 𝜺 = 𝟎. 𝟎𝟓 and nsettling = 40).

Answer:

𝟏
𝝅∙𝜺 𝒏𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈 ln 𝒓
𝒓= = 𝟎. 𝟗𝟐𝟒𝟐 𝒂𝒏𝒅 𝛀𝟎 = 𝝅 ∙ = 𝟎. 𝟏𝟑𝟎𝟓 →
𝝅𝟐 + 𝒍𝒏𝟐 (𝒐𝒔) ln 𝒐𝒔

𝒑𝟏,𝟐 = 𝒓±𝒋∙𝟎.𝟏𝟑𝟎𝟓 = 𝟎. 𝟗𝟏𝟔𝟒 ± 𝒋 ∙ 𝟎. 𝟏𝟐𝟎𝟐

6
Pole plots at constant settling time
The figure below show graphs of the pole locations when the overshoot varies
from almost 0% to a maximum value where W0 = p at a constant nsettling and
tolerance fraction 𝜺. The pole locations follow a circle-like figure with a radius of
𝒓 ≈ 𝜺 𝟏/𝒏𝒔𝒆𝒕𝒕𝒍𝒊𝒏𝒈 . Note the ‘notch’ in the circle at low overshoot values.
Also, note that smaller values of nsettling and 𝜺 result in smaller values of the pole
radius.

7
Pole plots at constant overshoot

The figure below show graphs of the pole locations when nsettling varies from
1000 down to a value where W0 = p at a constant overshoot and tolerance
fraction 𝜺. The pole locations all start at z=1 when nsettling→∞ .
Note that smaller overshoot values result in smaller values of the pole radius.

8
 Complex pole region plots
The maximum overshoot and minimum settling time of a system define the region
where the dominant poles of the system must lie. The grayed area in the figure
below shows 2 examples of such a poles regions. The requirements of the figure
on the left are: overshoot <25% and the nsettling<60 at 𝜺 = 𝟓%. The requirements on
the figure on the right are: overshoot <5% and nsettling<10 at 𝜺 = 𝟓%.

9
 Discrete root locus
The discrete root locus is a plot that shows the location of discrete poles of
a feedback system if one controller parameter varies. The figure below
shows 2 examples of the discrete root locus of a second order system that

is controlled by a simple proportional

controller with variable gain K.

10
 Discrete controller design
A discrete root locus plot can be combined with a complex pole region plot in
order to design a controller that meets given specifications. The figures below
show the complex pole region plot for a system having a maximum overshoot
of 10% and nsettling<15 at 𝜺 = 𝟓%. The root locus belong to 2 different 2nd order
system that are controlled by a proportional controller with variable gain K (see
plots on previous sheet).

11
 Discrete controller design
If we evaluate the root locus / complex pole region plot of the previous
sheet, we may conclude the following:

- Left plot: the root locus lies completely outside the complex pole
region. That means that a simple proportional controller cannot meet the
requirements for this system. To solve this, lead compensation can be
applied.

- Right plot: If K<0.2, the root locus lies within the complex pole region.
So, it is possible to meet the specifications. However, the gain of the
proportional controller is relatively low. This will lead to a relatively big
steady state error. To solve this, lag compensation can be applied.

12
 First order lead compensation
The goal of lead compensation is to move the poles of a system to the left in
the complex plane. This may help meeting the requirements if the root locus
lies too far to the right with respect to the complex pole region plot.
A 1st order discrete lead compensator is a controller that has one real pole
and one real zero. The pole is located to the left of the zero, so:
𝒛 − 𝒛𝒄
𝑯𝒄 𝒛 = 𝑲 ∙ 𝒘𝒉𝒆𝒓𝒆 𝒑𝒄 < 𝒛𝒄
𝒛 − 𝒑𝒄
If zc equals one of the plant poles, then this pole will be canceled by zc while a
new pole pc is introduced in the transfer function. For a 2nd order system with
poles p1 and p2 holds:
𝒛 − 𝒛𝒄 𝟏 𝑲
𝑯 𝒄 𝒛 ∙ 𝑯𝒑 𝒛 = 𝑲 ∙ ∙ = 𝒘𝒉𝒆𝒓𝒆 𝒛𝒄 = 𝒑𝟏
𝒛 − 𝒑𝒄 𝒛 − 𝒑𝟏 ∙ 𝒛 − 𝒑𝟐 𝒛 − 𝒑𝒄 ∙ 𝒛 − 𝒑𝟐

The net result is that the original pole p1 is moved to pc. Since pc < p1 ,
the root locus will shift to the left (see plots on next sheet).

13
 Example lead compensation
Design a lead compensator for the plant given in the left figure of sheet 10.

Answer: We make the zero of the lead compensator equal to zc=0.6 to cancel out the
plant pole at 0.6. For pc we take pc=0.1. The figure below shows the result. The vertical
section of the root locus now partially lies within the grayed area that corresponds to
the system requirements of maximum overshoot =10% and nsettling<15 at 𝜺 = 𝟓% .

14
 Lag compensation
The goal of lag compensation is to decrease the steady state error. A 1st order
discrete lag compensator is a controller that has one real pole and one real
zero both located close together a little left of z=1. The transfer function of a
1st order lag compensator is given by:

𝒛 − 𝟏 − 𝜶𝒛
𝑯𝒄 𝒛 = 𝑲 ∙ 𝒘𝒉𝒆𝒓𝒆: 𝟎 < 𝜶𝒑 < 𝜶𝒛 << 𝟏
𝒛 − 𝟏 − 𝜶𝒑
Because the zero and pole lie close to each other, the lag compensator
doesn’t have a big influence on the root locus of the dominant poles.
However, they have a big influence on the steady state error (𝜺𝒔𝒔 ).

𝑯𝒄 𝟏 ∙ 𝑯𝒑 𝟏 𝟏 𝜶𝒛
𝜺𝒔𝒔 =𝟏− = 𝒘𝒉𝒆𝒓𝒆: 𝜸 = 𝑯𝒄 𝟏 =
𝟏 + 𝑯𝒄 𝟏 ∙ 𝑯𝒑 𝟏 𝟏 + 𝑲 ∙ 𝜸 ∙ 𝑯𝒑 𝟏 𝜶𝒑

The lag compensator adds an extra factor g = az/ap in the right term
of the denominator that decreases the steady state error.

15
 Example lag compensator (1)
Design a 1st order lag compensator for the plant given in the right figure of sheet
𝒛+𝟎.𝟔
10 ( 𝑯𝒑 𝒛 = 𝒛−𝟎.𝟓 ∙ 𝒛−𝟎.𝟐
). The primary requirement is to get the steady state error
on a step response to be less than 2%. Evaluate if the system meets the original
requirements related to overshoot (<15%) and settling time (nset<5 at 𝜺=5%).

Answer: A gain of K=0.2 meets the requirements with respect to overshoot and
nset (see sheet 10). The following holds at a steady state error to be 2%.

𝟏 𝟒𝟗
= 𝟎. 𝟎𝟐 → 𝟎. 𝟐 ∙ 𝜸 ∙ 𝑯𝒑 𝟏 = 𝟒𝟗 → 𝜸= = 𝟔𝟏. 𝟐𝟓
𝟏 + 𝑲 ∙ 𝜸 ∙ 𝑯𝒑 𝟏 𝟎. 𝟐 ∙ 𝟒

We choose to be az = 0.1. Then, this zero is still relatively far from the poles of
the plant, so the influence on the root locus of the dominant plant poles is
relatively small. For ap we then find: ap = 0.1 / 61.25 = 0.0016 →

𝑲 ∙ (𝒛 − 𝟎. 𝟗)
𝑯𝒄 𝒛 =
𝒛 − 𝟎. 𝟗𝟗𝟖𝟒
16
 Example lag compensator (2)
The figure below shows the root locus and step response of the system with a
proportional controller and that of the lag compensator. The root locus of the lag
compensator and proportional controller are almost the same, only the lag
compensator has an extra root locus from z=0.9984 to z=0.9.
At start (the first 3 samples), the step response of both systems are almost the same,
then the step response of the lag compensator goes to a steady state value of 0.98
whereas the steady state value of the step response of the proportional is only 0.44.
The overshoot of the lag compensator is 0 and nsettling = 50. So, the original settling
requirement of nsettling < 15 is not met anymore.

17
Questions / Exercises

Question 1: Calculate the dominant poles of a discrete system that has

an overshoot of 25% and after 18 samples, the step-response remains
within 5% bandwidth of its steady-state value (𝜺 = 𝟎. 𝟎𝟓 and nsettling =18).

Question 2: Calculate the resonance frequency wd, overshoot and the 5%

settling time of a discrete system with dominant poles at 𝒑𝟏,𝟐 = 𝟎. 𝟑𝟕𝟑 ± 𝒋 ∙
𝟎. 𝟔𝟑𝟕. The sample time is 10 [ms].

18
 Questions / Exercises
Question 3: Given the following transfer function of a continuous system (plant):
𝟓
𝑯𝑷 𝒔 =
𝒔𝟐 ∙ 𝟎. 𝟑 + 𝟎. 𝟒 ∙ 𝒔 + 𝟏

a. Give the discrete transfer function of the plant at fsample = 10Hz. Use Tustin.
b. Assume that a proportional controller is used to control this plant. Show in a
plot the root loci and the unit circle. Write a matlab script to do this.
c. Is there a gain factor K of the proportional controller that gives an overshoot
less then 20% and a 5% settling time less than 2s?
d. Determine a suited gain, pole(s) and zero(s) of a lead compensator that gives
an overshoot less then 20% and a 5% settling time less than 2s.
e. Add a 1st order lag compensator to the controller of question 3d. Determine
the pole and zero of the lag compensator so that the steady state error is 1%.
Show the step response of the system.
f. What can you do, if you have a lag compensator, to get a 0 steady
state error? Show the step response in that case.
19