Scribd Logo
Upload

Welcome to Scribd!

  • Crash Dump

    Uploaded by

    Andriyanto Saribulan
    9 views2 pages
    An unhandled SIG_SEGV error occurred due to an invalid memory access instruction. The error was caused by a stmnvia instruction accessing addresses 91. Register information and emulated ARM processor states are provided with no abnormal values noted. Translation cache details are given with normal allocated ranges.

    Original Description:

    Qww

    Original Title

    crash_dump

    Copyright

    © © All Rights Reserved

    Available Formats

    TXT, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    An unhandled SIG_SEGV error occurred due to an invalid memory access instruction. The error was caused by a stmnvia instruction accessing addresses 91. Register information and emulated ARM processor states are provided with no abnormal values noted. Translation cache details are given with normal allocated ranges.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    9 views2 pages

    Crash Dump

    Uploaded by

    Andriyanto Saribulan
    An unhandled SIG_SEGV error occurred due to an invalid memory access instruction. The error was caused by a stmnvia instruction accessing addresses 91. Register information and emulated ARM processor states are provided with no abnormal values noted. Translation cache details are given with normal allocated ranges.

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    of 2

    Unhandled SIG_SEGV in ''

    caused by instruction stmnvia sp, {r1 - r2, r6 - r8, r10 - r11, sp - lr}^ (at
    d60bd9e4), address 91
    Version: r2.5.2.2a build 104
    Reference: C54A45E4
    Registers:
    r00: 00000035
    r01: EAF7D390
    r02: C2EE1500
    r03: C8D27C28
    r04: 00000000
    r05: C8D27C28
    r06: D7596400
    r07: C8D27CA8
    r08: C8D27C70
    r09: EAF7D390
    r10: C2EE1500
    r11: C8D27C40
    r12: 00000065
    r13: C8D27C10
    r14: D76F5F33

    Emulated ARM9:
    Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
    r0: 00000000
    r1: 00000000
    r2: 00000000
    r3: 00000000
    r4: 00000000
    r5: 00000000
    r6: 00000000
    r7: 00000000
    r8: 00000000
    r9: 00000000
    r10: 00000000
    r11: 00000000
    r12: 00000000
    r13: 00000000
    r14: 00000000
    r15: 00000000
    Debug instruction count: 0

    Emulated ARM7:
    Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
    r0: 00000000
    r1: 00000000
    r2: 00000000
    r3: 00000000
    r4: 00000000
    r5: 00000000
    r6: 00000000
    r7: 00000000
    r8: 00000000
    r9: 00000000
    r10: 00000000
    r11: 00000000
    r12: 00000000
    r13: 00000000
    r14: 00000000
    r15: 00000000
    Debug instruction count: 0

    Translation cache details:


    main: 0xc567e000 - 0xc667e000
    main: 983048192 + -966270976 bytes
    itcm: 0xc667e000 - 0xc677e000
    itcm: 966270976 + -965222400 bytes
    alternate: 0xc677e000 - 0xc697e000
    alternate: 965222400 + -963125248 bytes

    0 texture cache bytes allocated, 0 texture cache elements.

    You might also like