Dashboard Courses Soen Digital Logic II (Beirut - Section B - 193068) Fall 2021 - 2022 General CENG335-Final-Exam-Fall-2021-2022

1/19/22, 3:29 PM CENG335-Final-Exam-Fall-2021-2022
Dashboard / Courses / SoEN / Digital Logic II( Beirut - Section B - 193068) Fall 2021 - 2022 / General / CENG335-Final-Exam-Fall-2021-2022
Question 1
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Complete the behavioral VHDL code of a generic tristate buffer with a default size equals to 16.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY trin IS
GENERIC ( N : INTEGER := 16 ) ;
PORT ( X : IN STD_LOGIC_VECTOR(N−1 DOWNTO 0) ;

E : IN STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(N−1 DOWNTO 0) ) ;
END trin ;
ARCHITECTURE Behavior OF trin IS

BEGIN
PROCESS (E)
BEGIN
if E ='0' THEN
F <= E;
ELSE
F <= X;
END IF;
END PROCESS;
END Behavior ;
GENERIC ( N : INTEGER := 16 ) ; GENERIC ( N : INTEGER := 8 ) ; GENERIC ( N : INTEGER := 32 ) ;
GENERIC ( N : INTEGER := 2 x 8 ) ; STD_LOGIC_VECTOR(N−1 DOWNTO 0) STD_LOGIC_VECTOR(15 DOWNTO 0)
STD_LOGIC_VECTOR(16 DOWNTO 0) PROCESS (X,E) PROCESS (X)
PROCESS (E) E ='1' E ='0'
E ='Z' F <= X; F <= E;
F<= (OTHERS=>'Z'); END IF; END PROCESS;
https://ems.liu.edu.lb/mod/quiz/attempt.php 1/22
Question 2
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Determine the storage element corresponding to each of the following diagrams. D and Q denote the input and the output of the storage element respectively.
Note that no answer should be repeated more than once. Note that the storage element (Gated Latch or Flip Flop) may have an asynchronous clear.
Positive-edge-triggered flip flop
Positive-edge-triggered flip flop with asynchronous clear
Negative-edge-triggered flip flop
Gated D latch
Question 3
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Consider the universal shift register with an Asynchronous parallel load shown in the following figure:
The register has 8-bit parallel inputs R0 to R7 and a serial input bit SI and 8-bit outputs Q0 to Q7.
When the Asychonous control signal L is 1 the register will load instantaneously the parallel inputs R0 to R7 into the register.
When L is 0 the register act as a synchronous shift register and it will load the serial input SI. The shift direction is controlled by the signal Left_right, where
it will shift to the left if Left_right is 1 and to the right otherwise.
The register has a Synchronous Reset signal that will clear the register at the rising edge of the next clock cycle when Reset is 0.
Complete the following VHDL code that provides the design of this register.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shift IS
GENERIC (N: INTEGER :=8);
PORT(Clock, SI, LEFT_RIGHT, Reset,L : IN STD_LOGIC;
R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0));
END shift;
ARCHITECTURE Behavior OF shift IS
BEGIN
PROCESS(Clock, L)
BEGIN
IF L='1' THEN Q => R;
ELSIF ( Clock'EVENT AND Clock='1' ) THEN
ELSIF ( ) THEN
Q <= Q(N-2 DOWNTO 0) & SI;
ELSE
Q <= ;
END IF;
END IF;
END PROCESS;
END Behavior;
IF L='1' THEN Q <= R; IF Reset = '0' THEN Q <= (OTHERS => '0')
LEFT_RIGHT='1' SI & Q(N‑1 DOWNTO 1)
SI & Q(N‑2 DOWNTO 0) IF Reset = '0' THEN Q <= 0 LEFT_RIGHT='0'
Clock'EVENT AND Clock='0'
Question 4
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We consider the comparison of the two unsigned numbers A and B each on 4 bits: A=(a3 a2 a1 a0) and B=(b3 b2 b1 b0).
Drag the equations from the list below into the correct spaces in order to complete the following algorithm that describes the execution of the 4-bit
comparison operation.
A > B IF:
a3 > b3 ,
Or
a3 = b3 and a2 > b2
, Or
a3 = b3 and a2 = b2 and a1 > b1 , ,
Or
a3 = b3 and a2 = b2 and a1 = b1 and a0 > b0
Question 5
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Given below the table that shows the control signals asserted in each operation/time step.
Determine the expression of the signal "R3out" in terms of X, Y, I0, I1, I2, I3, T0, T1, T2 and T3.
Select one:
a. R3out = [(I1T1 + I2T2 + I3T2 ]Y3 + (I2+ I3)T1X3
b. R3out = [(I1T1 + I2T2 + I3T2 ]Y0 + (I2+ I3)T1X0
c. R3out = [(I1T1 + I2T2 + I3T2 ]X3 + (I2+ I3)T1Y3
d. R3out = [(I1T1 + I2T2 + I3T3 ]Y3 + (I2+ I3)T3X3
Clear my choice
Time left 0:01:52
Question 6
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A 4-bit ALU has the following ports:
Port Name Mode Size Data Type
inp_a input 4 bits SIGNED
inp_b input 4 bits SIGNED
sel input 3 bits STD_LOGIC_VECTOR
out_alu output 4 bits SIGNED
This ALU can perform different operations based on the value of sel vector, as shown below:
sel out_alu
000 inp_a + inp_b
001 inp_a - inp_b
010 inp_a - 1
011 inp_a + 1
100 inp_a AND inp_b
101 inp_a OR inp_b
110 NOT inp_a
111 inp_a XOR inp_b;
Others NULL
To complete the following VHDL of this ALU, match the numbers between brackets with the correct keywords selected from the list below:
library ____[1]_____;
use ___[2]___;
use IEEE.NUMERIC_STD.ALL;
entity ____[3]____ is
Port ( inp_a : in signed ____[4]___;
inp_b : in signed(3 downto 0);

sel : in ____[5]____ (2 downto 0);
___ [6]___ : out signed(3 downto 0));

end alu;
architecture Behavioral of alu is
begin
process (inp_a, inp_b, ___[7]____)
begin
____[8]___ sel is
when "000" =>
out_alu<= inp_a + inp_b;

when ___[9]____ =>
out_alu<= inp_a - inp_b;

when "010" =>

out_alu<= inp_a - 1; --sub 1
when "011" =>

out_alu<= inp_a + 1; --add 1
when "100" =>

out_alu<= __[10]___;
when "101" =>

out_alu<= inp_a or inp_b;
when "110" =>
out_alu<= ___[11]___ ;
when "111" =>
out_alu<= inp_a xor inp_b; when ___[12]___ =>

___[13]___;
end case;
end ___[14]___;
end ___[15]___;
[1] IEEE
[2] IEEE.STD_LOGIC_1164.ALL
[3] alu
[4] (3 downto 0)
[5] sel
[6] out_alu
[7] sel
[8] Choose...
[9] Choose...
[10] Choose...
[11] Choose...
[12] Choose...
[13] Choose...
[14] Process
[15] Behavioral
Question 7
Incomplete answer
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Given below the implementation of 3-input function f using two two-input LUTs. By dragging and dropping the items below, show the truth table implemented
inside each LUT and indicate the input of each LUT.
Hint: Remember that the inputs of a LUT should respect their positions in the Truth Table as shown below:
f = w2' [w1' + w3] + w2 [w1w3'] (result of Shannon expansion with respect to w2)
w1w3'
w2
w2 w3 w1w3' w1
Your answer is not complete; please drag an item to each drop region.
Question 8
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Consider the following circuit in which we would like to perform the below operations in sequence. Note that each operation in the following sequence takes
only one clock cycle.
1. R1 receives data from Data1
2. R0 receives data from Data2

3. Copy R1 to R2
4. Copy R0 to R1
5. Copy R2 to R0
6. Copy R1 to R2
7. Copy R0 to R3
Fill the below truth table with the corresponding signals values (do not leave cells empty)
Clock Cycle 1 2 3 4 5 6 7 8
R0in 0 1 0 0 1 0 0 0
R1in 1 0 0 1 0 0 0 0
R2in 0 0 1 0 0 1 0 0
R3in 0 0 0 0 0 0 1 0
R0out 0 0 0 1 0 0 1 0
R1out 0 0 1 0 0 1 0 0
R2out 0 0 0 0 1 0 0 0

Clock Cycle 1 2 3 4 5 6 7 8
R3out 0 0 0 0 0 0 0 0
Extern1 1 0 0 0 0 0 0 0
Extern2 0 1 0 0 0 0 0 0
Question 9
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Marked out of 4.00
The control unit of the processor, explained in class, contains the following circuit that generates the required control signals in each step of the operations:
"Load", "Move", "Add" and "Sub".
If the processor is executing the operation "Sub" and while being in the second step of "Sub" we have:
Select one:
a. T0 = 1
b. T1 = 1
c. T2 = 1
d. T3 = 1
Clear my choice
Question 10
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Consider the below circuit and timing diagram. Indicate the values of registers R0, R1, R2 and R3 at the end of the simulation knowing that all of these registers
contain the value 0 at the beginning of the simulation. Note that all the read/write operations occur at the rising edge of the clock.
Select one:
R0=8 ; R1=8; R2= 5; R3= 8;

R0=8 ; R1=5; R2= 8; R3= 5;
R0=5 ; R1=5; R2= 8; R3= 5;

R0=8 ; R1=8; R2= 8; R3= 8;
None of the answers is correct
R0=5 ; R1=5; R2= 5; R3= 5;
Clear my choice
Question 11
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Complete the VHDL code of a rising-edge D flip-flop that has two inputs D and CLK and two outputs Q and Qprime. This flip flop has one additional input
named CLEAR. When CLEAR is equal to 0, the outputs Q and Qprime will be forced to the values 0 and 1 respectively. Otherwise, the flip flop behaves normally.
Note that the CLEAR input is asynchronous.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dff IS
PORT ( D, CLK, CLEAR : IN STD_LOGIC ;

Q, Qprime : OUT STD_LOGIC) ;
END dff;
ARCHITECTURE Behavior OF dff IS
BEGIN
PROCESS (CLK, CLEAR)
BEGIN
IF CLEAR = ‘0’ THEN
Q <=’0’ ; Qprime <=’1’;
ELSIF Clock’EVENT AND Clock = ’1’ THEN
Q <=D ;
Qprime <=NOT (D);
END IF;
END PROCESS ;
END Behavior;
PROCESS (CLK, CLEAR) PROCESS (CLK) PROCESS (CLEAR) CLEAR = ‘0’ CLEAR = ‘1’ Q <=’0’ ; Qprime <=’1’;
Q <=’1’ ; Qprime <=’0’; Q <=D ;
Question 12
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Consider the VHDL package containing the declaration of the decoders 2-to-4 and 3-to-8 as shown below.
Complete the below structural VHDL code of the decoder 5-to-32 shown below:
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE work.decoders_package.all;
ENTITY dec5to32 IS;
PORT ( w : IN STD_LOGIC_VECTOR(4 DOWNTO 0 );
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 31) );
END dec5to32 ;
ARCHITECTURE structure OF dec5to32 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Dec_ri: dec3to8 PORT MAP( w(2 DOWNTO 0) , m(i) ,
y(8*i TO 8*i+7) ); 
END GENERATE ;
Dec_left: dec2to4 PORT MAP ( w(4 DOWNTO 3) ,
En , m );
END structure ;
work.decoders_package.all; IN STD_LOGIC_VECTOR(4 DOWNTO 0 En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 31) END dec5to32 ; dec5to32
STD_LOGIC_VECTOR(0 TO 3) ; FOR i IN 0 TO 3 GENERATE
dec3to8 w(2 DOWNTO 0) m(i)
y(8*i TO 8*i+7) dec2to4 w(4 DOWNTO 3)
En m structure
Dec_left: ARCHITECTURE
Question 13
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The figure below shows the time diagram of a Gated D latch. Choose the correct values of Q at the specified time instants (A, B, C, D, E, F and G).
Hint: plot the timing diagram on scratch and then answer the question by selecting the correct answer.
Select one:
a. Q(A) =1, Q(B) = 1, Q(C) = 0, Q(D) = 0, Q(E) = 0, Q(F) = 0, Q(G) = 1
b. Q(A) =1, Q(B) = 0, Q(C) = 0, Q(D) = 0, Q(E) = 0, Q(F) = 0, Q(G) = 0
c. Q(A) =1, Q(B) = 1, Q(C) = 0, Q(D) = 1, Q(E) =1, Q(F) = 0, Q(G) = 1
d. Q(A) =0, Q(B) = 0, Q(C) = 0, Q(D) = 1, Q(E) =1, Q(F) = 0, Q(G) = 0
Clear my choice
Question 14
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Marked out of 4.00
The 4-bit comparator is shown in the figure below. It compares two unsigned 4-bit numbers A = (a3 a2 a1 a0)2 and B = (b3 b2 b1 b0)2, and generates three
signals AeqB, AgtB and AltB as follows:
AeqB=1 if A=B
AgtB=1 if A > B
AltB=1 if A<B. Note that the circuit should be completed to generate this signal.
By completing the circuit of AltB, determine the total delay of this comparator knowing that all gates have same delay Δ.
Select one:
a.
4Δ
b. 3Δ
c. 2Δ
d. 5Δ
Clear my choice
Question 15
Not yet answered
Marked out of 4.00
Consider the following circuit in which registers can swap their values. The component connected to the output of each register is a NOT gate.
Select one:
True
False
Question 16
Not yet answered
Marked out of 6.00
Consider the following circuit. Drag and drop the text into the corresponding gaps in the VHDL code that corresponds to the circuit shown in the Figure.
ENTITY mux4to1 IS
PORT ( s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
w0, w1, w2, w3 : IN STD_LOGIC ;
f : OUT STD_LOGIC );
END mux4to1 ;
ARCHITECTURE Structure OF mux4to1 IS

SIGNAL y: STD_LOGIC_VECTOR(0 TO 3);
BEGIN
Dec: dec2to4 PORT MAP( s, 1, y );
f<=(w0 AND y(0) ) OR ( w1 AND y(1)) OR (w2
AND y(2)) OR (w3 AND y(3)) ;
END Behavior ;
Question 17
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Marked out of 6.00
The Register described in the below VHDL code:
Select one or more:

a. Reads the input bits serially and outputs them in parallel
b. Reads the input bits in parallel and outputs them serially
c. Has a Non-Synchronous Clear
d. Has a Synchronous Clear
Question 18
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Marked out of 5.00
Complete the below VHDL code of a N-bit (generic) parallel load up/down counter with Asynchronous reset.
The counter has the following inputs:
1. W has a size of N bits. Default of N is 16
2. direction, clock, Load each has a size of 1 bit
and the output "COUNT_OUT" that has a size of N bits
The counter works like follows:

- The counter is sensitive on the falling-edge of the clock
- When Load equals one , the counter should be counting up or counting down depending on the direction:
if direction is 1 then the counter will count down
if the direction is 0 then the counter will count up
- When Load is zero, the counter will load the value of its input W on its output "OUT"
- Reset is active-High and is responsible of resetting the counter. Resetting will force the output "OUT" to:
zeros if the direction is '1'
ones if the direction is '0'
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Counter IS
GENERIC (N: INTEGER := 16 );
PORT ( Reset, CLK , direction, Load: IN STD_LOGIC;
W: IN STD_LOGIC_VECTOR ( N‑1 DOWNTO 0 );
COUNT_OUT: BUFFER STD_LOGIC_VECTOR (N-1 DOWNTO 0));

END Counter ;
ARCHITECTURE Behavior OF Counter IS

BEGIN
PROCESS ( Reset,Clock, direction ) BEGIN
IF Reset = '1' THEN
IF direction = '1' THEN

COUNT_OUT<= ( others => '0');
ELSE
COUNT_OUT<= (others=> '1');
END IF
ELSIF Clock' event and Clock= '0' THEN
IF Load ='0' THEN
COUNT_OUT<= W ;
ELSIF direction='0'THEN
COUNT_OUT<= COUNT_OUT+1 ;
ELSE
COUNT_OUT <= COUNT_OUT‑1 ;

END IF;
END IF;
END PROCESS ;
END Behavior ;
8 6 32 N
N+1 Counter
UPTO 1 "1"
Clock rising falling
output input signal
Question 19
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Marked out of 4.00
In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to
implement the same?
Select one:
a. WITH-SELECT
b. WITH-SELECT-WHEN
c. IF-ELSE
d. CASE
Clear my choice
Question 20
Not yet answered
Marked out of 5.00
The code given below is a VHDL implementation of:
Select one:
a. 2 to 4 decoder
b. 4 to 2 encoder
c. 4 to 1 MUX
d. None of the options
Clear my choice

Dashboard Courses Soen Digital Logic II (Beirut - Section B - 193068) Fall 2021 - 2022 General CENG335-Final-Exam-Fall-2021-2022

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1/19/22, 3:29 PM CENG335-Final-Exam-Fall-2021-2022

Marked out of 5.00

PORT ( X : IN STD_LOGIC_VECTOR(N−1 DOWNTO 0) ;

ARCHITECTURE Behavior OF trin IS

GENERIC ( N : INTEGER := 16 ) ; GENERIC ( N : INTEGER := 8 ) ; GENERIC ( N : INTEGER := 32 ) ;

GENERIC ( N : INTEGER := 2 x 8 ) ; STD_LOGIC_VECTOR(N−1 DOWNTO 0) STD_LOGIC_VECTOR(15 DOWNTO 0)

STD_LOGIC_VECTOR(16 DOWNTO 0) PROCESS (X,E) PROCESS (X)

PROCESS (E) E ='1' E ='0'

E ='Z' F <= X; F <= E;

F<= (OTHERS=>'Z'); END IF; END PROCESS;

Marked out of 5.00

Positive-edge-triggered flip flop

Positive-edge-triggered flip flop with asynchronous clear

Negative-edge-triggered flip flop

Not yet answered

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GENERIC (N: INTEGER :=8);

PORT(Clock, SI, LEFT_RIGHT, Reset,L : IN STD_LOGIC;

R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);

Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0));

ARCHITECTURE Behavior OF shift IS

IF L='1' THEN Q => R;

ELSIF ( Clock'EVENT AND Clock='1' ) THEN

Q <= Q(N-2 DOWNTO 0) & SI;

LEFT_RIGHT='1' SI & Q(N‑1 DOWNTO 1)

SI & Q(N‑2 DOWNTO 0) IF Reset = '0' THEN Q <= 0 LEFT_RIGHT='0'

Clock'EVENT AND Clock='0'

Marked out of 6.00

a3 = b3 and a2 = b2 and a1 > b1 , ,

a3 = b3 and a2 = b2 and a1 = b1 and a0 > b0

Not yet answered

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b. R3out = [(I1T1 + I2T2 + I3T2 ]Y0 + (I2+ I3)T1X0

c. R3out = [(I1T1 + I2T2 + I3T2 ]X3 + (I2+ I3)T1Y3

d. R3out = [(I1T1 + I2T2 + I3T3 ]Y3 + (I2+ I3)T3X3

Time left 0:01:52

Not yet answered

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A 4-bit ALU has the following ports:

Port Name Mode Size Data Type

inp_a input 4 bits SIGNED

inp_b input 4 bits SIGNED

sel input 3 bits STD_LOGIC_VECTOR

out_alu output 4 bits SIGNED

000 inp_a + inp_b

001 inp_a - inp_b

100 inp_a AND inp_b

101 inp_a OR inp_b

110 NOT inp_a

111 inp_a XOR inp_b;

Port ( inp_a : in signed ____[4]___;

inp_b : in signed(3 downto 0);

___ [6]___ : out signed(3 downto 0));

architecture Behavioral of alu is

out_alu<= inp_a + inp_b;

out_alu<= inp_a - inp_b;

when "011" =>

when "100" =>

when "101" =>

when "110" =>

out_alu<= inp_a xor inp_b; when ___[12]___ =>

Marked out of 5.00

Port ( inp_a : in signed __[4]_;

_ [6]_ : out signed(3 downto 0));

out_alu<= inp_a xor inp_b; when _[12]_ =>

y(8i TO 8i+7) dec2to4 w(4 DOWNTO 3)