VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

SPI DESIGN
PROJECT REPORT

MAVEN SILICON- GLOBAL COURSE

MADE BY:
VANYA NANDWANI
21BEC0434

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

INDEX

Topic Page no.

Core Registers 3

SPI Architecture 6

Data Transfer Waveforms 7

SPI Master Core 8

Clock Generator 9

Shift Register 10

Serial Slave 13

SPI TOP MODULE 12

Conclusion 16

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 VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

CORE REGISTERS LIST:

Name Access Address Description
Rx0 R 0x00 Data Receive Register 0
Rx1 R 0x04 Data Receive Register 1
Rx2 R 0x08 Data Receive Register 2
Rx3 R 0x0c Data Receive Register 3
Tx0 R/W 0x00 Data Transmit Register 0
Tx1 R/W 0x04 Data Transmit Register 1
Tx2 R/W 0x08 Data Transmit Register 2
Tx3 R/W 0x0c Data Transmit Register 3
CTRL R/W 0x10 Control and Status Register
DIVIDER R/W 0x14 Clock divider Circuit
SS R/W 0x18 Slave Select register.

All registers are 32-bit wide and accessible only with 32 bits
• The Data Receive registers hold the value of received data of the last executed
transfer. Valid bits depend on the character length field in the CTRL register
(i.e. if CTRL[9:3] is set to 0x08, bit RxL[7:0] holds the received data). If
character length is less or equal to 32 bits, Rx1,Rx2 and Rx3 are not used, if
character length is less than 64 bits, Rx2 and Rx3 are not used and so on.

• The Data Receive registers hold the data to be transmitted in the next transfer.
Valid bits depend on the character length field in the CTRL register (i.e. if
CTRL[9:3] is set to 0x08, the bit Tx0[7:0] will be transmitted in next transfer).
If character length is less or equal to 32 bits, Tx1, Tx2 and Tx3 are not used, if
character len is less than 64 bits, Tx2 and Tx3 are not used and so on.

• CTRL REGISTERS
Bit# 31:14 13 12 11 10 9 8 7 6:0

Access R R/W R/W R/W R/W R/W R/W R R/W

Name Reserved ASS 1E LSB TX_NEG RX_NEG GO_BUSY Reserved CHAR_LEN

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

1. ASS: If this bit is set, ss_pad_o signals are generated automatically.

This means that slave select signal, which is selected in SS register is
asserted by the SPI controller, when transfer is started by setting
CTRL[GO_BSY] and is de-asserted after transfer is finished. If this
bit is cleared, slave select signals are asserted and de-aserted by
writing and clearing bits in SS register.

2. IE:If this bit is set, the interrupt output is set active after a transfer is
finished. The Interrupt signal is deasserted after a Read or Write to
any register.

3. LSB: If this bit is set, the LSB is sent first on the line (bit TxL[0]), and
the first bit received from the line will be put in the LSB position in
the Rx register (bit RxL[0]). If this bit is cleared, the MSB is
transmitted/received first (which bit in TxX/RXX register that is
depends on the CHAR_LEN field in the CTRL register).

4. Tx_NEG:

If this bit is set, the mosi_pad_o signal is changed on the falling edge
of a sclk_pad_o clock signal, or otherwise the mosi_pad_o signal is
changed on the rising edge of sclk_pad_o.

5. Rx NEG:
If this bit is set, the miso_pad_i signal is latched on the falling edge of
a sclk_pad_o clock signal, or otherwise the miso_pad_i signal is
latched on the rising edge of sclk_pad_o.

6. GO_BUSY:

Writing 1 to this bit starts the transfer. This bit remains set during the
transfer and is automatically cleared after the transfer finished.
Writing 0 to this bit has no effect.

7. CHAR LEN:
This field specifies how many bits are transmitted in one transfer. Up
to 64 bits can be transmitted.

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

CHAR_LEN = 0x01 ... 1 bit

CHAR_LEN = 0x02 ... 2 bits
CHAR_LEN = 0x7f... 127 bits
CHAR_LEN = 0x00 ... 128 bits

• DIVIDER REGISTER:
Bit# 31:16 15:0
Access R R/W
Name Reserved DIVIDER

The value in this field is the frequency divider of the system clock wb_clk_i to
generate the serial clock on the output sclk_pad_o. The desired frequency is
obtained according to the following equation:

• SLAVE SELECT:
Bit# 31:8 7:0
Access R R/W
Name Reserved SS

If CTRL[ASS] bit is cleared, writing 1 to any bit location of this field sets the
proper ss_pad_o line to an active state and writing O sets the line back to
inactive state. If CTRL[ASS] bit is set, writing 1 to any bit location of this field
will select appropriate ss_pad_o line to be automatically driven to active state
for the duration of the transfer, and will be driven to inactive state for the rest of
the time.

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 VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

SPI ARCHITECTURE:
Serial Peripheral Interface (SPI) is a master – slave type protocol that provides a
simple and low-cost interface between a microcontroller and its peripherals ICs
such as sensors, ADC’s, DAC’s, shift register, SRAM and others. In SPI protocol,
there can be only one master but many slave devices.

The SPI bus consists of 4 signals or pins. They are

● Master – Out / Slave – In (MOSI)

● Master – In / Slave – Out (MISO)
● Serial Clock (SCLK) and ● Slave Select (SS)

The Serial Peripheral Interface (SPI) is an essential communication protocol used

in various electronic systems.

ss_pad_o

WISHBONE SPI sclk_pad_ SPI

WISHBONE MASTER o SERIAL
MASTER mosi_pad_
INTERFACE CORE SLAVE
o
miso_pad
_i

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

Data Transfer Waveforms:

1. For TX_NEG=1 AND RX_NEG=0

2. For TX_NEG=1 AND RX_NEG=0

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

SPI MASTER CORE :

CLOCK GENERATOR

SPI SHIFT
MASTER REGISTER

CORE

The SPI (Serial Peripheral Interface) master core is a crucial component in

embedded systems and integrated circuits, providing an efficient means of
communication with peripheral devices.

Features of SPI Master Core:

● Full duplex synchronous serial data transfer

● Variable length of transfer word up to 128 bits
● MSB or LSB first data transfer
● Rx and Tx on both rising or falling edge of serial clock independently
● 8 slave select lines
● Fully static synchronous design with one clock domain
● Technology independent Verilog
● Fully synthesizable

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 VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

CLOCK GENERATOR:
BLOCK DIAGRAM:

wb_clk sclk_out
wb_rst

tip Clock
cpol_0
go generator
divider
cpol_1
last_clk

OUTPUTs:
• Sclk_out: It is the serial clock output that is generated.
• cpol_0 & cpol_1:The serial transmission is done based on the rising or falling
edges. Therefore, the rising edge and the falling edge will be indicated and
detected by cpol_0 and cpol_1.

INPUTs:
• If tip is 1 that means serial transfer is happening.
• go input is a part of CTRL registers {GO_BUSY} so whatever serial
transmission is to be done that happens only if go is 1.
• Divider tells by what value the wishbone clock has to be divided. It is 16 bits

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

OUTPUT WAVEFORM:

SHIFT REGISTER:

It is used to implement the shifting logic. It calculates the transfer in progress and
the last character indicator. It also calculates the serial output based on the clock
signals and the current bit position.

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

BLOCK DIAGRAM:

sclk_out
CLOCK cpol_0
mosi
GENERATOR cpol_1
tip
wb_clk
SHIFT
wb_rst
rx_negedge REGISTER
tx_negedge p_out
BLOCK
lsb
byte_sel
latch last
len
p_in
miso

In the context of a Shift Register used in a Serial Peripheral Interface (SPI), the
input and output ports have specific functionalities. Here's an explanation of the
purpose and use of each port:
Inputs:
1. rx_negedge: Input signal, indicates the negative edge of the receive
clock.
2. tx_negedge: Input signal, indicates the negative edge of the transmit
clock.
3. byte_sel: 4-bit input signal used for byte selection.
4. latch: Input signal used for latch control.
5. len: 32-bit input signal representing the length of the character.
6. p_in: 32-bit input signal for the incoming data.
7. wb_clk_in: Input clock signal (system clock).
8. wb_rst: Input reset signal.
9. go: Input signal to initiate the transfer.
10. miso: Input signal for the master input slave output.
11. lsb: Input signal indicating the least significant bit.
12. cpol_0: Input signal for the pulse marking the positive edge of the
sclk_out.
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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

13. cpol_1: Input signal for the pulse marking the negative edge of the
sclk_out.
Outputs:
1. mosi: Master Out Slave In, the output line for transmitting data to the
peripheral device.
2. tip: Signal indicating the state of the transaction in progress.
3. p_out: Output signal for parallel data shifted out of the register.
4. last: Signal indicating the end of the data transfer process.
Each of these input and output ports plays a crucial role in controlling the data flow
and communication process within the SPI shift register, facilitating the seamless
transfer of data between the master and slave devices in the SPI network.
OUTPUT WAVEFORM:
MISO:

MOSI:

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

Serial Slave:

mosi
sclk miso
SPI SLAVE
Ss_pad_o

Inputs:
1. sclk_out: Serial clock signal received from the master device, which
synchronizes the data transmission.
2. mosi (Master Out Slave In): The input line for receiving data from the
master device.
3. cpol_0 and cpol_1: Control signals that define the idle state of the clock for
data sampling and shifting.
4. rx_negedge: Control signal determining the edge sensitivity for data
reception in the SPI module.
5. lsb: Control signal for selecting the data transmission order, either Least
Significant Bit (LSB) first or Most Significant Bit (MSB) first.
6. byte_sel: Control signal used to select the byte order during data
transmission.
7. latch: Signal used for latching data in the shift register.
8. len: Control signal defining the length of the data during the transmission
process.
Outputs:
1. sclk_out: Serial clock signal transmitted to the master device, synchronized
with the data transmission.
2. miso (Master In Slave Out): The output line for transmitting data to the
master device.
3. tip: Signal indicating the state of the transaction in progress.
4. p_out: Output signal for parallel data shifted out of the register.
5. last: Signal indicating the end of the data transfer process.

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 VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

SPI TOP MODULE:

In an SPI (Serial Peripheral Interface) design, the SPI top module refers to the highest-level
module that coordinates and manages the overall SPI communication. It serves as the primary
interface for the SPI bus and orchestrates the interactions between the SPI master and slave
devices.

WISHBONE MASTER WITH SPI MASTER CORE:

4 bit sel
wb_clk
cyc_out
wb_rst
str
ack
WISHBONE write_enable

error 32-bit data_out

32-bit data_in Address 5 bit

tip
CLOCK GENERATOR go
divider
t
Sclk_ou
Cpol_0
Cpol_1
Last_clk

wb_clk
wb_rst
miso SHIFT REGISTER P_out
lsb mosi
Byte_sel
ack
int
Pin 32

ss
Latch

SPI MASTER CORE

len

biit

Wb_data
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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

Wishbone Master:

Inputs:
• Wishbone Clock (wb_clk): The system clock used to synchronize the
Wishbone bus operations.
• Wishbone Reset (wb_rst): The reset signal used to reset the Wishbone
master module and its associated components.

Outputs:
• Wishbone Address : The output port carrying the address information for the
data transfer.
• Wishbone Data Out: The output port for sending data from the master to the
slave.
• Wishbone Data Strobe: The output signal indicating a valid data transfer
during a write operation.
• Wishbone Slave Select: The output signal used for selecting the slave
component during data transfer.
SPI Master Core:
• Consists of Shift Register block
• Consists of Clock Generator block
• Outputs: acknowledge,interrupt,serial slave,wishbone data,serial clock
output and parallel output alongwith master out slave input.

OUTPUT WAVEFORM:
1. RX negedge = 1 and TX negedge = 0

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VANYA NANDWANI 21BEC0434 SPI DESIGN PROJECT

2. RX negedge =0 and TX negedge = 1

CONCLUSION:
The top module along with the sub blocks was successfully implemented and
designed using MODELSIM and the block diagrams for the same were made
successfully.

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