LAB MANUAL

CMOS Digital Integrated Circuits Laboratory

BIRLA VISHVAKARMA MAHAVIDYALAYA

1|Page
 CERTIFICATE

This is to certify that Meshwa Naik of THIRD YEAR (5TH Semester), ID No.
20EC437has completed her term work in the subject CMOS Digital Integrated
Circuits Laboratory (3EC05) satisfactorily in the department of Electronics and
Communication.

Head Of Department Course Coordinator

(Dr. Bhargav C Goradiya) (Dr. Robinson Paul)

2|Page
 INDEX
Sr. Aim Page Date Sign
No. No.

1. Introduction to layout design software- Microwind. 4

2. To Study MOSIS (MOS Implementation System) layout 6

Design Rules.
3. To Study and implement n-MOS transistor and its V-I 8
characteristic using Microwind.
4. To Study and implement p-MOS transistor and its V-I 10
characteristic using Microwind.
5. To Study and implement CMOS Inverter using 12
Microwind.
6. To Study and implement NAND, AND gate using 15
Microwind.
7. To Study and implement NOR, OR gate using 21
Microwind.
8. To Study and implement XNOR gate using Microwind. 25

9. To Study and implement XOR gate using Microwind. 27

10. Introduction to DSCH Software and Verilog. 29

11. To Study and implement 2:1 MUX CMOS layout using 32

DSCH and Verilog.
12. To Study and implement Half-Adder CMOS layout using 35
DSCH and Verilog.
13. To Study and implement CMOS Ring Oscillator CMOS 38
layout using DSCH and Verilog.
14. To Study and implement Full Adder CMOS layout using 41
DSCH and Verilog.
15. To Study and implement Two-bit Comparator CMOS 44
layout using DSCH and Verilog.
16. To Study and implement Edge Triggered D-Flip Flop 49
CMOS layout using DSCH and Verilog.

3|Page
 PRACTICAL: 1

AIM: Introduction to layout design software-Microwind.

APPARATUS: Microwind 3.1 Software.
THEORY: MICROWIND is truly integrated EDA software encompassing IC designs from concept to
completion, enabling chip designers to design beyond their imagination. MICROWIND integrates
traditionally separated front-end and back-end chip design into one flow, accelerating the design cycle and
reduces design complexities.
It tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-
level extraction and verification – providing an innovative education initiative to help individuals to
develop the skills needed for design positions in virtually every domain of IC industry.
The MICROWIND software allows the designer to simulate and design an integrated circuit at physical
description level. Born in Toulouse (France), Microwind is an innovative CMOS design tool for educational
market.
Microwind is developed as comprehensive package on windows platform to enable students to learn smart
design methods and techniques with more practice. With inbuilt layout editing tools, mix-signal simulator,
MOS characteristic viewer and more, it allows students to learn complete design process with ease.
Microwind unifies schematic entry, pattern based simulator, SPICE extraction of schematic, Verilog
extractor, layout compilation, on layout mix-signal circuit simulation, cross sectional & 3D viewer, netlist
extraction, BSIM4 tutorial on MOS devices and sign-off correlation to deliver unmatched design
performance and productivity.
With its approach for CMOS design education, Microwind has gained lot followers worldwide. Universities
across the globe are using Microwind for budding engineers to teach CMOS concepts with ease. Paving
their path for more skilled softwares to be used at later stage of their course work.
Here are some screen shots of the microwind application

This is the pallete from where you can select different materials and put them on the blank space to make your cmos
circuit. There is also a screen where you can simulate your circuit.

4|Page
CONCLUSION: Here we learnt about how you can use microwind to make your cmos layout.

5|Page
 PRACTICAL: 2

AIM: To Study MOSIS (MOS Implementation System) layout Design Rules.

APPARATUS: Microwind 3.1 Software.
Theory:
Layout design rules: For complex processes, it becomes difficult to understand the intricacies of fabrication
process and interpret different phot masks. Layout design rules act as interface between circuit designer and
process engineer.
We have different types of cmos layout rules like
Layout design rules: Well rules
N-well is deeper mounted than any other transistor implants. Clearance between n-well edges and n+
diffusion should be good enough.
This clearance is usually determined by the oxide transition time across the well boundary.
The other rule is grounding n-well, providing sufficient number of well taps. This will prevent significant
voltage drops due to well current.
Layout design rules: Transistor rules
transistor is designed with at least for masks:
active mask – defines where p- or n-diffusion type or gates will be placed;
n-implant mask – defines areas where n-type diffusion is required; n-type diffusion in p-wells define nMOS
transistors; p-type diffusion in n-wells defines pMOS transistors;
p-implant mask – defines where p-type diffusion is required;p-type diffusion in n-wells define n-type
contacts.; p-type diffusion in p-wells define p-well contacts
polysilicon mask – crossing of polysilicon and diffusion mask defines the gates of transistor.
Polysilicon mask should cover active mask and extend beyond that area, otherwise transistor will be
shorted with the diffusion path between source and drain. Crossing of polisilicon and active mask create
gate of transistors. Polysilicon and active masks that does not form a transistor should be kept separately.
Layout design rules: Contacts rules
Types of contacts:
metal to p-active (p-diffusion)
metal to n-active (n-diffusion)
metal to polysilicon
metal to well or substrate
Metal rules
Metal spacing can be different depending on the metal line. But there is certain width applied to small and
thick wires. So if there is a need of wider wires, they can be made of several small wires connected together.
6|Page
Via (vertical interconnect access) rules
Modern planar technology allows stacked vias.
Other structures
Usually ready chip is marked with scribe lines, where it should be cut. Manufacturer define the construction
of the scribe line.
Alignment mark is placed on the mask to align one mask to another.
Critical dimension test structures are measured after processing to check proper etching of narrow
polysilicon or metal lines.
Vernier structures are used to check alignment between layers.
MOSIS scalable design rules
MOSIS CMOS design rules are λ-scallable. MOSIS CMOS design rules also include SCMOS, SUBM and
DEEP rules variations. For example for SUBM rule λ=0.3μm.

CONCLUSION: Thus, we have studied MOS Implementation system layout design rules.

7|Page
 PRACTICAL: 3

Aim: To study and implement n-MOS transistor and its V-I characteristics using Microwind.
Apparatus: Microwind 3.1 Software
Theory:
An N-channel metal-oxide semiconductor (NMOS) is a microelectronic circuit used for logic and memory
chips and in complementary metal-oxide semiconductor (CMOS) design. NMOS transistors are faster than
the P-channel metal-oxide semiconductor (PMOS) counterpart, and more of them can be put on a single
chip.
NMOS: • Cut off region Vgs< Vt
• Linear region Vgs>=Vt Vds=Vt Vds>= Vgs – Vt
• Saturation region Vgs>=Vt Vds>= Vgs – Vt

Layout design of nMOS:

8|Page
 Waveform of nMOS characteristics:

CONCLUSION: We implemented n-MOS transistor and its V-I characteristics using Microwind.

9|Page
 PRACTICAL: 4

Aim: To study and implement p-MOS transistor and its V-I characteristics using Microwind.
Apparatus: Microwind 3.1 Software.
Theory: PMOS or pMOS logic (from P-channel metal–oxide–semiconductor) is a family of digital
circuits based on p-channel, enhancement mode metal–oxide–semiconductor field-effect
transistors (MOSFETs). In the late 1960s and early 1970s, PMOS logic was the dominant semiconductor
technology for large-scale integrated circuits before being superseded by NMOS and CMOS devices.
PMOS:
• Cut off region Vgs< Vt
• Linear region Vgs>=Vt Vds=Vt Vds>= Vgs – Vt
• Saturation region Vgs>=Vt Vds>= Vgs – Vt

Layout design of pMOS:

10 | P a g e
 Waveform of pMOS:

Conclusion:We implemented p-MOS transistor and its V-I characteristics using Microwind.

11 | P a g e
 PRACTICAL: 5

Aim: To Study and implement CMOS Inverter using Microwind.

Apparatus: Microwind 3.1 Software.

Theory: CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and
adaptable MOSFET inverters used in chip design. They operate with very little power loss and at relatively
high speed. Furthermore, the CMOS inverter has good logic buffer characteristics, in that, its noise
margins in both low and high states are large.

This short description of CMOS inverters gives a basic understanding of the how a CMOS inverter works. It
will cover input/output characteristics, MOSFET states at different input voltages, and power losses due to
electrical current.

A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a
supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal,
were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.(See diagram). It
is important to notice that the CMOS does not contain any resistors, which makes it more power efficient
that a regular resistor-MOSFET inverter. As the voltage at the input of the CMOS device varies between 0
and 5 volts, the state of the NMOS and PMOS varies accordingly. If we model each transistor as a simple
switch activated by VIN, the inverter’s operations can be seen very easily.

12 | P a g e
TRUTH TABLE:

PROCEDURE:
1. To implement CMOS inverter in Microwind3.1 we follow the steps shownbelow.
2. First of all we create a pMOSat the top and nMOS at thebottom.
3. Then we connect them as shown in thediagram.
4. Then we give Vdd to pMOS and ground tonMOS.
5. Then we give input to gate and take output on the otherside.
LAYOUT DESIGN OF CMOS INVERTER:

13 | P a g e
WAVEFORM:

CONCLUSION:
We create the CMOS inverter by following the steps as given.

14 | P a g e
 PRACTICAL 6
AIM: To study and implement NAND, AND gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:
NAND
The NAND gate is a special type of logic gate in the digital logic circuit. The NAND gate is the universal
gate. It means all the basic gates such as AND, OR, and NOT gate can be constructed using a NAND gate.
The NAND gate is the combination of the NOT-AND gate. The output state of the NAND gate will be low
only when all the inputs are high. Simply, this gate returns the complement result of the AND gate.

The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes “LOW”
to logic level “0” when ALL of its inputs are at logic level “1”. The Logic NAND Gate is the reverse or
“Complementary” form of the AND gate.
The logic or Boolean expression given for a logic NAND gate is that for Logical Addition, which is the
opposite to the AND gate, and which it performs on the complements of the inputs.
The Boolean expression for a logic NAND gate is denoted by a single dot or full stop symbol, ( . ) with a
line or Overline, ( ‾‾ ) over the expression to signify the NOT or logical negation of the NAND gate giving
us the Boolean expression of: A.B =Q.

NAND Truth Table

15 | P a g e
AND
An AND gate is a logic gate having two or more inputs and a single output. An AND gate operates on
logical multiplication rules. In this gate, if either of the inputs is low (0), then the output is also low. If all of
the inputs are high (1), then the output will also be high. An AND gate can have any number of inputs,
although 2 input and 3 input AND gates are the most common.

The output state of a digital logic AND gate only returns “LOW” again when ANY of its inputs are at a
logic level “0”. In other words, for a logic AND gate, any LOW input will give a LOW output.
The logic or Boolean expression given for a digital logic AND gate is that for Logical Multiplication
which is denoted by a single dot or full stop symbol, (.) giving us the Boolean expression of: A.B = Q.

PROCEDURE:
 First of all, we create a pMOS at the top and nMOS at the bottom.
 Then we connect them as shown in the diagram.
 Then we give Vdd to pMOS and ground to nMOS.
 Then we give input clock A and B.
 Then we give input to gate and take output on the other side.

16 | P a g e
LAYOUT DESIGN OF NAND GATE:

WAVEFORM:

17 | P a g e
LAYOUT DESIGN OF AND GATE:

18 | P a g e
CONCLUSION:
We create the NAND & AND gate by following the steps as given.

19 | P a g e
 PRACTICAL 7
AIM: To Study and implement NOR, OR gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:
NOR
In CMOS design, the NOR gate consists of two nMOS in parallel connected to two pMOS in series. The
schematic diagram of the CMOS NOR cell is reported below. The nMOS in parallel tie the output to the
ground if either A or B are at 1. When both A and B are at 0, the nMOS path is cut, but the two pMOS
devices in series tie the output to the supply Vdd.
The logic or Boolean expression given for a logic NOR gate is that for Logical Multiplication which it
performs on the complements of the inputs. The Boolean expression for a logic NOR gate is denoted by a
plus sign, (+) with a line or Overline, (‾‾) over the expression to signify the NOT or logical negation of the
NOR gate.

OR
As for the AND gate, the OR gate is the sum of a NOR gate and an inverter. The implementation of the OR2
gate in CMOS layout requires 6 transistors. An arrangement may be found to obtain continuous diffusions
on n-MOS regions and pMOS regions An OR gate is a logic gate that performs logical OR operation.
A logical OR operation has a high output (1) if one or both the inputs to the gate are high (1). If neither input
is high, a low output (0) result. Just like an AND gate, an OR gate may have any number of input probes but
only one output probe.
The function of a logical OR gate effectively finds the maximum between two binary digits, just as the
complementary AND function finds the minimum.

20 | P a g e
PROCEDURE:
 First of all, we create a pMOS at the top and nMOS at the bottom.
 Then we connect them as shown in the diagram.
 Then we give Vdd to pMOS and ground to nMOS.
 Then we give input to gate and take output on the other side.
LAYOUT DESIGN OF NOR GATE:

21 | P a g e
WAVEFORM:

LAYOUT DESIGN OF OR GATE:

22 | P a g e
WAVEFORM:

CONCLUSION:
We create the CMOS NOR and OR GATE by following the steps as given.

23 | P a g e
 PRACTICAL 8
AIM: To study and implement XNOR gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:
XNOR gate also known as Exclusive-NOR or Exclusive-Negative OR gate is “A logic gate which produces
High state “1” only when there is an even number of High states “1” inputs”. For 2-input gate, it can be
interpreted as when both of the inputs are same, then the output is High state and when the inputs are
different, then the output is Low state “0”. XNOR gate can have two or more than two inputs but it has only
one output. This gate is also used for equality.

PROCEDURE:
 First place a p+ diffusion from the palette.
 Then place n+ diffusion right below the p+ diffusion.
 Then put n-well across P+ diffusion.
 We will put four polysilicon layers.
 Connect the P contact, N contact and polysilicon contact wherever necessary.
 Connect Vdd+ and Vss-(ground) wherever necessary.
 Connect clock sources at all the 4 polysilicon contact sources.
 The four input should be such that there will be two different inputs X and Y and the other two
will be the complementary of these two inputs ~X and ~Y.

24 | P a g e
LAYOUT DESIGN OF XNOR:

WAVEFORM:

CONCLUSION:
We follow the steps given and create XNOR gate in Microwind 3.1.

25 | P a g e
 PRACTICAL 9
AIM: To study and implement XOR gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:
The XOR gate stands for the Exclusive-OR gate. This gate is a special type of gate used in different types of
computational circuits. Apart from the AND, OR, NOT, NAND, and NOR gate, there are two special gates,
i.e., Ex-OR and Ex-NOR. These gates are not basic gates in their own and are constructed by combining
with other logic gates. Their Boolean output function is significant enough to be considered as a complete
logic gate. The XOR and XNOR gates are the hybrids gates.

The 2-input OR gate is also known as the Inclusive-OR gate because when both inputs A and B are set to 1,
the output comes out 1(high). In the Ex-OR function, the logic output "1" is obtained only when either
A="1" or B="1" but not both together at the same time. Simply, the output of the XOR gate is high(1) only
when both the inputs are different from each other.

The plus(+) sign within the circle is used as the Boolean expression of the XOR gate. So, the symbol of the
XOR gate is ⨁. This Ex-OR symbol also defines the "direct sum of sub-objects" expression.

LAYOUT DESIGN OF XOR:

26 | P a g e
WAVEFORM:

CONCLUSION:
Hence, we have studied and implemented XOR gate in Microwind 3.1.

27 | P a g e
 PRACTICAL 10
AIM: Introduction to DSCH Software and Verilog.
APPARATUS: DSCH Software
THEORY:
DSCH stands for Design Schematic Editor Tool. The DSCH program is logic editor and simulator. The
DSCH3 program is a logic editor and simulator. DSCH3 is used to validate the architecture of the logic
circuit before the microelectronics design is started. DSCH3 provides a user-friendly environment for logic
structures.While using DSCH we can design in three types - Gate Level Design, Chip Level Design,CMOS
Level Design. DSCH also features the symbols, models and assembly support for 8051 & 16F84
controllers.Designers can create logic circuits for interfacing with these controllers and verify software
programs using DSCH.A key innovative feature is the possibility to estimate the power consumption of the
circuit.
Installation :
 Click "Download DSCH3 (ZIP file)". In your PC, create manually a directory (Suggested:
c:\program files\dsch3). Store the dsch2.ZIP file in this directory.
 Extract all files with WinZip in c:\program files\dsch2.
 Test: double click in DSCH3.EXE. Load "base.sch". Click "Simulate".

Home Screen of DSCH3

Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated
circuit (IC) designers. The other one is VHDL. HDL’s allows the design to be simulated earlier in the
design cycle in order to correct errors or experiment with different architectures. Designs described in HDL
are technology-independent, easy to design and debug, and are usually more readable than schematics,
particularly for large circuits.
Verilog can be used to describe designs at four levels of abstraction:
(i) Algorithmic level (much like c code with if, case and loop statements).
(ii) Register transfer level (RTL uses registers connected by Boolean equations).
(iii) Gate level (interconnected AND, NOR etc.).
28 | P a g e
 (iv) Switch level (the switches are MOS transistors inside gates).
The language also defines constructs that can be used to control the input and output of simulation. More
recently Verilog is used as an input for synthesis programs which will generate a gate-level description (a
netlist) for the circuit. Some Verilog constructs are not synthesizable. Also, the way the code is written will
greatly affect the size and speed of the synthesized circuit.
Most readers will want to synthesize their circuits, so non synthesizable constructs should be used only for
test benches. These are program modules used to generate I/O needed to simulate the rest of the design. The
words “not synthesizable” will be used for examples and constructs as needed that do not synthesize.
Verilog has four levels of modelling:
The switch level which includes MOS transistors modelled as switches.
 The gate level.
 The Data-Flow level.
 The Behavioural or procedural level.

Menu Bar Description

29 | P a g e
Highlights
● User-friendly environment for rapid design of logic circuits.
● Supports hierarchical logic design.
● The technique allows injection of single stuck-at fault at the nodes of the circuit.
● Improved interface between DSCH and Winspice.
● Handles both conventional pattern-based logic simulation and intuitive on screen mouse driven
simulation.
● Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible
with PSPICETM and WinSpiceTM).
● Generates a VERILOG description of the schematic for layout conversion.
● Immediate access to symbol properties (Delay, fanout).
● Model and assembly support for 8051 and PIC 16F84 microcontrollers.
● Sub-micron, deep-submicron, nanoscale technology support.
● Supported by huge symbol library.
CONCLUSION:
Hence, we have introduced DSCH Software and learnt its functions and we have also studied about Verilog.

30 | P a g e
 PRACTICAL 11
AIM: To Study and implement 2:1 MUX CMOS layout using DSCH and Verilog.
APPARATUS: Microwind 3.1 Software and DSCH Software
THEORY:
A multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the
selected input into a single line. A multiplexer of 2^n inputs has n select lines, which are used to select
which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can
be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data
selector. Multiplexers can also be used to implement Boolean functions of multiple variables.
The input A of this 2:1 mux circuit constructed from standard NAND gates acts to control which input (I₀
and I₁) gets passed to the output at Q. From the truth table above, we can see that when the data select input,
A is LOW at logic 0, input I₁ passes its data through the NAND gate mux circuit to the output, while input
I₀ is blocked. When the data select A is HIGH at logic 1, the reverse happens and now input I₀ passes data
to the output Q while input I₁ is blocked.
So, by the application of either a logic “0” or a logic “1” at A we can select the appropriate input I₀ or I₁
with the circuit acting a bit like a single pole double throw switch. As we only have one control line then we
can only switch 2 inputs and in this simple example, the 2-input multiplexer connects one of two 1-bit
sources to a common output, producing a 2-to-1 line multiplexer. We can confirm this in the following
Boolean expression.

PROCEDURE:
 Open DSCH software and implement the circuit using gates present on the pallet.
 Stimulate the circuit and verify the truth table of 2:1 MUX.
 Save file with .v extension.
 Go to Files>Make Verilog file, to make Verilog file of the 2:1 MUX circuit in DSCH software.
 A Verilog code will be generated, compile the code.
 If no error is shown then click on Back to editor.
 CMOS layout of 2:1 MUX will be generated.
 Click on RUN and the output waveforms will be generated.

31 | P a g e
Logic Circuit of 2:1 MUX in DSCH:

Verilog code:
module 2TO1MUX( IN1_19EC438,INPUT2_19EC438,SELECT_19EC438,OUT_19EC438);
input IN1_19EC438,INPUT2_19EC438,SELECT_19EC438;
output OUT_19EC438;
wire w5,w6,w8;
or #(16) or2_1(OUT_19EC438,w5,w6);
and #(16) and2_2(w5,w8,IN1_19EC438);
and #(16) and2_3(w6,INPUT2_19EC438,SELECT_19EC438);
not #(10) inv_4(w8,SELECT_19EC438);
endmodule
// Simulation parameters in Verilog Format
always
#1000 IN1_19EC438=~IN1_19EC438;
#2000 INPUT2_19EC438=~INPUT2_19EC438;
#4000 SELECT_19EC438=~SELECT_19EC438;
// Simulation parameters
// IN1_19EC438 CLK 10 10
// INPUT2_19EC438 CLK 20 20
// SELECT_19EC438 CLK 40 40

32 | P a g e
Layout design of 2:1 MUX in Microwind:

Waveform of 2:1 MUX:

CONCLUSION:
Hence, we construct the 2:1 Mux in DSCH Software and also verify its truth table, and by the help of the
Verilog code that is made in DSCH is directly used in the Microwind 3.1 and verifies the output waveform
with the truth table.

33 | P a g e
 PRACTICAL 12
AIM: To study and implement Half-Adder CMOS layout using DSCH and Verilog.
APPARATUS: Microwind 3.1 Software and DSCH Software
THEORY:
The Half-Adder is a basic building block of adding two numbers as two inputs and produce out two outputs.
The adder is used to perform OR operation of two single bit binary numbers. The augent and addent bits are
two input states, and 'carry' and 'sum 'are two output states of the half adder.It gives us the following
Boolean expression of:
SUM = (A B) = A.B’ + A’. B
CARRY = A.B

Logic Circuit of Half Adder in DSCH:

34 | P a g e
Verilog Code:

module HFADDER( A_19EC438,B_19EC438,SUM_19EC438,CARRY_19EC438);

input A_19EC438,B_19EC438;
output SUM_19EC438,CARRY_19EC438;
wire ;
xor #(16) xor2_1(SUM_19EC438,A_19EC438,B_19EC438);
and #(16) and2_2(CARRY_19EC438,B_19EC438,A_19EC438);
endmodule
// Simulation parameters in Verilog Format
always
#1000 A_19EC438=~A_19EC438;
#2000 B_19EC438=~B_19EC438;
// Simulation parameters
// A_19EC438 CLK 10 10
// B_19EC438 CLK 20 20
Layout design of Half Adder in Microwind:

35 | P a g e
Wave Form of Half Adder in Microwind:

CONCLUSION:
Hence, we have generated a circuit which follows the truth table of Half Adder.

36 | P a g e
 PRACTICAL 13
AIM: To study and implement CMOS Ring Oscillator CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates between two
voltage levels, representing true and false. A schematic diagram of a simple three inverter ring oscillator is
shown in Fig.1.

Fig.1: A 3-inverter ring oscillator.

The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first.
Because a single inverter computes the logical NOT of its input, it can be shown that the last output of a
chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a finite
amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation.
A real ring oscillator only requires power to operate; above a certain threshold voltage, oscillations begin
spontaneously. To increase the frequency of oscillation, two methods may be used. Firstly, the applied
voltage may be increased; this increases both the frequency of the oscillation and the power consumed,
which is dissipated as heat.
PROCEDURE:
 Open DSCH software and implement the circuit using gates present on the pallet.
 Stimulate the circuit and verify the truth table of Ring Oscillator.
 Save file with .v extension.
 Go to Files=>Make Verilog file, to make Verilog file of the Ring Oscillator circuit in DSCH
software.
 Open Microwind 3.1 software click on Compile=>Compile Verilog File.
 Select the file with .v extension.
 A Verilog code will be generated, compile the code.
 If no error is shown then click on Back to editor.
 CMOS layout of Ring Oscillator will be generated.
 Click on RUN and the output waveforms will be generated.

37 | P a g e
Architecture of Ring Oscillator in DSCH:

Verilog Code:
module RINGOSCII_19EC438( out1_19EC438,out2_19EC438,out3_19EC438);
output out1_19EC438,out2_19EC438,out3_19EC438;
wire ;
not #(17) inv_1(out1_19EC438,out3_19EC438);
not #(17) inv_2(out2_19EC438,out1_19EC438);
not #(17) inv_3(out3_19EC438,out2_19EC438);
endmodule
Layout design of Ring Oscillator in Microwind:

38 | P a g e
Waveform:

CONCLUSION:
Hence, we successfully studied and implemented implement CMOS Ring Oscillator CMOS layout using
DSCH and Verilog and observed its output in Microwind3.1 We saw the astable behaviour when odd
numbers of inverters are connected into a cascade circuit.

39 | P a g e
 PRACTICAL 14
AIM: To study and implement Full-Adder CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds
three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in
from the previous less-significant stage.[2] The full adder is usually a component in a cascade of adders,
which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output. Output carry and sum
typically represented by the signals Cout and S, where the sum equals 2Cout + S.
A full adder can be implemented in many different ways such as with a custom transistor-level circuit or
composed of other gates. One example implementation is with S = A ⊕ B ⊕ Cin and Cout = (A ⋅ B) +
(Cin ⋅ (A ⊕ B)).

TRUTH TABLE:

PROCEDURE:
 Open DSCH software and implement the circuit using gates present on the pallet.
 Stimulate the circuit and verify the truth table of Full Adder.
 Save the file with .v extension.
 Go to Files=>Make Verilog file, to make Verilog file of the Full Adder circuit in DSCH software.
 Open Microwind 3.1 software click on Compile=>Compile Verilog File.
40 | P a g e
  Select the file with .v extension.
 A Verilog code will be generated, compile the code.
 If no error is shown then click on Back to editor.
 CMOS layout of Full Adder will be generated.
 Click on RUN and the output waveforms will be generated.

Logic Circuit of Full Adder in DSCH:

Verilog Code:
module FULLADD_19EC438(
A_19EC438,B_19EC438,CARRY_19EC438,SUM_19EC438,CARRY_19EC438);
input A_19EC438,B_19EC438,CARRY_19EC438;
output SUM_19EC438,CARRY_19EC438;
wire w4,w7,w8,;
xor #(23) xor2_1(w4,A_19EC438,B_19EC438);
xor #(16) xor2_2(SUM_19EC438,w4,CARRY_19EC438);
and #(16) and2_3(w7,w4,CARRY_19EC438);
and #(16) and2_4(w8,B_19EC438,A_19EC438);
or #(16) or2_5(CARRY_19EC438,w7,w8);
endmodule
// Simulation parameters in Verilog Format
always
#1000 A_19EC438=~A_19EC438;
#2000 B_19EC438=~B_19EC438;
#4000 CARRY_19EC438=~CARRY_19EC438;

// Simulation parameters
// A_19EC438 CLK 10 10
// B_19EC438 CLK 20 20
// CARRY_19EC438 CLK 40 40

41 | P a g e
Layout design of Full Adder in Microwind:

Waveform of Full Adder:

CONCLUSION:
Hence, we have generated a circuit which follows the truth table of Full Adder.

42 | P a g e
 PRACTICAL 15
AIM: To study and implement 2-bit Comparator CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
A 2-bit comparator compares two binary numbers, each of two bits and produces their relation such as one
number is equal or greater than or less than the other. The figure below shows the block diagram of a two-
bit comparator which has four inputs and three outputs.
The first number A is designated as A = A1A0 and the second number is designated as B = B1B0. This
comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B) and L (L= 1 if A<B).

Truth Table:

43 | P a g e
The k-map simplification for the above truth table is as follows.

From the above k-map simplification, each output can be expressed as:

By using above obtained Boolean equation for each output, the logic diagram can be implemented by using
four NOT gates, seven AND gates, two OR gates and two Ex-NOR gates.
The figure below shows the logic diagram of a 2-bit comparator using basic logic gates. It is also possible to
construct this comparator by cascading of two 1-bit comparators.

PROCEDURE:
 Make a logic diagram as shown above in DSCH software.
 Save the file.
 Go to FILE > “Make Verilog File” and generate the Verilog file.

44 | P a g e
  Open Microwind Software.
 Go to COMPILE > “Compile Verilog File” and select the same Verilog file generated using DSCH
and generate CMOS layout.
 Now RUN it to generate the corresponding waveform.

Logic Circuit of 2-bit Comparator in DSCH:

Verilog Code:
module 2BitComparator_19EC438(
A1_19ec438,B0_19ec438,B1_19ec438,A0_19ec438,AeB_19EC438,AsB_19EC438,AiB_19EC438);
input A1_19ec438,B0_19ec438,B1_19ec438,A0_19ec438;
output AeB_19EC438,AsB_19EC438,AiB_19EC438;
wire w3,w6,w8,w9,w10,w11,w13,w14;
wire w15,w16,w18,w19,;
not #(1) inv_1(w3,A0_19ec438);
not #(1) inv_2(w6,B1_19ec438);
not #(1) inv_3(w8,B0_19ec438);
not #(1) inv_4(w9,A1_19ec438);
xnor #(1) xnor2_5(w10,B1_19ec438,A1_19ec438);
xnor #(1) xnor2_6(w11,B0_19ec438,A0_19ec438);
and #(1) and2_7(AeB_19EC438,w11,w10);
and #(1) and3_8(w13,A0_19ec438,w6,w8);
and #(1) and3_9(w14,A1_19ec438,A0_19ec438,w8);
and #(1) and2_10(w15,w6,A1_19ec438);
and #(1) and2_11(w16,B1_19ec438,w9);
or #(1) or3_12(AsB_19EC438,w13,w14,w15);
and #(1) and3_13(w18,w3,B1_19ec438,B0_19ec438);
and #(1) and3_14(w19,w9,w3,B0_19ec438);
or #(1) or3_15(AiB_19EC438,w18,w19,w16);
endmodule

45 | P a g e
// Simulation parameters in Verilog Format
always
#10 A1_19ec438=~A1_19ec438;
#20 B0_19ec438=~B0_19ec438;
#40 B1_19ec438=~B1_19ec438;
#80 A0_19ec438=~A0_19ec438;

// Simulation parameters
// A1_19ec438 CLK 10 10
// B0_19ec438 CLK 20 20
// B1_19ec438 CLK 40 40
// A0_19ec438 CLK 80 80

Layout design of 2-bit Comparator in Microwind:

46 | P a g e
Waveform of 2-bit Comparator:

CONCLUSION:
Hence, we studied about the working of 2-bit Comparator using DSCH and Microwind 3.1 software.

47 | P a g e
48 | P a g e
 PRACTICAL 6
AIM: To study and implement NAND, AND gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:
NAND
The NAND gate is a special type of logic gate in the digital logic circuit. The NAND gate is the universal
gate. It means all the basic gates such as AND, OR, and NOT gate can be constructed using a NAND gate.
The NAND gate is the combination of the NOT-AND gate. The output state of the NAND gate will be low
only when all the inputs are high. Simply, this gate returns the complement result of the AND gate.

The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes “LOW”
to logic level “0” when ALL of its inputs are at logic level “1”. The Logic NAND Gate is the reverse or
“Complementary” form of the AND gate.
The logic or Boolean expression given for a logic NAND gate is that for Logical Addition, which is the
opposite to the AND gate, and which it performs on the complements of the inputs.
The Boolean expression for a logic NAND gate is denoted by a single dot or full stop symbol, ( . ) with a
line or Overline, ( ‾‾ ) over the expression to signify the NOT or logical negation of the NAND gate giving
us the Boolean expression of: A.B =Q.

NAND Truth Table

49 | P a g e
AND
An AND gate is a logic gate having two or more inputs and a single output. An AND gate operates on
logical multiplication rules. In this gate, if either of the inputs is low (0), then the output is also low. If all of
the inputs are high (1), then the output will also be high. An AND gate can have any number of inputs,
although 2 input and 3 input AND gates are the most common.

The output state of a digital logic AND gate only returns “LOW” again when ANY of its inputs are at a
logic level “0”. In other words, for a logic AND gate, any LOW input will give a LOW output.
The logic or Boolean expression given for a digital logic AND gate is that for Logical Multiplication
which is denoted by a single dot or full stop symbol, (.) giving us the Boolean expression of: A.B = Q.

PROCEDURE:
 First of all, we create a pMOS at the top and nMOS at the bottom.
 Then we connect them as shown in the diagram.
 Then we give Vdd to pMOS and ground to nMOS.
 Then we give input clock A and B.
 Then we give input to gate and take output on the other side.

50 | P a g e
LAYOUT DESIGN AND WAVEFORM OF NAND GATE WITH ONE FINGER NMOS AND PMOS

51 | P a g e
LAYOUT DESIGN AND WAVEFORM OF NAND GATE WITH TWO FINGER NMOS AND
PMOS

52 | P a g e
LAYOUT DESIGN AND WAVEFORM OF NAND GATE WITH THREE FINGER NMOS AND
PMOS

53 | P a g e
LAYOUT DESIGN AND WAVEFORM OF NAND & AND GATE FROM ONE :

CONCLUSION:
We create the NAND & AND gate by following the steps as given.

54 | P a g e
 PRACTICAL 7
AIM: To Study and implement NOR, OR gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:
NOR
In CMOS design, the NOR gate consists of two nMOS in parallel connected to two pMOS in series. The
schematic diagram of the CMOS NOR cell is reported below. The nMOS in parallel tie the output to the
ground if either A or B are at 1. When both A and B are at 0, the nMOS path is cut, but the two pMOS
devices in series tie the output to the supply Vdd.
The logic or Boolean expression given for a logic NOR gate is that for Logical Multiplication which it
performs on the complements of the inputs. The Boolean expression for a logic NOR gate is denoted by a
plus sign, (+) with a line or Overline, (‾‾) over the expression to signify the NOT or logical negation of the
NOR gate.

OR
As for the AND gate, the OR gate is the sum of a NOR gate and an inverter. The implementation of the OR2
gate in CMOS layout requires 6 transistors. An arrangement may be found to obtain continuous diffusions
on n-MOS regions and pMOS regions An OR gate is a logic gate that performs logical OR operation.
A logical OR operation has a high output (1) if one or both the inputs to the gate are high (1). If neither input
is high, a low output (0) result. Just like an AND gate, an OR gate may have any number of input probes but
only one output probe.
The function of a logical OR gate effectively finds the maximum between two binary digits, just as the
complementary AND function finds the minimum.

55 | P a g e
PROCEDURE:
 First of all, we create a pMOS at the top and nMOS at the bottom.
 Then we connect them as shown in the diagram.
 Then we give Vdd to pMOS and ground to nMOS.
 Then we give input to gate and take output on the other side.
LAYOUT DESIGN OF NOR GATE:

56 | P a g e
WAVEFORMS OF NOR GATE:

LAYOUT DESIGN OF OR GATE:

57 | P a g e
WAVEFORMS OF OR GATE:

CONCLUSION:
We create the CMOS NOR and OR GATE by following the steps as given.

58 | P a g e
 PRACTICAL 8
AIM: To study and implement XNOR gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:
XNOR gate also known as Exclusive-NOR or Exclusive-Negative OR gate is “A logic gate which produces
High state “1” only when there is an even number of High states “1” inputs”. For 2-input gate, it can be
interpreted as when both of the inputs are same, then the output is High state and when the inputs are
different, then the output is Low state “0”. XNOR gate can have two or more than two inputs but it has only
one output. This gate is also used for equality.

PROCEDURE:
 First place a p+ diffusion from the palette.
 Then place n+ diffusion right below the p+ diffusion.
 Then put n-well across P+ diffusion.
 We will put four polysilicon layers.
 Connect the P contact, N contact and polysilicon contact wherever necessary.
 Connect Vdd+ and Vss-(ground) wherever necessary.
 Connect clock sources at all the 4 polysilicon contact sources.
 The four input should be such that there will be two different inputs X and Y and the other two
will be the complementary of these two inputs ~X and ~Y.

59 | P a g e
LAYOUT DESIGN OF XNOR:

WAVEFORM:

CONCLUSION:
We follow the steps given and create XNOR gate in Microwind 3.1.

60 | P a g e
 PRACTICAL 9
AIM: To study and implement XOR gate using Microwind.
APPARATUS: Microwind 3.1 Software
THEORY:

The XOR gate stands for the Exclusive-OR gate. This gate is a special type of gate used in different types of
computational circuits. Apart from the AND, OR, NOT, NAND, and NOR gate, there are two special gates,
i.e., Ex-OR and Ex-NOR. These gates are not basic gates in their own and are constructed by combining
with other logic gates. Their Boolean output function is significant enough to be considered as a complete
logic gate. The XOR and XNOR gates are the hybrids gates.

The 2-input OR gate is also known as the Inclusive-OR gate because when both inputs A and B are set to 1,
the output comes out 1(high). In the Ex-OR function, the logic output "1" is obtained only when either
A="1" or B="1" but not both together at the same time. Simply, the output of the XOR gate is high(1) only
when both the inputs are different from each other.

The plus(+) sign within the circle is used as the Boolean expression of the XOR gate. So, the symbol of the
XOR gate is ⨁. This Ex-OR symbol also defines the "direct sum of sub-objects" expression.

Layout design of XOR Gate in Microwind:

61 | P a g e
Waveform:

CONCLUSION:
Hence, we have studied and implemented XOR gate in Microwind 3.1.

62 | P a g e
 PRACTICAL 10
AIM: Introduction to DSCH Software and Verilog.
APPARATUS: DSCH Software
THEORY:
DSCH stands for Design Schematic Editor Tool. The DSCH program is logic editor and simulator. The
DSCH3 program is a logic editor and simulator. DSCH3 is used to validate the architecture of the logic
circuit before the microelectronics design is started. DSCH3 provides a user-friendly environment for logic
structures.While using DSCH we can design in three types - Gate Level Design, Chip Level Design,CMOS
Level Design. DSCH also features the symbols, models and assembly support for 8051 & 16F84
controllers.Designers can create logic circuits for interfacing with these controllers and verify software
programs using DSCH.A key innovative feature is the possibility to estimate the power consumption of the
circuit.
Installation :
 Click "Download DSCH3 (ZIP file)". In your PC, create manually a directory (Suggested:
c:\program files\dsch3). Store the dsch2.ZIP file in this directory.
 Extract all files with WinZip in c:\program files\dsch2.
 Test: double click in DSCH3.EXE. Load "base.sch". Click "Simulate".

Home Screen of DSCH3

Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated
circuit (IC) designers. The other one is VHDL. HDL’s allows the design to be simulated earlier in the
design cycle in order to correct errors or experiment with different architectures. Designs described in HDL
are technology-independent, easy to design and debug, and are usually more readable than schematics,
particularly for large circuits.
Verilog can be used to describe designs at four levels of abstraction:
(v) Algorithmic level (much like c code with if, case and loop statements).
(vi) Register transfer level (RTL uses registers connected by Boolean equations).
(vii) Gate level (interconnected AND, NOR etc.).
63 | P a g e
 (viii) Switch level (the switches are MOS transistors inside gates).
The language also defines constructs that can be used to control the input and output of simulation. More
recently Verilog is used as an input for synthesis programs which will generate a gate-level description (a
netlist) for the circuit. Some Verilog constructs are not synthesizable. Also, the way the code is written will
greatly affect the size and speed of the synthesized circuit.
Most readers will want to synthesize their circuits, so non synthesizable constructs should be used only for
test benches. These are program modules used to generate I/O needed to simulate the rest of the design. The
words “not synthesizable” will be used for examples and constructs as needed that do not synthesize.
Verilog has four levels of modelling:
The switch level which includes MOS transistors modelled as switches.
 The gate level.
 The Data-Flow level.
 The Behavioural or procedural level.

Menu Bar Description

64 | P a g e
Highlights
● User-friendly environment for rapid design of logic circuits.
● Supports hierarchical logic design.
● The technique allows injection of single stuck-at fault at the nodes of the circuit.
● Improved interface between DSCH and Winspice.
● Handles both conventional pattern-based logic simulation and intuitive on screen mouse driven
simulation.
● Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible
with PSPICETM and WinSpiceTM).
● Generates a VERILOG description of the schematic for layout conversion.
● Immediate access to symbol properties (Delay, fanout).
● Model and assembly support for 8051 and PIC 16F84 microcontrollers.
● Sub-micron, deep-submicron, nanoscale technology support.
● Supported by huge symbol library.
CONCLUSION:
Hence, we have introduced DSCH Software and learnt its functions and we have also studied about Verilog.

65 | P a g e
 PRACTICAL 11
AIM: To Study and implement 2:1 MUX CMOS layout using DSCH and Verilog.
APPARATUS: Microwind 3.1 Software and DSCH Software
THEORY:
A multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the
selected input into a single line. A multiplexer of 2^n inputs has n select lines, which are used to select
which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can
be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data
selector. Multiplexers can also be used to implement Boolean functions of multiple variables.
The input A of this 2:1 mux circuit constructed from standard NAND gates acts to control which input (I₀
and I₁) gets passed to the output at Q. From the truth table above, we can see that when the data select input,
A is LOW at logic 0, input I₁ passes its data through the NAND gate mux circuit to the output, while input
I₀ is blocked. When the data select A is HIGH at logic 1, the reverse happens and now input I₀ passes data
to the output Q while input I₁ is blocked.
So, by the application of either a logic “0” or a logic “1” at A we can select the appropriate input I₀ or I₁
with the circuit acting a bit like a single pole double throw switch. As we only have one control line then we
can only switch 2 inputs and in this simple example, the 2-input multiplexer connects one of two 1-bit
sources to a common output, producing a 2-to-1 line multiplexer. We can confirm this in the following
Boolean expression.

PROCEDURE:
 Open DSCH software and implement the circuit using gates present on the pallet.
 Stimulate the circuit and verify the truth table of 2:1 MUX.
 Save file with .v extension.
 Go to Files>Make Verilog file, to make Verilog file of the 2:1 MUX circuit in DSCH software.
 A Verilog code will be generated, compile the code.
 If no error is shown then click on Back to editor.
 CMOS layout of 2:1 MUX will be generated.
 Click on RUN and the output waveforms will be generated.

66 | P a g e
Logic Circuit of 2:1 MUX in DSCH:

Verilog code:
module 2TO1MUX( IN1_19EC438,INPUT2_19EC438,SELECT_19EC438,OUT_19EC438);
input IN1_19EC438,INPUT2_19EC438,SELECT_19EC438;
output OUT_19EC438;
wire w5,w6,w8;
or #(16) or2_1(OUT_19EC438,w5,w6);
and #(16) and2_2(w5,w8,IN1_19EC438);
and #(16) and2_3(w6,INPUT2_19EC438,SELECT_19EC438);
not #(10) inv_4(w8,SELECT_19EC438);
endmodule
// Simulation parameters in Verilog Format
always
#1000 IN1_19EC438=~IN1_19EC438;
#2000 INPUT2_19EC438=~INPUT2_19EC438;
#4000 SELECT_19EC438=~SELECT_19EC438;
// Simulation parameters
// IN1_19EC438 CLK 10 10
// INPUT2_19EC438 CLK 20 20
// SELECT_19EC438 CLK 40 40

67 | P a g e
Layout design of 2:1 MUX in Microwind:

Waveform of 2:1 MUX:

CONCLUSION:
Hence, we construct the 2:1 Mux in DSCH Software and also verify its truth table, and by the help of the
Verilog code that is made in DSCH is directly used in the Microwind 3.1 and verifies the output waveform
with the truth table.

68 | P a g e
 PRACTICAL 12
AIM: To study and implement Half-Adder CMOS layout using DSCH and Verilog.
APPARATUS: Microwind 3.1 Software and DSCH Software
THEORY:
The Half-Adder is a basic building block of adding two numbers as two inputs and produce out two outputs.
The adder is used to perform OR operation of two single bit binary numbers. The augent and addent bits are
two input states, and 'carry' and 'sum 'are two output states of the half adder.It gives us the following
Boolean expression of:
SUM = (A B) = A.B’ + A’. B
CARRY = A.B

Logic Circuit of Half Adder in DSCH:

69 | P a g e
Verilog Code:

module HFADDER( A_19EC438,B_19EC438,SUM_19EC438,CARRY_19EC438);

input A_19EC438,B_19EC438;
output SUM_19EC438,CARRY_19EC438;
wire ;
xor #(16) xor2_1(SUM_19EC438,A_19EC438,B_19EC438);
and #(16) and2_2(CARRY_19EC438,B_19EC438,A_19EC438);
endmodule
// Simulation parameters in Verilog Format
always
#1000 A_19EC438=~A_19EC438;
#2000 B_19EC438=~B_19EC438;
// Simulation parameters
// A_19EC438 CLK 10 10
// B_19EC438 CLK 20 20
Layout design of Half Adder in Microwind:

70 | P a g e
Wave Form of Half Adder in Microwind:

CONCLUSION:
Hence, we have generated a circuit which follows the truth table of Half Adder.

71 | P a g e
 PRACTICAL 13
AIM: To study and implement CMOS Ring Oscillator CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates between two
voltage levels, representing true and false. A schematic diagram of a simple three inverter ring oscillator is
shown in Fig.1.

Fig.1: A 3-inverter ring oscillator.

The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first.
Because a single inverter computes the logical NOT of its input, it can be shown that the last output of a
chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a finite
amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation.
A real ring oscillator only requires power to operate; above a certain threshold voltage, oscillations begin
spontaneously. To increase the frequency of oscillation, two methods may be used. Firstly, the applied
voltage may be increased; this increases both the frequency of the oscillation and the power consumed,
which is dissipated as heat.
PROCEDURE:
 Open DSCH software and implement the circuit using gates present on the pallet.
 Stimulate the circuit and verify the truth table of Ring Oscillator.
 Save file with .v extension.
 Go to Files=>Make Verilog file, to make Verilog file of the Ring Oscillator circuit in DSCH
software.
 Open Microwind 3.1 software click on Compile=>Compile Verilog File.
 Select the file with .v extension.
 A Verilog code will be generated, compile the code.
 If no error is shown then click on Back to editor.
 CMOS layout of Ring Oscillator will be generated.
 Click on RUN and the output waveforms will be generated.

72 | P a g e
Architecture of Ring Oscillator in DSCH:

Verilog Code:
module RINGOSCII_19EC438( out1_19EC438,out2_19EC438,out3_19EC438);
output out1_19EC438,out2_19EC438,out3_19EC438;
wire ;
not #(17) inv_1(out1_19EC438,out3_19EC438);
not #(17) inv_2(out2_19EC438,out1_19EC438);
not #(17) inv_3(out3_19EC438,out2_19EC438);
endmodule
Layout design of Ring Oscillator in Microwind:

73 | P a g e
Waveform:

CONCLUSION:
Hence, we successfully studied and implemented implement CMOS Ring Oscillator CMOS layout using
DSCH and Verilog and observed its output in Microwind3.1 We saw the astable behaviour when odd
numbers of inverters are connected into a cascade circuit.

74 | P a g e
 PRACTICAL 14
AIM: To study and implement Full-Adder CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds
three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in
from the previous less-significant stage.[2] The full adder is usually a component in a cascade of adders,
which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output. Output carry and sum
typically represented by the signals Cout and S, where the sum equals 2Cout + S.
A full adder can be implemented in many different ways such as with a custom transistor-level circuit or
composed of other gates. One example implementation is with S = A ⊕ B ⊕ Cin and Cout = (A ⋅ B) +
(Cin ⋅ (A ⊕ B)).

TRUTH TABLE:

PROCEDURE:
 Open DSCH software and implement the circuit using gates present on the pallet.
 Stimulate the circuit and verify the truth table of Full Adder.
 Save the file with .v extension.
 Go to Files=>Make Verilog file, to make Verilog file of the Full Adder circuit in DSCH software.
 Open Microwind 3.1 software click on Compile=>Compile Verilog File.
75 | P a g e
  Select the file with .v extension.
 A Verilog code will be generated, compile the code.
 If no error is shown then click on Back to editor.
 CMOS layout of Full Adder will be generated.
 Click on RUN and the output waveforms will be generated.

Logic Circuit of Full Adder in DSCH:

Verilog Code:
module FULLADD_19EC438(
A_19EC438,B_19EC438,CARRY_19EC438,SUM_19EC438,CARRY_19EC438);
input A_19EC438,B_19EC438,CARRY_19EC438;
output SUM_19EC438,CARRY_19EC438;
wire w4,w7,w8,;
xor #(23) xor2_1(w4,A_19EC438,B_19EC438);
xor #(16) xor2_2(SUM_19EC438,w4,CARRY_19EC438);
and #(16) and2_3(w7,w4,CARRY_19EC438);
and #(16) and2_4(w8,B_19EC438,A_19EC438);
or #(16) or2_5(CARRY_19EC438,w7,w8);
endmodule
// Simulation parameters in Verilog Format
always
#1000 A_19EC438=~A_19EC438;
#2000 B_19EC438=~B_19EC438;
#4000 CARRY_19EC438=~CARRY_19EC438;

// Simulation parameters
// A_19EC438 CLK 10 10
// B_19EC438 CLK 20 20
// CARRY_19EC438 CLK 40 40

76 | P a g e
Layout design of Full Adder in Microwind:

Waveform of Full Adder:

CONCLUSION:
Hence, we have generated a circuit which follows the truth table of Full Adder.

77 | P a g e
 PRACTICAL 15
AIM: To study and implement 2-bit Comparator CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
A 2-bit comparator compares two binary numbers, each of two bits and produces their relation such as one
number is equal or greater than or less than the other. The figure below shows the block diagram of a two-
bit comparator which has four inputs and three outputs.
The first number A is designated as A = A1A0 and the second number is designated as B = B1B0. This
comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B) and L (L= 1 if A<B).

Truth Table:

78 | P a g e
The k-map simplification for the above truth table is as follows.

From the above k-map simplification, each output can be expressed as:

By using above obtained Boolean equation for each output, the logic diagram can be implemented by using
four NOT gates, seven AND gates, two OR gates and two Ex-NOR gates.
The figure below shows the logic diagram of a 2-bit comparator using basic logic gates. It is also possible to
construct this comparator by cascading of two 1-bit comparators.

PROCEDURE:
 Make a logic diagram as shown above in DSCH software.
 Save the file.
 Go to FILE > “Make Verilog File” and generate the Verilog file.

79 | P a g e
  Open Microwind Software.
 Go to COMPILE > “Compile Verilog File” and select the same Verilog file generated using DSCH
and generate CMOS layout.
 Now RUN it to generate the corresponding waveform.

Logic Circuit of 2-bit Comparator in DSCH:

Verilog Code:
module 2BitComparator_19EC438(
A1_19ec438,B0_19ec438,B1_19ec438,A0_19ec438,AeB_19EC438,AsB_19EC438,AiB_19EC438);
input A1_19ec438,B0_19ec438,B1_19ec438,A0_19ec438;
output AeB_19EC438,AsB_19EC438,AiB_19EC438;
wire w3,w6,w8,w9,w10,w11,w13,w14;
wire w15,w16,w18,w19,;
not #(1) inv_1(w3,A0_19ec438);
not #(1) inv_2(w6,B1_19ec438);
not #(1) inv_3(w8,B0_19ec438);
not #(1) inv_4(w9,A1_19ec438);
xnor #(1) xnor2_5(w10,B1_19ec438,A1_19ec438);
xnor #(1) xnor2_6(w11,B0_19ec438,A0_19ec438);
and #(1) and2_7(AeB_19EC438,w11,w10);
and #(1) and3_8(w13,A0_19ec438,w6,w8);
and #(1) and3_9(w14,A1_19ec438,A0_19ec438,w8);
and #(1) and2_10(w15,w6,A1_19ec438);
and #(1) and2_11(w16,B1_19ec438,w9);
or #(1) or3_12(AsB_19EC438,w13,w14,w15);
and #(1) and3_13(w18,w3,B1_19ec438,B0_19ec438);
and #(1) and3_14(w19,w9,w3,B0_19ec438);
or #(1) or3_15(AiB_19EC438,w18,w19,w16);
endmodule

80 | P a g e
// Simulation parameters in Verilog Format
always
#10 A1_19ec438=~A1_19ec438;
#20 B0_19ec438=~B0_19ec438;
#40 B1_19ec438=~B1_19ec438;
#80 A0_19ec438=~A0_19ec438;

// Simulation parameters
// A1_19ec438 CLK 10 10
// B0_19ec438 CLK 20 20
// B1_19ec438 CLK 40 40
// A0_19ec438 CLK 80 80

Layout design of 2-bit Comparator in Microwind:

81 | P a g e
Waveform of 2-bit Comparator:

CONCLUSION:
Hence, we studied about the working of 2-bit Comparator using DSCH and Microwind 3.1 software.

82 | P a g e
 PRACTICAL 16
AIM: To study and implement edge triggered D-flip flop CMOS layout using DSCH and Verilog.
APPARATUS: DSCH Software and Microwind 3.1 Software
THEORY:
D Flip-flops are used as a part of memory storage elements and data processors as well. D flip-flop can be
built using NAND gate or with NOR gate. Due to its versatility they are available as IC packages. The major
applications of D flip-flop are to introduce delay in timing circuit, as a buffer, sampling data at specific
intervals. D flip-flop is simpler in terms of wiring connection compared to JK flip-flop. Here we are
using NAND gates for demonstrating the D flip flop.
Whenever the clock signal is LOW, the input is never going to affect the output state. The clock has to be
high for the inputs to get active. Thus, D flip-flop is a controlled Bi-stable latch where the clock signal is the
control signal. Again, this gets divided into positive edge triggered D flip flop and negative edge triggered D
flip-flop. Thus, the output has two stable states based on the inputs which have been discussed below.
The circuit for edge triggered flipflop is as follows,

Truth Table to edge triggered D-flip flop:

PROCEDURE:
 Open DSCH software and implement the circuit using gates present on the pallet.
83 | P a g e
  Stimulate the circuit and verify the truth table of D Flip-Flop.
 Go to Files=>Make Verilog file, to make Verilog file of the D Flip-Flop circuit in DSCH software.
 Another file with same name but with .v extension will be saved.
 Open Microwind 3.1 software click on Compile=>Compile Verilog File.
 Select the file with .v extension.
 A Verilog code will be generated, compile the code.
 If no error is shown then click on Back to editor.
 CMOS layout of D Flip-Flop will be generated.
 Click on RUN and the output waveforms will be generated.
Logic Circuit of D Flip Flop in DSCH:

Verilog Code:
module DFLIPFLOPNEW_19EC438(
INP_19EC438,CLOCK_19EC438,OUT_19EC438,OUT2_19EC438);
input INP_19EC438,CLOCK_19EC438;
output OUT_19EC438,OUT2_19EC438;
wire w2,w3,w4,w6,;
nand #(13) nand2_1(w4,w2,w3);
nand #(27) nand2_2(w2,CLOCK_19EC438,w4);
nand #(20) nand3_3(w6,w2,CLOCK_19EC438,w3);
nand #(20) nand2_4(w3,INP_19EC438,w6);
nand #(20) nand2_5(OUT_19EC438,OUT2_19EC438,w2);
nand #(20) nand2_6(OUT2_19EC438,w6,OUT_19EC438);
endmodule
84 | P a g e
// Simulation parameters in Verilog Format
always
#1000 INP_19EC438=~INP_19EC438;
#1000 CLOCK_19EC438=~CLOCK_19EC438;
// Simulation parameters
// INP_19EC438 CLK 10 10
// CLOCK_19EC438 CLK 10.000 10.000
Layout design of D Flip Flop in Microwind:

Waveform:

CONCLUSION:
Hence, we studied about the working of D flip flop using DSCH and Microwind 3.1 software.

85 | P a g e
86 | P a g e