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KITHUATDIENTU
KITHUATDIENTU
KITHUATDIENTU
KHOA CƠ KHÍ
BỘ MÔN CƠ ĐIỆN TỬ
KỸ THUẬT ĐIỆN TỬ
(Cho sinh viên ngành Cơ điện tử)
Firma convenzione
Năm học: 2023 - 2024
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
MercoledìTS. Đặng Phước
27 maggio 2015 Vinh
Email: dpvinh@dut.udn.vn
2
Content – 30 hours
Chapter 1: Introduction
5. Internet
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
4
Evaluation
3 elements: Process + Mid-term + Final exam
Weight:
Process: Diligence 15% + Exercises 15%
• 01 absence -2 of diligence
• 05 absences No final exam
Mid-term exam: 20%
Final exam: 50%
Exam: written exam, materials are not allowed (60 min)
“Liêm chính học thuật”
Introduction
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Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
Mercoledì 27 maggio 2015
16
Content
1. History
2. Popular electronic devices
Passive devices
Active devices
Opto-Electronic devices
3. Voltage, current and fundamental laws
Voltage and Current
Voltage source and Current source
Ohm law
Kirchoff voltage law (KVL)
Kirchoff current law (KCL)
Devices
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
Mercoledì 27 maggio 2015
34
Classification
1. Passive device
2. Active device
3. Opto-Electronic devices
Resistor
Capacitor
Inductor
Relay
…
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
37
Resistor
Resistor: is a passive two-terminal electrical
component that implements electrical resistance as a
circuit element
Resistivity is a fundamental property of a material that
measures how strongly it resists electric current.
= 2. .f.L
Iron core
Ferrite core
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
75
Exercises
1. Characteristics, functions and applications of
4 kinds of inductors?
Where N is the
number of turns
in winding
2000 W 2000 W
A B C D E F G Dp
A B C D E F G Dp
Gustav Kirchhoff
(1824 – 1887)
n>p
p>n
Unbiased
Reverse Biased
Forward Biased
I =I −1
where
• q: absolute value of electron charge (q = 1,6.10 C)
• k: Boltzmann's constant (k = 1,38.10-23 J/K)
• T: Kelvin temperature (K).
• U: applied voltage across the terminals of the diode
• I : "dark saturation current", the diode leakage current
density in the absence of light.
Equation of
Set UT = kT/q is the thermal voltage Diode characteristic
At 300 K: UT ~ 25.5 mV.
/
= −1
Dark saturation current :
= . /°
= ( ) ( ) ° = − ;
Reverse biased
U remains
constant when
I change
Working range
Dr. Dang Phuoc Vinh of ZenerFaculty
diodeof Mechanical Engineering
Avalanche breakdown? 163
Function?
V0 ?
V0 = 0, vs < VD0
V0 = (vs-VD0)R/(R+rD)
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
181
Half Wave Rectifier
V0 ?
D1
D2
D4
D3
V0 ?
D1
D2
D4
D3
= + .
Voltage regulator IC
Input voltage: U ≤ 35 V
U >U +3
Input voltage : U ≤ 35 V
U >U +2÷3 Out
In
Ground
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
209
Positive voltage – 78XX
Input voltage:
U ≤ 35 V
U >U +2÷3
Input voltage : U ≤ 35 V
U > U +3
IE IC IE IC
- UCE + + UEC -
E C E C
- - + +
VBE IB VBC VEB IB VCB
+ + - -
B B
IE = IB + IC IE = IB + IC
UCE = -VBC + VBE UEC = VEB - VCB
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
249
Specifications
• IE = IB + IC
• Ratio of the collector current to the = IC = IE
emitter current
• Current gain:
IC = IB
= ( 100 with low-power BJT)
IE IC
= IC / (IE – IC) = / (1- ) E
- UCE +
C
= / ( + 1) - -
IB = (1 - )IE VBE IB VBC
+ +
IE = (1 + )IB B
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
250
Specifications
50 A
β? β = IC / IB = 1 mA / 0.05 mA = 20
= IC / IE = 1 mA / 1.05 mA = 0.95238
?
= β / (β + 1) = 20/21 = 0.95238
The load line shows all corresponding levels of IC and VCE that
can exist in a particular circuit.
IB
µA Q V UCE RC
RB
VB VCC
=
B-E is forward biased
B-C is reverse biased (Vc > Vb > Ve)
DC Load line =
Active (Linear) region
=
Q-Point
= Cut-off region
BJT “fully OFF”
=
=
( )
VB = 3 V ; RB = 10 kΩ
VC = 5 V ; RC = 1 kΩ
VBE = 1 V ; VCE Sat = 0.1 V
β(hFE) = 100
• Determine IB ; IC ; VCE
• Power consumption? E
= − = 5 − 20 mA × 1kΩ = −15 V
Wrong Assumption
− 3−1
= = = 0.2 mA
10 kΩ
RB = 10 kΩ − ( ) 5 − 0.1
( ) = = = 4.9 mA
1 kΩ
( ) 4.9
Re-check: = = = 0.049 mA
E ( )
100
> ( ) Suitable Assumption
VB = 3 V ; RB = 100 kΩ
VC = 5 V ; RC = 1 kΩ
VBE = 1 V ; VCE Sat = 0.1 V
β(hFE) = 100
• Determine IB ; IC ; VCE
• Power consumption? E
( )
( ) =
IB < ( ): Active
circuit)
ICQ
• Straight line. Q(UCEQ, ICQ)
• UCE = 0 I =
IB = 0
L
• IC = 0 UCE = VCC UCE(V)
UCEQ VCC
Q point
VB = 5 V ; RB = 107.5 kΩ.
VC = 10 V ; RC = 1 kΩ.
Vγ = 0.6 V ; β = 100.
• Calculate IB ; IC ; UCE
• Determine Q point?
E
UCE (V)
5.9 10
– Q Point
• Q locates in the middle of the DC load line BJT works stable.
−
=
+ (1 + )
Q point
• =
IB decreases IC decreases
• A’ A
• Circuit has thermal stability
Một mạch tuyến tính hay phức tạp có thể thay thế dòng và điện áp nguồn
bằng một mạch tương đương có chứa một điện áp độc lập VTH và một điện
trở nối tiếp RTH.
VTH = 8 V
RTH = 766.67 Ω
−
=
+ 1+
=
1+
We can have:
= + +
where α =
Q point
E C
C
B ra
vào B ra
vào E
Rn rBE=rp iB it
RC Rt
ur
O
uv
RB
en
rv iE Rr
Rv
RB = R1//R2 E
v E re O C
Rn t
RE RC Rt
en
rv Rr
Rv
B
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
313
C-C Type Circuit
• RB1, RB2: for the BJT biasing. VCC
• RC: resistor of C terminal.
RB1 RC
• RE: resistor of E terminal.
• Rt: resistor of load.
Q
• en, Rn: value and inside C1
Rn
resistor of supply power. RB2 RE
C2
Rt
• C1, C2: input and output en
capacitor blocking DC and
allowing AC signal.
ur
RB = R1//R2
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
Applications
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Application: Amplifier
= + +
Applications
Mercoledì 27 maggio 2015
334
Content
What is an OPAMP?
Applications:
1. Comparator
2. Inverting & Non- Inverting Amplifier
3. Voltage Follower
4. Inverting & Non- Inverting summing Amplifier
5. Differential Amplifier
6. Differentiator Amplifier
7. Integrator Amplifier
8. Instrumentation Amplifier
i-
Inverting input
G : Gain of OPAMP.
i(+), i(-) : input Idea OPAMP: G = ∞
current of OP-AMP at
: output resistance
inverting and non-
inverting input -15V Idea OPAMP: R = 0.
−
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
347
Inverting amplifier
=0
=0
Virtual
Earth
=∞
=0
=
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
350
Inverting Summing Amplifier
Fundamental of
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Digital Electronics
del Duomo di Milano
Aula Magna – Rettorato
Mercoledì 27 maggio 2015
357
Content
1. Basic of Digital Electronic
2. Algebraic Logic
BCD 8421
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
375
Binary to Hexadecimal
1101 0101 1100 1111 D5CF
0b1101 0101 1100 1111
0xD5CF
A B C D E F G Dp
F G B
A B C D E F G Dp
E C
1 0 0 1 1 0 0
D
0b.0001.1001
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
378
7 segment LED
Logic Sum
0+0=0 0+1=1 1+0=1 1+1=1
x+0=x x+1=1 x+x=x x+x=1
Logic Product
0.0 = 0 0.1 = 0 1.0 = 0 1.1 = 1
x.0 = 0 x.1 = x x.x = x x.x = 0
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
382
Laws of Boolean
Commutative (hoán vị) Absorptive (hấp thu)
x+y=y+x x + x.y = x
x.y = y.x x.(x+y) = x
A B Output
A.B = Y 0 0 0
0 1 0
Ex: Burglar alarm = AND (alarm
switch ; door). 1 0 0
1 1 1
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
A B Output
A+B=Y 0 0 0
OR gates can also have more 0 1 1
than two inputs
1 0 1
1 1 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
394
NOT gate
Just one input and one output
Giving an output which is the inversion of the input
inverse gate
Giving a “1” output when input is “0” and vice versa.
A =Y
A bar over a symbol indicate the inverse of output.
Input Output
1 0
0 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
396
NAND gate
Can be considered as a combination of an AND gate
followed by a NOT gate
Output is “0” only when input A and B are “1”
Symbol: the AND symbol followed by a circle
A B Output
0 0 1
A. B = Y 0 1 1
1 0 1
1 1 0
A B Output
0 0 1
A+ B = Y
0 1 0
1 0 0
1 1 0
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
400
XOR gate
XOR stands for exclusive OR
Output will be “1” when the inputs are different
XOR operation is represented by the symbol
A B Output
0 0
Y=A⊕B= + 0 1
1 0
1 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
402
XNOR gate
XNOR stands for exclusive NOR
It is an XOR gate with its output inverted.
XNOR operation is represented by the symbol (.)
A B Output
0 0
Y = A (·) B = + .( + ) 0 1
1 0
1 1
A B
B
B+
B A B Output
0 0
0 1
1 0
1 1
x.y.z
x.y.z
x.y.z
F
x.y.z
x.y.z
x.y.z
xy
00 01 11 10
zt
00
4-variable Karnaugh-map 01
11
10
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
414
Truth Table Expression
A B C S
0 0 0 0
0 0 1 0
0 1 0 1
S= + + + ABC
0 1 1 0
1 0 0 1
1 0 1 1
Non-inverting variation 1
1 1 0 0
Inverting variation 0 1 1 1 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
415
Karnaugh - map
Value of variations are expressed in blocks.
Consecutive blocks have only one different variation.
Example: S = ABC + + +
A B C S
AB B AB A 0 0 0 0
C 00 01 11 10 0 0 1 0
0 1 0 1 0 1 0 1
0
0 1 1 0
1 0 0 1 1
1 0 0 1
1 0 1 1
Not Consecutive Consecutive
1 1 0 0
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
1 1 1 1
416
Rules
1. Groups may not include any cell containing a zero
= + + +
A
xy
00 01 11 10
zt A z.t B x. y.t
00 1 1 1 1 C x.z.t D x. y.t
01 1 F A B C D
11 1 1 z.t x. y.t x.z.t x. y.t
10 1
Dr. Dang Phuoc Vinh DMechanical Engineering
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B C
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Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
Mercoledì 27 maggio 2015