A 1.

2 ps-Jitter Fully-Synthesizable Fully-Calibrated

Fractional-N Injection-Locked PLL Using True
Arbitrary Nonlinearity Calibration Technique
Bangan Liu∗ , Huy Cu Ngo∗ , Kengo Nakata∗ , Wei Deng∗ , Yuncheng Zhang∗ , Junjun Qiu∗ ,
Toru Yoshioka∗ , Jun Emmei∗ , Haosheng Zhang∗ , Jian Pang∗ , Aravind Tharayil Narayanan∗ ,
Dongsheng Yang∗ , Hanli Liu∗ , Kenichi Okada∗ , and Akira Matsuzawa∗
∗ Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
2-12-1-S3-27, Ookayama, Meguro-ku, Tokyo, 152-8552, Japan

Abstract — This paper presents a fully-synthesizable Duty Cycle Error

Gain Error
+ INL
Gain Error

Delay

Delay
fractional-N injection-locked PLL in 65 nm CMOS. A true REF 2xREF
arbitrary non-linearity calibration scheme is specifically pro- Coarse
Code
Fine
Code
Inj. Edge &
Window Gen

posed for synthesizable DTC, together with an extensive VINJ VWIN

VOUT
Synthesizable timing generation blocks
digital calibration of the PLL. The RMS jitter of 1.2 ps 2xREF VOSC
Sym. MUX

REF 6-bit 8-bit

and 0.3 ps is achieved at 1 GHz output for fractional-N and REF Doubler Coarse DTC Fine DTC
Sym. PD
DCO
integer-N operation, respectively. The power consumption is
[6:0] [13:8] [7:0]
2.5 mW and 2.2 mW, corresponding to an FoM of -234.4 dB REF Doubler PD[1:0]
Fine

Fine Coarse
and -246.7 dB. PD Coarse
Tuning Gain Cal. & Medium

Index Terms — fully-synthesizable, digital PLL, PD

REF Doubler [7:0]
[4:0] [7:0]
DCE Cal.
injection-locked PLL, DTC calibration DTC: Digital-to-Time Converter
Coarse DLF
FLL
DTC
DCE: Duty Cycle Error TANC [7:0]
TANC: True Arbitrary
[13:8] [7:0] [9:0]
Nonlinearity Calibration
I. I NTRODUCTION FCWFRAC Σ
Coarse
DTCCTRL PD PD FCWINT
[13:0] Gain Cal. [13:0]
Calibration logic blocks
The synthesizable PLL is promising for reducing de- Error Source REF Doubler Coarse DTC Fine DTC DCO
sign/test cost and for improving process portability and Error Range
Error Type
Narrow (10ps)
Duty Cycle Error
Wide (1000ps)
Gain Error INL*
Narrow (10ps)
Gain Error
Narrow (10ps)
Freq. Error
scalability [1]–[3], which can be implemented through Cal. Executor Fine DTC Coarse DTC Fine DTC* Fine DTC DCO
*
Proposed in this paper
the standard digital design flow. The integer-N injection-
locked PLL (IL-PLL) in [1] realizes an excellent figure of Fig. 1. Block diagram of the proposed fully-synthesizable fully-
merit (FoM) performance comparable to custom-designed calibrated fractional-N injection-locked-PLL.
ones owing to the injection-locked architecture. The last
remaining issue in the synthesizable design is realization operation, which degrades fractional spur and causes a
of synthesizable fractional-N PLL. poor jitter performance. Notice that reference doubler and
Fig.1 shows the block diagram of the proposed fully- DCO need only narrow-range calibration. For example, a
synthesizable fractional-N IL-PLL, which consists of tim- 1ps-jitter DCO has to cover at least 10 ps linear tuning
ing generation blocks and calibration logic blocks. All the range while coarse tuning of DCO can be non-linear. On
circuit blocks are synthesizable and can be implemented the other hand, the DTC has to cover a full range of DCO
by commercial digital design tools with standard-cell li- period, and a very wide linear tuning range is required,
brary. The timing generation blocks consist of reference e.g. 1000 ps linear range in case of 1GHz oscillator.
doubler, DTC, and digitally-controlled oscillator (DCO) This stringent requirement has never been satisfied by
with symmetric multiplexer (MUX) and symmetric phase the conventional synthesizable design. And conventional
detector (PD). Due to the automatic place and route, DTC calibration scheme in [4] is not applicable due to
these timing generation blocks severely suffer from layout synthesizable DTC’s large differential non-linearity(DNL).
randomness as well as the PVT variation, so an overall In this work, a comprehensive and robust digital calibration
calibration is required for compensating the impairments. is utilized to remove all the above mentioned impairments.
The reference doubler needs a duty cycle error (DCE)
correction, and DCO needs a frequency error correction. II. T RUE A RBITRARY N ONLINEARITY C ALIBRATION
FOR SYNTHESIZED DTC
DTC is a key component for fractional-N operation, and
both gain error and non-linearity calibration are required. Fig.2 (a) shows the implementation of synthesizable
The non-linearity characteristic is important for fractional DTC and the proposed offset calibration. The proposed

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works for DTC with arbitrary INL profile. First, the INL
E of each coarse code is estimated from the PD output, then
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TANC for the coarse DTC calibration. The fractional part
Fig. 2. Conceptual operation of proposed True Arbitrary Non- of input FCW is first accumulated, and the coarse gain
linearity Calibration (TANC) for fully synthesizable DTC. is calibrated using an LMS algorithm depending the PD
output. The 6-bit MSB is used for controlling the 6-bit
synthesizable DTC is segmented into 6-bit coarse stage coarse DTC. The same code is also used for controlling the
and 8-bit fine stage for optimizing the trade-off between TANC block, which has 63 registers in case of 6-bit coarse
dynamic range and linearity. The fine stage is implemented DTC. Each calibration register corresponds to one specific
by a single-stage inverter loaded by variable capacitance coarse DTC code, and the delay offset of the coarse DTC
made of 3-input NAND gates with 0.24ps/LSB resolution, is compensated by the fine DTC delay after another LMS
which are connected to the same single node. Since calibration for the fine gain. The DTC nonlinearities are
the variable capacitance has lower sensitivity to layout observed by the symmetric PD, and the detected sign bit is
randomness, the fine DTC can maintain a good linearity also used for all the DTC calibrations. The offset τof f set,k
while the range is narrow. The coarse stage is implemented is stored in the register file, which is continuously updated
as a variable-length delay line, and each MUX stage in the background as well as the fine and coarse gain.
consists of a tri-state buffer with 28.6 ps/LSB resolution.
Unfortunately, the coarse stage is more sensitive the layout III. DCO AND R EFERENCE D OUBLER C ALIBRATION
randomness. Due to large local DNL jumps, the integral The coarse calibration of DCO is done by FLL, and
non-linearity(INL) profile of synthesizable DTC is very the fine calibration, i.e. phase lock, is controlled by a
different from conventional custom designed ones, as show digital loop filter (DLF) based on PD outputs for a target
in Fig.2 (b). frequency control word (FCW). Fig.4 shows the DCO
The conventional INL calibration using a piece-wise phase calibration and injection-lock operation using the
linear interpolation(PWLI) [4], [5], which estimates the symmetric PD and MUX. In the conventional IL-PLLs,
DTC INL based on the interpolation points. But the PWLI replica element [3], [6] and gated injection [7] techniques
can only works for custom designed DTC which has are utilized for DCO calibration. However, the replica-
small and regular INL, and for synthesizable DTC the based calibration suffers from the mismatch between the

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symmetric multiplexer for DCO calibration.
Fig. 5. Concept of proposed reference double calibration, the
DCO and replica elements, and the gated injection tech- duty cycle error (DCE) in the reference doubler is compensated
nique reduces the injection efficiency and degrades the by the fine DTC.
jitter performance. Thus, the DCO calibration used in this
paper extracts the frequency error by performing phase
comparison and edge replacement simultaneously. The os-
cillator edge is compared against the injection edge in the
symmetric PD, and replaced by the same injection edge in —P
the symmetric MUX at the same time. Thanks to the latch-

—P
based implementation, the proposed symmetric PD has a
larger gain than the conventional flip-flop implementation, )XOO\V\Q
63,

which gives larger loop gain and helps to minimize the
frequency error.
The reference doubler calibration is shown in Fig.5.
After the duty cycle error is roughly calibrated, the residue
error is precisely calibrated by the fine DTC. In the
integer-N mode, the fine DTC will introduce two different
delays τrise and τf all to rising edge and falling edge
respectively to eliminate the residue. In the fractional-N
mode, τrise and τf all will added with the desired delay
n ∗ Δτ thus residue DCE will not degrade the jitter and
spur performance.
IV. M EASUREMENT R ESULTS
The entire PLL is synthesized using commercial digital
design tools with a non-modified standard cell library. The
core area of the PLL is 0.12 mm2 , which is fabricated
in a 65 nm CMOS process. Fig.6 shows a die photo.
The phase noise is measured by a signal source analyzer
(Keysight E5052B), and the spectrum is measured by a
spectrum analyzer (Keysight E4407B). Fig.7 shows the
measured phase noise with a 100 MHz reference clock.
The PLL achieves 0.3 ps jitter at 1 GHz output in integer-N
mode, and 1.2 ps jitter at 971.24 MHz output in fractional-
N mode, which is integrated from 10 kHz to 10 MHz. The
)UDF13//
Fig. 6. Die micro-graph of fully synthesizable fractional-N IL-
PLL.
power consumption is 2.2 mW and 2.5 mW for integer-
N and fractional-N modes, respectively. The measured
fractional spur is -58.5 dBc at 1.0725 MHz offset.
Table.I summarizes the measured performance and com-
pares them with the state-of-the-art DTC-based fractional-
N digital PLLs. The proposed PLL achieves an FoM of
-246.7 dB in integer-N mode, which is 5 dB better than
the state-of-the-art [1]. The PLL also achieves an FoM of
-234.4 dB in fractional-N mode, which is also 10 dB better
than [3]. The measured worst fractional spur is -58.5 dBc
after the proposed TANC calibration. This represents the
best results among the fully-synthesizable PLLs, and the
results are comparable to that of custom-designed digital
PLLs.

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 TABLE I
P ERFORMANCE SUMMARY AND COMPARISON WITH STATE - OF - THE - ART
FRACTIONAL -N DIGITAL PLL S .

[4] [8] [3] This Work

Custom design Fully synthesizable
DTC+BBPD DTC+TDC Soft-injection DTC
Architecture
DPLL DPLL IL-PLL +IL-PLL
Oscillator type LC Ring Ring Ring
Freq.[GHz] 3∼4 4.5∼5.2 0.8∼1.7 0.6∼1.7
Ref.[MHz] 40 50 380 100
Integ. Jitter[ps] 0.7 0.5 3.6 0.3* 1.2
4.2 3.7 3.0 2.2 2.5
Pdc[mW]
@3.6GHz @4.5GHz 1.5GHz @1.0GHz @0.97GHz
FoM[dB] -237.0 -240.5 -224.6 -246.7 -234.4
CMOS Tech. 65nm 65nm 65nm 65nm
Area[mm2 ] 0.2 0.22 0.05 0.12
Frac.Spur[dBc] -51.7 -51.5 -45 -58.5
DTC Cal. Gain+INL(PWLI) Gain NA Gain+INL(TANC)
* Integer-N mode

0
ACKNOWLEDGMENT
Output Power [dBm]

-20 This paper is based on results obtained from a project

-40
58.5dBc commissioned by the New Energy and Industrial Technol-
-60
ogy Development Organization (NEDO).
-80
-100 R EFERENCES
-120
969.74M 971.24M 972.74M [1] H. C. Ngo, et al., “A 0.42ps-Jitter -241.7dB-FOM Synthe-
Frequency [Hz] sizable Injection-Locked PLL with Noise-Isolation LDO,” in
-40
IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 150–151.
-60 [2] W. Deng, et al., “A Fully Synthesizable All-Digital PLL with
Phase Noise [dBc/Hz]

-80
Interpolative Phase Coupled Oscillator, Current-Output DAC,
and Fine-Resolution Digital Varactor Using Gated Edge
-100 Injection Technique,” IEEE J. Solid-State Circuits, vol. 50,
-120 pp. 68–80, Jan. 2015.
[3] ——, “A 0.048 mm2 3mW Synthesizable Fractional-N PLL
-140
Int-N mode Frac-N mode DCO free-run with a Soft Injection-Locking Technique,” in IEEE ISSCC
-160 Dig. Tech. Papers, Feb. 2015, pp. 252–253.
10k 100k 1M 10M
Offset Frequency [Hz]
[4] S. Levantino, et al., “An Adaptive Pre-Distortion Technique
to Mitigate the DTC Nonlinearity in Digital PLLs,” IEEE J.
Solid-State Circuits, vol. 49, pp. 1762–1772, Aug. 2014.
Fig. 7. Measured DCO and PLL phase noise and spectrum.
[5] N. Markulic, et al., “A Self-Calibrated 10Mb/s Phase Mod-
ulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -
V. C ONCLUSION 246.6dB-FOM, Fractional-N Sub-sampling PLL,” in IEEE
ISSCC Dig. Tech. Papers, Feb. 2016, pp. 176–177.
[6] S. Choi, et al., “A PVT-Robust and Low-Jitter Ring-VCO-
Based Injection-Locked Clock Multiplier with a Continuous
A fully-synthesizable fully-calibrated fractional-N IL- Frequency-Tracking Loop Using a Replica-Delay Cell and
PLL is presented in this paper. Extensive digital calibration a Dual-Edge Phase Detector,” IEEE J. Solid-State Circuits,
of DTC, DCO and reference doubler is used to mitigate vol. 51, pp. 1878–1889, Aug. 2016.
the analog impairments caused by layout randomness. The [7] A. Elkholy, et al., “A 6.75-to-8.25GHz, 250fsrms-Integrated-
fully-synthesizable fractional-N IL-PLL achieves 1.2ps Jitter 3.25mW Rapid on/off PVT-insensitive Fractional-N
Injection-Locked Clock Multiplier in 65nm CMOS,” in IEEE
RMS jitter with 2.5mW power consumption. An FoM of ISSCC Dig. Tech. Papers, Feb. 2016, pp. 192–193.
-234.4dB is achieved, which is 10dB better than the best [8] ——, “A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Dig-
fractional-N PLL [3]. ital Fractional-N PLL Using Time Amplifier-Based TDC,”
IEEE J. Solid-State Circuits, pp. 867–881, Apr. 2015.

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