CLASS TEST S.No.

: 01SK_ECEE_A+B_190124

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DIGITAL ELECTRONICS
EC-EE
Date of Test : 19/01/2024

ANSWER KEY h

1. (b) 7. (c) 13. (c) 19. (a) 25. (d)

2. (b) 8. (b) 14. (c) 20. (c) 26. (a)

3. (a) 9. (b) 15. (b) 21. (d) 27. (a)

4. (c) 10. (d) 16. (a) 22. (d) 28. (a)

5. (b) 11. (b) 17. (b) 23. (b) 29. (b)

6. (d) 12. (d) 18. (b) 24. (c) 30. (c)

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D E TA I L E D E X P L A N AT I O N S

1. (b)
In J-K flip-flop
J K Output
1 0 Set
0 1 Reset
0 0 Hold
1 1 Racearound

2. (b)
X ⊕ Y = X
Y = XY + XY
= ( XY ) ( XY )
= (X + Y ) (X + Y )
= X +Y (∵ X + Y = 1 which is given)
3. (a)
A
1 I0 A I0
Difference = A + B
0 I1 S 0 I1 S0

A B

0 I0
Borrow = A B
I1 S0

4. (c)
The expression of Y can be written as
Y = ( A) AB + ( B) AB + ( B) AB + ( A) AB = AB + AB = B
5. (b)
Dual slope A/D convertor has the highest accuracy among the given converters.
6. (d)
7. (c)
8. (b)
9. (b)
By properly arranging the given k-map.
CD
AB 00 01 11 10
00 1 1 1 1 B

01 0 1 1 0

11 0 1 1 0
10 1 1 1 1

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 EC EE • Digital Electronics 13

∴ f = B+D
∴ Complement, f C = BD

10. (d)

11. (b)
The given circuit represents a 3-bit counter. So the count can be represented as

Clk Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1 ⇒ 5th clock pulse
6 1 1 0
7 1 1 1

∴ Y = Q 2 ⊕ Q1 ⊕ Q0
= 1⊕0⊕1= 0

12. (d)
Test for Lockout
Present State Present Input Nest State
0 1
Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Q2 Q1 Q0 2
0 0 0 1 0 1 1 0 1 1 1 0

0 0 1 1 1 1 1 0 1 1 1 0 5
3 4 6 7
0 1 0 1 0 1 1 1 1 1 0 1

1 0 1 1 1 1 0 0 0 0 1 1

Hence, the counter does not enter into lockout state.

13. (c)
Now, X > Y if
(a) X2 = 1
(b) X2 = 0 and X1X0 > Y1Y0
Y1Y0 Y1Y0
X1X0 00 01 11 10 X1X0 00 01 11 10
( X2 + X1 + X0 )
00 0 0 0 0 00 1 1 1 1

( X 2 + X 1 + Y1 )
01 1 0 0 0 01 1 1 1 1

11 1 1 0 1 11 1 1 1 1
( X 2 + Y1 + Y0 )

10 1 1 0 0 10 1 1 1 1

( X 2 + X 1 + Y0 )
X2 = 0 X2 = 1

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14. (c)
A⋅AB

A
X
B
AB

B⋅AB
Y

X = B( A + B) + A( A + B)
= AB + AB = A ⊕ B
Y = B( AB)
= B( A + B) = AB
The above circuit represents a half subtracter constructed using only NAND gates. Thus the truth
table can be written as
A B Difference (X ) Borrow (Y )
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

15. (b)

N Va N
2 TC ⋅ 2 TC
VR
t

N Va N
Total conversion time, (t) = 2 TC + ⋅ 2 TC
VR
Where, N = Number of bits of converter
T C = Time period of the clock
Va = Analog voltage
VR = reference voltage
The largest Va can be equal to VR therefore,
Va = VR
t = 2N + 1 TC
t = 212 + 1 ⋅ TC
13 1
t = 2 × sec
100 × 10 3
8192
t =
10 5
10 5
f <
8192

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 EC EE • Digital Electronics 15

f < 12.20
∴ fmax = 12 Hz

16. (a)
P = BCA + BCA + BCA + BCA
= A[BC + BC ] + A[BC + BC ]

= A[ B ⊕ C ] + A[ B ⊕ C ]
P = A ⊕ B⊕C
P(A, B, C) = Σm(1, 2, 4, 7)
Q = BC ⋅ 0 + BCA + BCA + BC
= BCA + BCA + BC( A + A)
= BCA + BCA + ABC + ABC
Q(A, B, C) = Σm(1, 2, 3, 7)

17. (b)
From the given code converter we can write
x + (1’s complement of 0011) + 1 = BCD
x + 1100 + 1 = BCD
x + 1101 = BCD
x = BCD – 1101 = BCD + (2’s complement of 1101)
∴ x = BCD + 0011 = Excess-3 code

18. (b)
By redrawing the given circuit,

A X=D+E

∴ ( )
y = ( AB + X ) ⋅ C = AB + ( D + E) ⋅ C

y = C + ( A + B)(D + E)

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 16 EC-EE

19. (a)
F = A( B + C )
A

B F

20. (c)
From the given diagram,
J1 = Q1Q2
K1 = Q2
J2 = K 2 = Q1
Also given, Q1 = 0; Q2 = 0 initially
Clk Q1 Q2 J1 K1 J2 K2
0 0 0 0 1 1 1
1 0 1 1 0 1 1
2 1 0 0 1 0 0
3 0 0 0 1 1 1
∴ It is MOD-3 counter.

21. (d)
PS NS FF inputs
QA QB QA QB JB kB
0 0 1 1 1 x

1 1 1 0 x 1

1 0 0 1 1 x

0 1 0 0 x 1

On solving for JB and kB

QB
QA 0 1
0 1 x
JB = 1
1 1 x

QB
QA 0 1
0 x 1
kB = 1
1 x 1

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 EC EE • Digital Electronics 17

22. (d)
X
100 ns
1

t
0

t
0
20 ns
y

1
⇐ y without XNOR gate delay
t
0
y

1
⇐ y after considering XNOR gate delay
t
0

23. (b)
f2 = x 0 x 1 + x 1 x 2 + x 0 x 1 x 2
= x0 x1 x 2 + x0 x1 x 2 + x0 x1 x 2 + x0 x1 x 2 + x0 x1 x 2
= Σm(1, 2, 6, 7)

24. (c)
Given, initially, PQR is 010.

D1 = R, D2 = PR , D3 = Q
R
Clk D1 D2 D3 P Q R
0 0 1 1 0 1 0
1 1 1 0 0 1 1
2 1 1 0

25. (d)

26. (a)
Input equations of flip-flops
TA = BX, TB = X, Y = AB
State equations, A(t + 1) = T′A + TA′
= (BX)′A + (BX)A′
= AB′ + AX′ + A′BX
B(t + 1) = T′B + TB′
= X′B + XB′ = X ⊕ B

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State table:
Present Input Next Output
State State
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 1 0 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 1
State diagram:
0 0

1
00/0 01/0

1 1

11/1 10/0
1

0 0

27. (a)
1st CLK 2 nd CLK 3rd CLK
000 
→ 100 → 010 → 101
The op-amp circuit is a R-2R Ladder DAC with digital input 101. Therefore,

 R f   Vref 
V0 = −  × × (Decimal equivalent of 101)
 R   2 3 

−R 5
V0 = × ×5
R 8
V0 = –3.125 V

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 EC EE • Digital Electronics 19

28. (a)

10W1Z
× 1 1 1 1
(10)(10) (1) (0) [Θ1510 = (1111)2]
0 W 1 Z
(10) 1
W 1 Z
(10) 1 0
1 0 W 1 Z
1 0 W 1 Z
10 1 0 1 1 0 0 Z =Y01011001

Y=1 Z=1
1 + W + 1 + Z = 100(W = 1)

Carry

∴ (WYZ)2 = (111)2 = 7

29. (b)
There are three data paths (flop A to flop B, flop A to flop C, flop B to flop C). Setup time is used
for deriving the maximum clock frequency.
Path A → B: tCLK > tCLK → Q + ts = 9 + 2 ⇒ tCLK > 11 ns
Path A → C: tCLK > tCLK → Q + ts + tpd = 9 + 2 + 4 ⇒ tCLK > 15 ns
tclk > 15 nsec
1 1
fmax = = = 66.67 MHz
tclk (min) 15 × 10−9

30. (c)
We know that
tsetup ≤ tclk – tpd, D – tpd, CL
for maximum setup time,
tsetup = tclk – tpd, D – tpd, CL
= 25 – 6 – max(11, 9)
= 25 – 6 – 11
= 8 ns

„„„„

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