Digital Design of IEEE 802.15.

4 PHY/MAC for a Thread Transceiver for Low-

Power Wireless Applications

Introduction:
Thread is a relatively new wireless communication protocol that offers low-power, low-data-rate transmission for various
applications as it’s based on IEEE 802.15.4 PHY and MAC standards, it has various applications including home
automation, and sensor networks. The design of Thread digital circuits involves the use of digital techniques to implement
the protocol's functional blocks, including the physical layer and media access control. In this project, we propose the
digital design of a Thread PHY and MAC layers for low-power wireless applications.

Objectives:
The main objectives of this project are:
To design the digital blocks of a Thread transceiver, including the physical layer and media access control.
To build a Verification environment using System Verilog for the designed architecture
To verify the functionality of the transceiver using FPGA platform.
To Synthesize a gate level netlist for the design
To evaluate the power consumption, timing, and area constraints of the designed transceiver.

Methodology:
A system level model built with MATLAB will be used for checking the integrity of the proposed architecture.
The proposed Thread transceiver will be designed using digital techniques, including the use of Verilog for the design of
the functional blocks. The designed blocks will be verified using system Verilog testbenches and checked against the
MATLAB model.
FPGA prototyping will be used to confirm functionality and to provide metrics about the designed architecture.
A gate level netlist will be synthesized using an ASIC gate synthesis tool.