* What is signal integrity? How it affects Timing?

Signal integrity is concerned with the quality of the propagating signal on the interconnects.
•The term signal integrity is often used to refer to a broad set of issues, like
–Crosstalk noise and the detrimental effects it can have on chip operation
–Electromigration both in signal lines and power distribution networks
–IR (voltage) drop in power lines that can cause chip operationalproblems
–Propagation delay, transition delay, and signal delay or skew due to reflections and dispersion.
–Ground bounce and power supply noise
–Manufacturing-related issues that if not addressed can lead to chip failure
* What is IR drop? How to avoid .how it affects timing?

IR Drop: IR drop is a reduction in voltage that occurs on power supply networks.

•Symptoms of IR Drop
􀂙Reduce noise margin
􀂙Increase overall delay
􀂙Cause functional failure
VDD
* What is EM and it effects

Electromigration is the problem of net disintegration in a chip due to high current density.
•"Electromigration" is the mass transport of a metal due to the momentum transfer between
conducting electrons and diffusing metal atoms

* What is floor plan and power plan?

Floorplanning is the process of:

• Positioning blocks on the die or within another block, thereby
defining routing areas between them
• Creating and developing a physical model of the design in the
form of an initial optimized layout
* What are types of routing?

Global routers
􀁻 function
􀂄 determining routing areas
􀂄 assigning net to routing areas
􀂄 minimizing global routing area, path
lengths
􀁻 congestion, approximate path length
􀂄 Detail routers
􀁻 goal
􀂄 routing actual wires
􀂄 minimizing routing area, path lengths
􀁻 general-purpose - maze, line probe
􀁻 restricted -channel, switchbox, river routers
􀂄 Specialized
􀁻 power, clock routers
* What is a grid .why we need and different types of grids?

Detail routers use both horizontal and vertical routing grids for actual
Grid-based routing imposes a routing grid (evenly spaced routing tracks
running both vertically and horizontally across the design area) that all
key for determining the appropriate place-and-route and/or physical synthesis
tool to be used.
routing. The horizontal and vertical routing grids are defined in the technology
file for all layers that are being used. The detail router can be gridbased,
gridless-based, or subgrid-based.
routing segments must follow. In addition, the router is allowed to change
direction at the intersection of vertical and horizontal tracks as indicated in

The advantage of grid-based routing is efficiency. When using a grid-based

router, one needs to make sure that the ports of all instances are on the grid.
Otherwise, they can create physical design rule errors and will be difficult to
resolve with the router.

Figure 4-10 Grid-based Routes

Gridless-based (or shape-based) routers do not follow the routing grid
explicitly, but are dependent on the entire routing area and are not limited by
grid’s restrictions. They can use different wire widths and spacing without
routing grid requirements. The most fundamental problem with this type of
router is that they are very slow and can be very complicated.

Manufacturing grid is determined by the smallest geometry that a semiconductor

foundry can process. All drawn geometries during physical design must snap to
this manufacturing grid.
Routing grids or tracks are used by physical synthesis and place-and-route tools
during detail routing. The routing tracks can be grid-based, gridless based, or
subgrid-based.
* What is core and how u will decide w/h ratio for core?

* What is effective utilization and chip utilization?

Chip utilization: a measure of the utilization for the chip as a
whole, looking at the entire chip area and including elements
such as the pad rings.

Effective utilization: a measure of utilization as viewed by the

placer— that is, examining an available cell row area relative to the
cells to be placed.
• Effective utilization, flat
• Effective utilization, hierarchical
* What is latency? Give the types?

Difference in arrival time of data from source [clock port] and end point[ clock pin at
the reg]

Source: time D/B origin and definition point

And

Network:time D/b definition point and clock pin

* What is LEF?

LEF defines the elements of an IC process technology and associated library of

cell models and contains library information for a class of designs.
It includes:
• Layer definition
• Via
• Placement
• Site type, and macro cell definitions

LEF file:cell information; pin information,area,

TECh LEF file: type of routing,pitch,witdth, direction,

* What is DEF?

Design exchange format: it give s information abt macro like functionality info, h,W of
macro, type of pin like synchronous, nonsynchoronous or don’t touch or ignore pin also
timing model,soft/ hard macro

* What are the steps involved in designing an optimal pad ring?

* What are the steps that you have done in the design flow?

* What are the issues in floor plan?

* How can you estimate area of block?

* How much aspect ratio should be kept (or have you kept) and what is the utilization?

* How to calculate core ring and stripe widths?

* What if hot spot found in some area of block? How you tackle this?

* After adding stripes also if you have hot spot what to do?

* What is threshold voltage? How it affect timing?

* What is content of lib, lef, sdc?

* What is meant my 9 track, 12 track standard cells?

* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?

* What is setup and hold? Why there are ? What if setup and hold violates?

* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum
operating frequency?

* How R and C values are affecting time?

* How ohm (R), fared (C) is related to second (T)?
* What is transition? What if transition time is more?

The propagation delay of a gate is very much dependent on the time taken for data to switch
from high to low or vice-versa
􀂊The time taken for data to switch from high-low or vice-versa known as transition time depends
mainly on
􀂄Load Capacitance
􀂄Wire length / characteristics -RC
􀂄Junction Capacitance of cell

If the allowable transition time is restricted the design performance will increase significantly
􀂊Every Gate and wire will have its own transition time
􀂊By specifying appropriate constraint we can ensure that only those components are chosen that
transit faster

* What is difference between normal buffer and clock buffer?

* What is antenna effect? How it is avoided?
* What is ESD?
Electrostatic Discharge: Electrostatic discharge is major cause for chip failure

• causes due to charged stored in machines and human contact

• Protection circuit consists of

resistor diode and its equivalent circuit

 Clamps the voltage to safe level

* What is cross talk? How can you avoid?

* How double spacing will avoid cross talk?

* What is difference between HFN synthesis and CTS?

* What is hold problem? How can you avoid it?

* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew
for the same circuit then which one you will select? Why?

* What is partial floor plan?

* What parameters (or aspects) differentiate Chip Design & Block level design??

* How do you place macros in a full chip design?

* Differentiate between a Hierarchical Design and flat design?

A flat definition considers a single level of hierarchy only,

without looking into intermediate cells.
4. A hierarchical definition considers a hierarchical design as a whole.
* Which is more complicated when u have a 48 MHz and 500 MHz clock design?

* Name few tools which you used for physical verification?

* What are the input files will you give for primetime correlation?

SDF
* What are the algorithms used while routing? Will it optimize wire length?

?
* If the routing congestion exists between two macros, then what will you do?
* How will you place the macros?
* How will you decide the die size?
* If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
* If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
* In your project what is die size, number of metal layers, technology, foundry, number of clocks?
* How many macros in your design?
* What is each macro size and no. of standard cell count?
* How did u handle the Clock in your design?
* What are the Input needs for your design?
* What is SDC constraint file contains?
* How did you do power planning?
* How to find total chip power?
* How to calculate core ring width, macro ring width and strap or trunk width?
* How to find number of power pad and IO power pads?
.* What are the problems faced related to timing?
* How did u resolve the setup and hold problem?
* If in your design 10000 and more numbers of problems come, then what you will do?
* In which layer do you prefer for clock routing and why?
* If in your design has reset pin, then it’ll affect input pin or output pin or both?
* During power analysis, if you are facing IR drop problem, then how did u avoid?
* Define antenna problem and how did u resolve these problem?
* How delays vary with different PVT conditions? Show the graph.
* Explain the flow of physical design and inputs and outputs for each step in flow.
* What is cell delay and net delay?
* What are delay models and what is the difference between them?
* What is wire load model?
* What does SDC constraints has?
* Why higher metal layers are preferred for Vdd and Vss?
* What is logic optimization and give some methods of logic optimization.
* What is the significance of negative slack?
* How the width of metal and number of straps calculated for power and ground?
* What is negative slack ? How it affects timing?
* What is track assignment?
* What is grided and gridless routing?
* What is a macro and standard cell?
* What is congestion?
* Whether congestion is related to placement or routing?
* What are clock trees?

B4 CTS : All clk pines are driven by a single clk source

After CTS: 1] A buffer tree is built to balance the loads and minimize skew

2] A delay line is added to meet the minimum insertion delay

* What are clock tree types?

H,X, tree, hybrid,Balanced

* Which layer is used for clock routing and why?

* What is cloning and buffering?

* What are placement blockages?
* How slow and fast transition at inputs effect timing for gates?
* What is antenna effect?
* What are DFM issues?
* What is .lib, LEF, DEF, .tf?
* What is the difference between synthesis and simulation?
* What is metal density, metal slotting rule?
* What is OPC, PSM?
* Why clock is not synthesized in DC?
* What are high-Vt and low-Vt cells?
* What corner cells contains?
* What is the difference between core filler cells and metal fillers?
* How to decide number of pads in chip level design?

* What is tie-high and tie-low cells and where it is used

Extra innings:
A setup timing check: verifies the timing relationship between the clock and the data pin of a
flip-flop so that the setup requirement is met. In other words, the setup check ensures that the
data is available at the input of the flip-flop before it is clocked in the flip-flop. The data should
be stable for a certain amount of time, namely the setup time of the flip-flop, before the active
edge of the clock arrives at the flip-flop.
A hold timing check ensures that a flip-flop output value that is changing does not pass through
to a capture flip-flop and overwrite its output before the flip-flop has had a chance to capture its
original value. This check is based on the hold requirement of a flip-flop. The hold specification
of a flip-flop requires that the data being latched should be held stable for a specified amount of
time after the active edge of the clock.

A removal timing check ensures that there is adequate time between an active clock edge and
the release of an asynchronous control signal. The check ensures that the active clock edge has
no effect because the asynchronous control signal remains active until removal time after the
active clock edge. In other words, the asynchronous control signal is released (becomes inactive)
well after the active clock edge so that the clock edge can have no effect.

A recovery timing check ensures that there is a minimum amount of time between
the asynchronous signal becoming inactive and the next active clock edge. In other
words, this check ensures that after the asynchronous signal becomes inactive, there
is adequate time to recover so that the next active clock edge can be effective.
A clock gating check occurs when a gating signal can control the path of a clock signal at a logic
cell. An example is shown in Figure. The pin of the logic cell connected to the clock is called the
clock pin and the pin where the gating signal is connected to is the gating pin. The logic cell
where the clock gating occurs is also referred to as the gating cell.

Data to data checks:

One important distinction with respect to the setup check of a flip-flop is that the data to data
setup check is performed on the same edge as the launch edge (unlike a normal setup check of a
flip-flop, where the capture clock edge is normally one cycle away from the launch clock edge).
Thus, the data to data setup checks are also referred to as zero-cycle checks or same-cycle
checks.