ISSCC 2021 / SESSION 14 / mm-WAVE TRANSCEIVERS FOR COMMUNICATION AND RADAR / 14.
14.1 A 71-to-86GHz Packaged 16-Element by 16-Beam Multi-User
Beamforming Integrated Receiver in 28nm CMOS
Emily Naviasky, Lorenzo Iotti, Greg LaCaille, Borivoje Nikolić, Elad Alon,
Ali Niknejad
University of California, Berkeley, CA
Multi-User MIMO (MU-MIMO) at mm-wave is a promising technique for high-capacity
wireless access. A base-station array of M antennas simultaneously steers K independent
2021 IEEE International Solid- State Circuits Conference (ISSCC) | 978-1-7281-9549-0/20/$31.00 ©2021 IEEE | DOI: 10.1109/ISSCC42613.2021.9365999
beams, which enables spatial multiplexing and channel bandwidth reuse across multiple
users. It has been shown that for M≫K (i.e. massive MIMO), linear algorithms can
achieve near-optimal user tracking and spatial interference rejection [1]. The power and
area demands of massive arrays are minimized with a fully connected architecture, where
each beam is a combination of all available array elements [2]. However, a massive fully
connected array results in significant hardware complexity.
Multistage beamforming, as shown in Fig. 14.1.1, provides a scalable, modularized
architecture to reduce complexity, and thus power, in massive MU-MIMO RXs [2]. The
array is divided into N subarrays, and beamforming (BF) is performed in two steps. At
the subarray level, analog conjugate BF points beams towards each user. This first stage
of BF provides voltage gain, SNR boost, and spatial filtering of out-of-beam interferers
before A/D conversion. In the digital domain, user streams from different subarrays are
then aggregated and a second digital BF step, zero forcing, is performed to reduce inter-
user interference (IUI)
A key element of this architecture is the subarray radio module, which supports K user
beams with a multi-output BF matrix. However, at mm-wave, state-of-the-art CMOS
transceiver arrays typically support only 1 to 2 user beams [3-6]. A 28GHz RX with 4-
element/4-user BF was shown in [7], but the baseband bandwidth demands of the
frequency-multiplexed user streams prevent the architecture from scaling to more users.
In this paper, we present a fully connected MIMO RX array ASIC supporting up to 16
beams and covering both the 71-to-76GHz and 81-to-86GHz bands allocated for wireless
communications (E-band). As shown in Fig. 14.1.1, a 16-element/16-beam baseband
analog BF matrix is employed to simultaneously steer 16 independent beams. The
system and circuits are optimized for power efficiency in order to enable truly massive
MU-MIMO base stations with many subarray modules and M≫K.
The ASIC includes 16 direct-conversion RX channels, LO generation and distribution,
as well as the multi-output beamformer. A mixer-first RX front-end based on the design
in [8] is employed to provide 20dB wideband gain with low power consumption. LO
circuits are shown in Fig. 14.1.2. An integer-N type-II PLL followed by a tail-switching
injection-locked frequency tripler [9] generates a 65.5-to-87GHz reference. The
differential LO tone is distributed to the RX elements using a combination of active and
passive power splitters. Non-isolated passive splitters, leveraging λ/4 transmission lines
for both power matching and LO fan-out, are used to minimize routing loss. Quadrature
generation is performed at each RX element to reduce LO routing complexity, using 16
transformer-coupled quadrature hybrids for low insertion loss and small footprint [8].
The hybrid characteristic impedance is limited to <100Ω at E-band by layout parasitics,
thus requiring significant driver current to achieve sufficient LO output swing. To reduce
the driver power, π-networks are used to match the hybrid to higher-impedance source
and loads, thus boosting the input current and output voltage (see Fig. 14.1.2). This
results in ~50% simulated power reduction, with negligible impact on quadrature
accuracy and bandwidth.
The baseband beamformer, shown in Fig. 14.1.3, performs 16 element, 16 user
conjugate beamforming. It applies 30dB of gain (including summation gain), consumes
670mW, and occupies an area of 0.7×2mm2. Wiring and parasitics of a fully connected
BF array scale with the product of number of antennas (M) and users (K), thus
optimization for low power is key. The baseband chain is composed of: 1) the distribution
stage, i.e. a two-stage, high-gain (13dB/20dB) VGA combined with a cross-beamformer
driver stage, 2) the phase shifters (PSs), i.e. digitally controlled 4-bit-I / 4-bit-Q vector
modulators, and 3) the summation stage. The distribution stage power scales with
M=16, while the PSs scale with M×K=256. Thus, budgeting 50% of the baseband power
to achieve high gain and low NF in the distribution stage reduces overall baseband power
by decreasing noise requirements in the much larger number of PS stages. The PSs can
then be resistively degenerated, which increases noise but allows for lower bias current
without increasing the gate capacitance. Total beamformer power is further reduced by
performing summation in two active stages. System optimization results, shown in Fig.
14.1.3, predict that summation power is more than halved by dividing the circuit into a
high-gain, low-wiring parasitic stage and a low-gain, high-wiring parasitic stage.
Furthermore, each summation stage employs a cascode topology to separate the
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significant cross-chip wiring parasitics from the amplifier load, thus decoupling
bandwidth and gain in a reduced footprint. After summation, high-linearity Cherry-
Hooper amplifiers drive the cross-chip routing lines between the beamformer outputs
and 32 resistively-terminated pad drivers located at the periphery of the chip.
A test chip was fabricated in 28nm CMOS, and flip-chip mounted to a 4-layer low-loss
organic BGA package, which includes a linear array of 16 cavity-backed patch antennas,
as shown in Fig. 14.1.7. Single-user continuous-wave measurement results are shown
in Fig. 14.1.4. Beam patterns are derived by transmitting a mm-wave tone and measuring
the downconverted RX power on a spectrum analyzer, after a one-time PS calibration
to compensate for delay mismatch between ASIC-antenna routing traces. Measurements
show correct single-user BF operation with 10dB worst-case sidelobe rejection.
Consistent performance is shown across different output channels and different carrier
frequencies. For PS characterization, shown in Fig. 14.1.4, magnitude and phase
information is extracted from averaged waveforms collected on a Keysight 54855A
oscilloscope.
Modulated-data wireless link measurements are shown in Fig. 14.1.5. For single-user
operation, data is produced by a Keysight 81134A pattern generator, and upconverted
to E-band using a commercial off-the-shelf (COTS) sliding-IF TX. The RX ASIC output
waveform is acquired using the oscilloscope. Beamformed single-user wireless links up
to 2Gb/s for QPSK and 16QAM without equalization are supported on the 71-to-76GHz
band with <10-3 BER. In the 81-to-86GHz band, the QPSK data rate is limited to 1Gb/s
due to a decrease in the RX mixer BW, and 16-QAM measurements could not be obtained
due to linearity limitations in the TX setup.
To demonstrate simultaneous multi-user operation, four COTS TX user-equipment (UE)
devices were assembled using FPGAs and custom PCBs that include DACs, an E-Band
quadrature upconverter, PA, and patch antenna. The 16 baseband outputs from the ASIC
are digitized using a custom ADC board and fed to an FPGA, which performs pilot-based
zero forcing to reduce IUI. Multi-user operation in Fig. 14.1.5 shows four simultaneously
received QPSK constellations from four ASIC outputs, with conjugate BF coefficients
pointed in the direction of the corresponding UEs. The data rate is limited to 250MBd
by the available ADC/DAC sampling rate. Correct BF and spatial filtering of user streams
is performed with <-11dB EVM. Multi-user wireless measurements were limited to 4
simultaneous users due to the availability of TX hardware. However, all 16 ASIC outputs
were tested, showing +/-0.5dB EVM variation across outputs.
Measured performance is summarized in Fig. 14.1.6 and compared to state-of-the-art
integrated 60-to-100GHz RX arrays. The proposed chip supports up to 2Gb/s/user
wireless links, handles 16 concurrent user streams, and covers the whole 71-to-86GHz
band. The power/antenna and power/antenna/user metrics, which are of key interest in
massive MU-MIMO systems, are also very competitive with state of the art.
Acknowledgement:
This work was supported in part by ComSenTer, a research center part of the
Semiconductor Research Corporation (SRC) program JUMP, by DARPA, the Intel
Connectivity SRS program, the NSF EARS program under Grant No. 1642920, and the
NSF Graduate Research Fellowship Program under Grant No. DGE 1752814. Authors
acknowledge the TSMC University Shuttle program for chip fabrication and Integrand
EMX for EM simulation. Thanks to Marko Kosunen, Kosta Trotskovsky, John Wright,
and Nathan Narevsky for digital design help, and to James Dunn, Nima Baniasadi,
Antonio Puglielli, Luke Calderin, and Sameet Ramakrishnan for measurement
contributions.
References:
[1] E. Larsson et al., “Massive MIMO for Next Generation Wireless Systems,” IEEE
Comm. Mag., vol. 52, no. 2, pp. 186-195, Feb. 2014.
[2] S. Mondal et al., “A 25–30 GHz Fully-Connected Hybrid Beamforming Receiver for
MIMO Communication,” IEEE JSSC, vol. 53, no. 5, pp. 1275-1287, May 2018.
[3] S. Shahramian et al., “A Fully Integrated 384-Element, 16-Tile, W-Band Phased Array
with Self-Alignment and Self-Test,” IEEE JSSC, vol. 54, no. 9, pp. 2419-2434, Sept.
2019.
[4] S. Pellerano et al., “A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver
Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology,” ISSCC, pp.
174-176, Feb. 2019.
[5] G. Mangraviti et al., “A 4-Antenna-Path Beamforming Transceiver for 60GHz Multi-
Gb/s Communication in 28nm CMOS,” ISSCC, pp. 246-247, Feb. 2016.
[6] A. Chakrabarti et al., “A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array
Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance,” ISSCC,
pp. 84-86, Feb. 2020.
978-1-7281-9549-0/21/$31.00 ©2021 IEEE
 ISSCC 2021 / February 17, 2021 / 7:00 AM

Figure 14.1.1: Block diagram of the proposed ASIC incorporated into a fully
connected massive MU-MIMO base-station receiver. Figure 14.1.2: LO generation and distribution circuits.

14

Figure 14.1.3: Baseband beamformer with circuit schematics of vector modulator

phase shifter and summation circuit, with results of system level optimization of Figure 14.1.4: Beam pattern over angle, carrier frequency, and beam output.
the two-stage summation. Characterization of single phase shifter element.

Figure 14.1.5: Measured constellations for single- and multi-user wireless data
links. Multi-user data rate is limited by the number of UEs and UE ADC/DACs Figure 14.1.6: Performance summary and comparison table with state-of-the-art
available for testing. 60-to-100GHz integrated arrays.

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 ISSCC 2021 PAPER CONTINUATIONS
Additional References:
[7] R. Garg et al., “A 28GHz 4-Element MIMO Beam-Space Array in 65nm CMOS with
Simultaneous Spatial Filtering and Single-Wire Frequency-Domain Multiplexing,”
ISSCC, pp. 80-82, Feb. 2020.
[8] L. Iotti et al., “A Low-Power 70-100-GHz Mixer-First RX Leveraging Frequency-
Translational Feedback,” IEEE JSSC, vol. 55, no. 8, pp. 2043-2054, Aug. 2020.
[9] L. Iotti et al., “A 57-74-GHz Tail-Switching Injection-Locked Frequency Tripler in
28-nm CMOS,” IEEE SSC-L, vol. 2, no. 9, pp. 115-118, Sept. 2019.

Figure 14.1.7: Die micrograph and layout of BGA package with patch-antenna array.

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