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EECS3611 Analog Electronics

Chapter 4

Frequency Responses

Outline
n Review of Bode Plots
n Frequency response
n Dominant pole for estimating frequency
response
n Short circuit time constant (SCTC)
n Open circuit time constant (OCTC)
n Miller Theorem
n Frequency responses for single-stage amplifiers

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EECS3611 Analog Electronics

Bode Plots

Bode Plot

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Bode Plots (2)

Vout (ω )
Solve impedance network transfer function H (ω ) =
Vin (ω )

Vout (w ) 1 / jwC
R H (w ) = =
Vin(w) Vout(w) Vin (w ) R + 1 / jwC
C
1
=
1 + jwRC

Convert H(w) to polar coordinates H (w ) Ðq

[
H (w ) = H (w )H * (w ) ] 1
2

ì I m (H (w ))ü
q = a taní ý
î Re (H (w )) þ

Bode Plot - Magnitude

1
1 ⎡⎛ 1 ⎞ ⎛ 1 ⎞⎤ 2
H (ω ) = ⎡⎣ H ω ⋅ H * ω ⎤⎦
( ) ( ) 2
= ⎢⎜ ⎟⋅⎜ ⎟⎥
⎣⎝ 1+ jω RC ⎠ ⎝ 1− jω RC ⎠⎦
1
⎛ ⎞ 2
1 ⎜ ⎟
⎛ ⎞ 2
⎜ 1 ⎟ ⎜ 1 ⎟ 1
=⎜ 2⎟
=⎜ 2
⎟ ,ω 3dB =
⎜ 1+ ω RC ⎟ RC
⎝ ( ) ⎠ ⎜ ⎛ ω ⎞ ⎟
⎜ 1+ ⎜ ⎟ ⎟
⎝ ⎝ ω 3dB ⎠ ⎠

Bode Plot Magnitude |H(w)|dB = 20 log |H(w)|

Gain w >> w3dB

20 dB/decade
1 w3dB
H (w ) »
-3dB point 6 dB/Octave
=
æ w ö
2
w
çç ÷÷
è w3dB ø
wp = 1/RC = w3dB 6dB/Octave – drops by 2 times
every time frequency doubles

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Bode Plot - Phase

1
H (ω ) = = H (ω ) ⋅ exp ( jθ (ω ))
ω
1+ j
ω 3dB
⎛ ω ⎞ ω ω
⎜1− j ⎟ 1− j j
1 ⎝ ω 3dB ⎠ ω 3dB 1 ω 3dB
H (ω ) = ⋅ = 2
= 2
− 2
ω ω ⎛ ω ⎞ ⎛ ω ⎞ ⎛ ω ⎞
1+ j 1− j 1+ 1+ 1+
ω 3dB ω 3dB ⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ω 3dB ⎠ ⎝ ω 3dB ⎠ ⎝ ω 3dB ⎠
⎧⎪ I ⎡⎣ H (ω )⎤⎦ ⎫⎪
m
θ (ω ) = arctan ⎨ ⎬
⎪⎩ Re ⎡⎣ H (ω )⎤⎦ ⎪⎭
ω
−
1 ω 3dB
Re {H (ω )} = 2
; I m {H (ω )} = 2
⎛ ω ⎞ ⎛ ω ⎞
1+ ⎜ ⎟ 1+ ⎜ ⎟
⎝ ω 3dB ⎠ ⎝ ω 3dB ⎠

Bode Plot – Phase (2)

log(w)
0.1w3dB w3dB 10w3dB
0
q
-45

-90
Linear Approximation

ì w ü ì w ü
q (w ) = arctan í- ý = - arctan í ý
î w3dB þ îw3dB þ

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EECS3611 Analog Electronics

Frequency Response

Overall Frequency Response

n The overall frequency
response is determined
by:
n L(s) – DC block/bypassing
capacitors, CS and CL
n M(s) - Small signal AC mid
band gain
n U(s) - MOSFET parasitic
capacitors, Cgs, Cgd, and
Cdb

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BJT Parasitic Capacitance

11

MOSFET Parasitic Capacitance

CGD
G D

CGS gmvgs gmbvbs ro

CGB
S CDB

CSB

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EECS3611 Analog Electronics

Dominant Pole for Estimating

Frequency Response

13

Dominant Pole for L(s)

14

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Short Circuit Time Constant Method

n SCTC method: find b1 based on time constant

1 1 1 b
b1 = ∑ = + ⇒ fL ≈ 1
i τ i τ CS τ CL 2π

n Steps:
n Kill all independent voltage sources by shorting them.
n Kill all independent current sources by opening them.
n When determine time constant associated with one
particular capacitor, replace all other capacitors with a
short circuit
n Only determine time constant associated with DC
block/bypass capacitors

15

Short Circuit Time Constant Example

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Dominant Pole for U(s)

17

Open Circuit Time Constant Method

n OCTC method: find a1 based on time constant

1
a1 = ∑τ i = τ Cgs + τ Cgd + τ Cdb ⇒ fu ≈
i 2π × a1

n Steps:
n Kill all independent voltage sources by shorting them.
n Kill all independent current sources by opening them.
n When determine time constant associated with one
particular capacitor, replace all other capacitors with a
open circuit
n Only determine time constant associated with
transistor parasitic capacitors

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Open Circuit Time Constant Method

Example
Remove block/bypassing capacitors,

Find τCgs,

19

Open Circuit Time Constant Example (2)

τCdb, τCgd,

20

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Overall Frequency Response

21

EECS3611 Analog Electronics

Single-stage frequency
response

22

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Steps for Frequency Analysis

23

Example: CG-Stage

24

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Example: Finding L(s)

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Example: Finding U(s)

26

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Example: Overall Frequency Response

27

EECS3611 Analog Electronics

Miller Theorem

28

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Example: OCTC for CE (1)

29

Example: OCTC for CE (2)

30

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Miller Theorem

31

Miller Theorem

From Eq.(4) in OCTC for CE(2) slide

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Outline
n Review of Bode Plots
n Frequency response
n Dominant pole for estimating frequency
response
n Short circuit time constant (SCTC)
n Open circuit time constant (OCTC)
n Miller Theorem
n Frequency responses for single-stage amplifier

33

Common-Source Stage

RL
CGD
vout Rin ZGD
v1 vout
Rin vin
vin CD ZD
ZG
CGB CGS Rout
gm vgs

Rout = RL || ro
CG = CGB + CGS

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Common-Source Stage (2)

Assume M1 is in saturation, λ=0 Rin ZGD
v1 vout
v −v v v −v vin
@ node v1 : 1 in + 1 + 1 out = 0
Rin ZG ZGD ZD
ZG
Rout
v −v v v gm vgs
@ node vout : 1 out = g m vgs + out + out ,vgs = v1
ZGD Z D Rout

Rout = RL || ro ,CG = CGB + CGS

⎛ C ⎞
⎜1− jω GD ⎟
vout ⎝ g m⎠
= −g m ⋅ Rout ⋅
vin { }
1+ jω ⎡⎣CGD 1+ g m ⋅ Rout + CG ⎤⎦ ⋅ Rin + Rout (CGD + C D ) − ω 2 Rout Rin (CGCGD + CGC D + CGDC D )
( )
⎛ C ⎞ ⎛ C ⎞
⎜1− jω GD ⎟ ⎜1− jω GD ⎟
⎝ gm ⎠ ⎝ gm ⎠
= =
⎛ ⎞ ⎛ ⎞ ⎛ ⎞
⎜1+ j ω ⎟ ⋅ ⎜1+ j ω ⎟ 1+ jω ⎜ 1 + 1 ⎟ − ω 2 1 1
⎜ ω ⎟ ⎜ ω ⎟ ⎜ω ω ⎟ ω p1 ω p2
⎝ p1 ⎠ ⎝ p2 ⎠ ⎝ p1 p2 ⎠

35

Common-Source Stage (3)

Assume ωp1 is the dominant pole, we have:
1 1 1 ⎡
+ ≈ = C 1+ g m ⋅ Rout + CG ⎤⎦ ⋅ Rin + Rout (CGD + C D )
( )
ω p1 ω p2 ω p1 ⎣ GD
1
∴ω p1 = (1)
⎡C 1+ g ⋅ R + C ⎤ ⋅ R + R (C + C )
(
⎣ GD m out G⎦ in out GD D )
1 1
Note: = Rout Rin (CGCGD + CGC D + CGDC D ) (2)
ω p1 ω p2
Substitute (1) to (2), we obtain:
⎡C 1+ g ⋅ R + C ⎤ ⋅ R + R (C + C )
(
ω p2 =
⎣ GD m out G⎦ in )out GD D

Rout Rin (CGCGD + CGC D + CGDC D )

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Common-Source Stage (4)

Assume CGD << CG ,CGD << C D ,

⎡C 1+ g ⋅ R + C ⎤ ⋅ R + R (C + C )
ω p2 =
⎣ GD m ( out G⎦ in )
out GD D

Rout Rin (CGCGD + CGC D + CGDC D )

⎡C 1+ g ⋅ R + C ⎤ ⋅ R + R (C + C )
(
≈
⎣ GD m out G⎦ in) out GD D

Rout RinCGC D
1 1 g C
≈ + + m GD
RoutC D RinCG C D CG

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Common-Source Stage (5)

1
ω p1 =
Rin ⋅ ⎡⎣CG + CGD 1+ g m Rout ⎤⎦ + Rout (CGD + C D )
( )
1 1 g C
ω p2 = + + m GD
RoutC D RinCG C D CG
gm
ωz =
CGD
⎛ ω⎞ ⎛ s⎞
⎜1+ j ⎟ ⎜1− ⎟
⎝ ωz ⎠ ⎝ sz ⎠
( )
H ω =
⎛ ⎞ ⎛ ⎞
; H s =
⎛ ()
⎞ ⎛ ⎞ sz = -jwz
⎜1+ j ω ⎟ ⋅ ⎜1+ j ω ⎟ ⎜1− s ⎟ ⋅ ⎜1− s ⎟
⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ω p1 ⎠ ⎝ ω p2 ⎠ ⎝ s p1 ⎠ ⎝ s p2 ⎠ sp1 = -jwp1
sp2 = -jwp2

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EECS3611 Analog Electronics

Frequency Response of
Common-Gate Stage

39

Common Gate Stage

Rs
vout

vin + CSB CGS RL

- CGD CDB

Assume ro ® ¥

gm vs
Rs
vs vout

vin + CD
- CS RL

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Common Gate Stage (2)

vin - vs
KCL @ vs ; = v s × j wC s + g m v s gm vs
Rs Rs
vs vout
v +
KCL @ vout ; g m vs = vout × jwC D + out vin - CS CD RL
RL
g m RL
vout 1 + g m Rs
=
vin æ ö
(1 + jwRLC D ) × çç1 + jw RsCs ÷÷
è 1 + g m Rs ø
no zeros, poles @
1
p1 =
RL C D
1 1
p2 = =
Rs
Cs ç Rs || 1 ö÷Cs
æ
1 + g m Rs ç g m ÷ø
è

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Common Gate Stage (3)

@ vout ® Req = RL 1 1
p1 = =
Ceq = C D ReqCeq RL C D

1 1 1
p2 = =
@ vs ® Req = Rs ReqCeq æ ö
gm ç Rs 1 ÷Cs
ç g m ÷ø
Ceq = Cs è

Since all caps go to ground, finding poles reduces to finding

Req’s and Ceq’s at the nodes.

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EECS3611 Analog Electronics

Frequency Response of
Source Follower

43

Source Follower
CGD

Rin
vin
vout
CGB CGS

Rs CSB

Rin vg
vin
CGS
CG= CGD +CGB vout
CSB
Rs

Small Signal Model

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Source Follower (2)

Rin
vin - v g
Rin
( )
= v g × jwCG + v g - vout × jwCGS
vin vg
CGS
CG= CGD +CGB vout
(vg - vout )× jwCGS + g m (vg - vout ) = vRout + vout × jwCSB CSB
Rs
s

g m Rsé C ù
× ê1 + jw GS ú
vout 1 + g m Rs
ë gm û
=
vin é R C R (C + CSB ) ù é C C + CSB (CG + CGS ) ù
1 + jw ê Rin CG + in GS + s GS ú - w 2 Rs Rin ê GS G ú
ë 1 + g m Rs 1 + g m Rs û ë 1 + g m Rs û

æ wö æ wö
Let denominator = çç1 + j ÷÷ × çç1 + j ÷÷
è p1 ø è p2 ø
æ 1 1 ö w2
= 1 + jw çç + ÷÷ -
è p1 p2 ø p1 p2

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Source Follower (3)

For p1 and p2 widely separated, if we assume that p1 is the dominant pole,
1 1
>>
p1 p2
1 1
p1 = =
Rin CGS R (C + CSB ) Rin CGS
Rin CG + + s GS Rin CG + + Ro (CGS + CSB )
1 + g m Rs 1 + g m Rs 1 + g m Rs
where ,
1
Ro = || Rs
gm
thus ,
Rin CGS
Rin CG + + Ro (CGS + CSB )
1 + g m Rs
p2 =
Ro Rin [CGS CG + CSBCG + CSBCGS ]

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Source Follower (4)

2 limiting cases,

Case 1:
æ CGS ö Miller cap = CGS × (1 - A)
Ro (CGS + CSB ) >> Rin çç CG + ÷
è 1 + g m Rs ÷ø A=
g m Rs
1 1 + g m Rs
w p1 =
Ro (CGS + CSB ) 1- A =
1
1 + g m Rs
Case 2:
æ CGS ö
Rin çç CG + ÷ >> Ro (CGS + CSB )
è 1 + g m Rs ÷ø
1
w p1 =
æ CGS ö
Rin çç CG + ÷
è 1 + g m Rs ÷ø

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