IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO.

9, SEPTEMBER 2021 4315

A 2.4 GHz Power Receiver Embedded With a

Low-Power Transmitter and PCE of 53.8%, for
Wireless Charging of IoT/Wearable Devices
Arash Hejazi , ByeongGi Jang, Reza E. Rad , Graduate Student Member, IEEE,
Jong Wan Jo, Student Member, IEEE, Behnam S. Rikan , YoungGun Pu , Sang-Sun Yoo , Member, IEEE,
Keum Cheol Hwang , Senior Member, IEEE, Youngoo Yang , Senior Member, IEEE,
and Kang-Yoon Lee , Senior Member, IEEE

Abstract— This article presents a 2.4 GHz and high-efficiency

wireless power receiver (Rx) integrated with a low-power trans-
mitter (Tx) for wireless charging of the Internet-of-Things (IoT)
or wearable devices. A single pole double throw (SPDT) circuit
isolates the operation of the Rx from Tx, thereby offering the
capability of sharing antenna between them. The Rx employs
a high-efficiency radio frequency (RF)-dc converter, which is
facilitated with threshold voltage cancellation technique for
enhancing the efficiency, and adjustable internal impedance
matching network to compensate the nonlinear behavior of the
input impedance with respect to input power level. In addition,
it includes a boost dc-dc converter to charge the storage element
with a fixed voltage and current. The Tx utilizes a low-power
phase-locked loop (PLL) and a class-D power amplifier (PA).
Several techniques are adopted to achieve low power consump- Fig. 1. Techniques of WPT. (a) Near-field. (b) Far-field.
tion. The chip is implemented in a 180 nm CMOS process with
a die size of 2.3 mm × 5 mm. The Rx shows the measured RF to
dc maximum power conversion efficiency (PCE) of 53.8% at the devices. Batteries require maintenance after regular intervals of
input power level of 0 dBm. The Tx achieves a variable output time and recharging, and replacement of them in a harsh envi-
power range of −10 to 10 dBm, while consumes 4 and 23 mA ronment is a difficult task. The wireless power transfer (WPT)
at 0 and 10 dBm output power, respectively. technology enables the usage of low-capacity batteries [1], [2].
Index Terms— High-efficiency, Internet-of-Things (IoT), The WPT allows power delivery without requiring wire and
low-power transmitter (Tx), power transceiver (Rx), threshold can be applied to biomedical implants, radio frequency identi-
voltage cancellation, wireless charger. fication (RFID), IoT/wearable, and difficult to access devices
to improve user convenience [3], [4]. However, the challenge
I. I NTRODUCTION of a WPT system is achieving high efficiency with a reasonable
link distance.
N OWADAYS, a stationary power supply using wires is
not attractive for mobile, Internet-of-Things (IoT), and
wearable devices. The battery as a rechargeable power supply
In WPT systems, energy can be transferred in various
forms. A well-known method is simultaneous wireless infor-
is the main source of power for the majority of electronic mation and power transfer (SWIPT), which is based on using
radio frequency (RF) signals to carry both information and
Manuscript received March 1, 2021; revised May 3, 2021 and May 25, 2021; power [5]. The other type of WPT is to transmit power over a
accepted May 28, 2021. Date of publication June 25, 2021; date of current
version September 2, 2021. This work was supported in part by the Korea long link distance through the RF waves, which can be applied
Institute for Advancement of Technology (KIAT) grant through the Korea to wireless charging of IoT/wearable devices.
Ministry of Trade, Industry and Energy (MOTIE), The Competency Develop- As illustrated in Fig. 1, electromagnetic energy can be wire-
ment Program for Industry Specialist, under Grant P0012451. (Corresponding
author: Kang-Yoon Lee.) lessly transferred by near-field and far-field techniques. The
Arash Hejazi, ByeongGi Jang, Reza E. Rad, Jong Wan Jo, Behnam S. Rikan, near-field technique by using resonant inductive and magnetic
YoungGun Pu, Keum Cheol Hwang, Youngoo Yang, and Kang-Yoon Lee are couplings offers high efficiency for the operating frequency
with the Department of Electrical and Computer Engineering, Sungkyunkwan
University, Suwon 16419, South Korea (e-mail: klee@skku.edu). range of several hundred kHz up to tens of MHz scale [6]–[8].
Sang-Sun Yoo is with the Department of Smart Automobile, Pyeongtaek These systems are highly efficient at short link distances and
University, Pyeongtaek 450-701, South Korea. safe in terms of human health [9], [10]. Nevertheless, they
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TMTT.2021.3088503. suffer from the large size of coils, which affects the portability
Digital Object Identifier 10.1109/TMTT.2021.3088503 of the device.
0018-9480 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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4316 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 9, SEPTEMBER 2021

Fig. 2. Concept of the WPT from (a) base station to device, (b) device to device, and (c) demonstration of the communication between two IoT/wearable
devices and the top block diagram of the proposed RF TRx.

The far-field technique uses RF bands and short-wavelength

while offering long communication distance. As the frequency
and the distance increase, the free-space path loss becomes
larger and the RF energy must be extracted from the air at very
low power density resulting in poor transmission efficiency.
Thus, most of the recent works try to increase the sensitivity
and efficiency of the power conversion stage.
A WPT system is more beneficial if the transmitter (Tx)
and receiver (Rx) are embedded into a device. In this case,
each IoT/wearable device can transfer the power to other
devices around it or get the power from them. It enables the
charge-sharing capability between customers. Fig. 2(a) and
(b) illustrate the concept of WPT from a base station to device
or from device to device.
In recent years, most of the works integrate the Rx with
Tx to provide the battery-less operation for the Tx with very
low input power levels. The work presented in [11], utilizes
the on-off keying (OOK) modulation technique and integrates
an energy harvester (EH) into a 2.4 GHz Tx. It transfers both
power and modulated signal with maximum power conversion
efficiency (PCE) of 15.9% that is limited by the RF-dc
converter.
Another work [12] offers a battery-less industrial, scientific,
and medical (ISM) band EH while using a six stage RF-dc
converter to receive the power level of −10 dBm or less.
It supports the frequency bands of 402/433 MHz. However,
the power efficiency is low because the antenna size for signal
reception is large.
As mentioned before, the sensitivity and efficiency of a
WPT system mainly depend on the performance of the RF-dc
converter. The literature reveals that most of the reported
CMOS RF-dc converters operate only at low-frequency bands
or the efficiency is low at higher frequency bands. The
proposed reconfigurable RF-dc converter in [13] achieves 60%
peak PCE at 868 MHz. The work in [14] presents a dual-band
RF-dc converter with an internal threshold voltage cancellation
Fig. 3. Timing diagram of the duty-cycling operation corresponding to
wireless charging or power transmission modes.
scheme, while achieves 47% and 27.1% efficiency at 902 MHz
and 2.45 GHz, respectively. Therefore, there is room for
further improvement in the efficiency of the EH block.
In this article, a new WPT mechanism for wireless charging
of IoT/wearable devices is presented. Both Rx and Tx are
embedded into a single chip, which enables power sharing
between two electronic devices. In addition, the device can
harvest power from the base station or power transmitter,
wirelessly. The efficiency of the RF-dc converter is maximized
by using the threshold voltage cancellation technique and an
internal variable impedance matching network.
The Tx and Rx operate at the same frequency of 2.4 GHz
and share the same antenna. Operation of the Rx and Tx
are isolated through an integrated single pole double throw
(SPDT), which shrinks the number of required external com-
ponents. The power management circuitry driven by the RF-dc
converter includes a boost dc-dc converter, low dropout (LDO)
voltage regulator, and band-gap reference (BGR) generator,
which regulates the output voltage of the storage device
and provides the supply voltage for different blocks of the

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HEJAZI et al.: 2.4 GHz POWER Rx EMBEDDED WITH LOW-POWER Tx AND PCE OF 53.8%
transceiver (TRx). The Tx includes a low-power phase-locked
loop (PLL) and a class-D power amplifier (PA) and offers
variable output power from −10 to 10 dBm. The power con-
sumption of the PLL is lowered by maximizing the inductance
for the resonance and it consumes 1.2 mA at 2.4 GHz.
The article is organized as follows. Section I elaborates the
operation principle of the proposed TRx. Sections II and III
discuss detailed architectures of the Rx and Tx, respectively.
Section IV presents the experimental result. The conclusion of
the article is summarized in Section V.
II. O PERATION P RINCIPLES OF THE P ROPOSED TR X
As illustrated in Fig. 2(c), the focus of this article is on
broadcasting the power between two IoT/wearable devices in
which one device either can charge another device or can be
charged by another device or base station remotely.
In the proposed architecture here, the transmitted frequency
is in the range 2.4–2.485 GHz. Since the adjacent frequency
bands are licensed, a free-running oscillator results in power
leakage into adjacent frequency bands. Therefore, a low-power
PLL is employed to generate transmission frequency within
the required frequency band. The structure of the PA is the
class-D type, which is a suitable structure for the generation
of nominal output power levels around 0 dBm.
To eliminate the degradation of the efficiency due to con-
duction loss and reverse leakage current, the RF-dc converter
is facilitated by the threshold voltage cancellation technique
and variable internal matching network. Finally, the dc-dc
converter boosts the output voltage of the RF-dc converter to
3 V, and BGR and LDO arrays provide a 1.8 V supply voltage
for different blocks of the TRx.
The proposed TRx works in two main operational modes,
wireless charging mode, and power transmission mode.
As illustrated in Fig. 3, during the wireless charging mode,
the Rx is activated and harvests energy from another device.
In this mode, the battery is charged, while in power trans-
mission mode, the proposed Tx transfers the power to other
devices and powers the devices or charges batteries around the
TRx. The micro-controller unit (MCU) and SPDT control the
switching frequency between two paths. In contrast, Tx and
Rx never operate simultaneously.
In addition, the proposed architecture can be utilized in
RFID applications too where the utilized backscattering tech-
nique is based on OOK modulation. In this regard, the reader
sends the signal to power up the tag and listens for the
response. When the tag harvests enough energy from the
reader, it responds with a 1 bit pulse-width modulated signal,
and the OOK modulation can be done by enabling or disabling
the Tx as described in [15] and shown in Fig. 3.
The power link budget of the whole TRx can be calculated
according to the following equation:
PRx = PTx + G Tx + G RX − PathLoss − μ
where PTx , G Tx , and G Rx are the output power and antenna
gains for the Tx and Rx while PathLoss and μ indicate the
free space path loss and sum of the matching network and
SPDT losses. The path loss can be obtained according to the
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4317
TABLE I
P OWER L INK B UDGET
following equation:
d
PathLoss = 20 log10 4π (2)
λ
where d and λ are the distance of Tx and Rx and wave-
length, respectively. Therefore, the values of the parameters
are summarized in Table I. Considering the 50% efficiency of
the Rx, continuous operation of the Tx is not possible if the
saved power across the battery is less than the required power
for power transmission. Thus, the battery should be charged
sufficiently to provide the power for the Tx part, which in the
case of harvesting low-power levels the charging time would
be longer than that of harvesting high power levels.
III. P ROPOSED RF W IRELESS P OWER R X
As illustrated in Fig. 2(c), the RF-dc converter is the first
block of the Rx and rectifies the RF input signal. Since the
output voltage level of the RF-dc converter is not sufficient to
charge the battery and has ripples, a boost dc-dc converter is
required. The dc-dc converter omits the voltage ripples of the
RF-dc converter and boosts the output voltage of the RF-dc
converter to 3 V.
A. Proposed RF-DC Converter
The threshold voltage of the RF-dc device as the first block
of an EH system determines the performance of the RF-dc
converter, which is the minimum voltage level of the device
to turn on as a rectifying device. Minimizing threshold voltage
extends the sensitivity of the RF-dc converter to lower input
power levels and provides higher output voltage for the same
input power level.
The received RF signal by the antenna is fed to the matching
network to match the source impedance of the antenna with
the load impedance of the RF-dc converter. Since in EH
applications the power level of the received RF signal is
variable, implementing an efficient matching network becomes
challenging [16], [17]. Therefore, a variable matching network
can enhance the efficiency of the whole system considering
the nonlinear behavior of the load impedance of the RF-dc
converter with respect to the input power level.
(1) Design challenges of an RF-dc converter such as the number
of stages, sensitivity, and efficiency are related to each other.
Increasing the number of stages results in more power loss
across each stage while fewer stages provide less voltage
drop between the stages and higher threshold voltage for
all. In contrast, more stages achieve high sensitivity and
4318 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 9, SEPTEMBER 2021

Fig. 4. Circuit and design environment of the proposed RF-dc converter.

fewer stages give more PCE, accordingly. Thus, the design Equations (3) and (4) describe the VRF−dc as a function of
needs to be optimized considering the application target and VRx_IN , VSD4 , VSD5 , and Vcomp
specifications [18], [19].
Fig. 4 shows the schematic of the proposed RF-dc converter. VRF−dc = VRx_IN − VSD4 (3)
An external L-type impedance matching network is provided VRF−dc = VSD5 + Vcomp . (4)
to ensure the maximum power transfer between the RF source
and the load. A tunable capacitor bank is applied to match By adding (3) and (4), VRF−dc can be represented as
the internal impedance of the circuit concerning different
input power levels. The input impedance of this work has VRF−dc = 1/2(VRx_IN − VSD4 + VSD5 + Vcomp ) (5)
been optimized for 0 dBm. Therefore, if we consider the
case the power drops to lower power levels there will be an where VSD4 and VSD5 are the voltage drops across the M4 and
impedance mismatch, which degrades the efficiency of the M5, respectively. When M4 and M5 are in the saturation
system. The on-chip adaptive matching network contains a region, VSD4 and VSD5 are the threshold voltages of M4 and
switched-capacitor array. Initially, the optimized output volt- M5, respectively. Similarly, the VRF−dc can be represented by
age of the rectifier is observed at different input power levels VSG and VSD of the M4 and M5 as
and the switched capacitor array has been fixed with respect
to each power level. Then the digital controller is designed to VRX−IN = VSG4 + Vcomp . (6)
adjust the matching characteristics for different power levels.
Therefore, the digital controller adjusts the capacitor array By putting (6) into (3), we can get
automatically.
The RF-dc converter supports the wide input power range VRF−dc = VSD4 + VSG4 + Vcomp (7)
from −10 to 10 dBm while providing an output voltage level VRF−dc = VSG5 + Vcomp . (8)
from 0.5 to 2.9 V. During the negative phase of the RF
input signal, the transistors M4 and M5 are reverse-biased. By subtracting (7) from (8), (9) can be obtained
In this case, the Vcomp will be connected to VRF−dc and the
source–gate voltage of the M2 becomes larger, thereby reduc- VSD4 = VSG4 − VSG5 . (9)
ing the source–gate voltages of the M4 and M5 to zero and
leakage current. In this case, the purpose of the Ccomp capacitor Equation (8) clearly shows that the value of VSG5 increases
is to preserve some part of the charge lost during the reverse with VRF−dc . The M4 enters the saturation region when VSG5
conduction in the RF-dc converter. During the positive phase equals the threshold voltage. Through (5) and (9), VRF−dc can
of the RF input signal, the transistors of M4 and M5 are be calculated as follows:
forward biased while the transistor M1 compensates for the
forward loss and results in the reduction of the threshold VRF−dc = 1/2(VRx−IN −VSG4 +|VTH4|+VSG5 −|VTH5|+Vcomp )
voltage of the transistors M4 and M5, thereby increasing the VSG4 = VSG5 = VTH (10)
forward current. Since the gate voltage of M4 and M5 are VRF−dc = 1/2(VRx_IN + |VTH4 | − |VTH5 | + Vcomp ). (11)
connected to RX−IN through the M1, the source–gate voltage
of M2 lies below the threshold voltage and remains turned Thus, the effect of the threshold voltage on the dc output
off. voltage is minimized.

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HEJAZI et al.: 2.4 GHz POWER Rx EMBEDDED WITH LOW-POWER Tx AND PCE OF 53.8%
Fig. 5. Block diagram of the proposed boost dc-dc converter.
Fig. 6. Circuit implantation and timing diagram of the PWM generator.
B. Structure of the Proposed DC-DC Converter and LDO
Fig. 5 demonstrates the top block diagram of the boost
dc-dc converter. The dc-dc converter structure includes power
MOS, gate driver, gate controller, zero current detector (ZCD),
type III compensation, error amplifier, soft-start, sawtooth
generator, comparator, and non-overlap generator.
In the proposed architecture, a single pulse width modu-
lation (PWM) associated with the sawtooth generator omits
the phase mismatch and discontinuity of the regulation and
provides good regulation characteristics with a low output
ripple. The boost dc-dc converter generates the output voltage
of 3 V from the rectified voltage of 0.5–2.9 V. The operation
is defined by using an external 6.8 μH inductor and 1 μF
capacitor, while the switching frequency is 2 MHz. Initial
inrush current is suppressed by minimizing the voltage gap
between input and output by the soft-start circuit. The ZCD
improves the efficiency of the dc-dc by reducing a control
loss account for a large proportion of dc-dc converter in a
light load current condition. For low power implementation
and decreasing the area, the type III compensation technique
is used, and to limit the switching ratio of the dc-dc converter
for safe operation, a duty limiting circuit is added. VCMAX
is added to limit the maximum duty, while VCMIN limits the
minimum duty (see Fig. 6). Fig. 7 shows the simulation result
of the dc-dc converter when the input voltage is 600 mV.
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4319
Fig. 7. Simulation result of the dc-dc converter with 600 mV input voltage.
Fig. 8. Schematic of the proposed LDO.
The LDO voltage regulator is widely used for voltage level
conversion and the stability of the output voltage over PVT
variations. Design of a high power supply rejection ratio
(PSRR), fast settling time (FST), and low noise LDO is critical
in state-of-art complex mixed-signal circuits, in which various
systems are implemented into a single chip. The BGR and
LDO array consists of a BGR and four low-noise LDOs, each
making 1.8 V core supply voltage for different blocks of the
TRx.
As shown in Fig. 8, at the output of the BGR, a low pass
filter (LPF) removes the output noise of the BGR. During the
initial time, both enables of the LDO and BGR are 0 and 1,
respectively. Therefore, the resistor of the LPF is bypassed
through a switch. In this case, BGR voltage is applied to the
LDO without any delay and charges the output capacitance
with an FST. Then, LDO becomes enable, and the output
voltage of the BGR is applied to the LDO through the LPF
and suppresses the output noise of the LDO.
IV. P ROPOSED W IRELESS P OWER T RANSMITTER
According to Fig. 9, the main building blocks of the Tx
are an analog PLL and a class-D PA. The SPDT provides
the selection ability between the Rx and Tx. As shown
in Fig. 10, in conventional architecture, external components
are utilized to provide some essential functions including
impedance matching, switching between Rx and Tx, and filters
for attenuations of harmonics of the Tx. In the proposed
architecture, the TRx switch, Rx, and Tx are integrated into
a single chip. Meanwhile, the only external component is the
matching network, which is shared between the Rx and Tx.
A. Phase-Locked Loop
As depicted in Fig. 9, the PLL structure consists of
a phase-frequency detector (PFD), charge-pump (CP), a
4320 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 9, SEPTEMBER 2021
Fig. 9. Top block diagram of the RF power transmitter.
Fig. 10. TRx architectures with SPDT. (a) Conventional. (b) Proposed.
third-order loop filter (LF), voltage-controlled oscillator
(VCO), dividers [/2, fractional divider with delta–sigma mod-
ulator (DSM)], resistive feedback buffer, and PLL calibration.
The frequency range of the PLL is from 2.4 to 2.485 GHz and
the resolution of the frequency is 10 kHz. This frequency step
is realized by adjusting the controlling bits of the DSM. The
fractional-N divider is composed of the pulse-swallow counter
with divide-by 4/5 and third-order DSM.
The PLL works in two main operating modes, mode 1 and
mode 2. During mode 1, the PLL calibration block through
the frequency-locked loop (FLL) locates the VCO output
frequency close to the target frequency by the open-loop
operation. This approach is realized by utilizing a binary
searching algorithm and counting the number of the clock
cycles of the VCO within a mask-time and comparing it with
a reference number as presented in [20]. The FLL adjusts
the provided binary-weighted cap banks (Cap_Cont 7:0)
inside the VCO. Once the FLL is locked, the LOCK signal
would be activated, and to save the power, FLL is disabled.
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Finally, in mode 2, the PLL adjusts the frequency of the whole
loop through the closed-loop operation. Fig. 11 shows the
schematic of the proposed VCO. As mentioned before, for
WPT applications, power consumption needs to be minimized.
In contrast, VCO as one of the power-hungry blocks of the
Tx, demands low power design.
Typically, there are two ways to tune the frequency in the
PLL, continuous tuning, and discrete tuning. If the VCO is
implemented based on continuous tuning, to cover the whole
frequency range considering the PVT variation, a high VCO
gain (KVCO) is needed. Thus, the varactor size should be
larger but it decreases the oscillation amplitude. Moreover,
increasing VCO gain introduces higher amplitude modulation
to frequency modulation noise and degrades the phase noise
performance of the VCO.
The switched-capacitor structure is often used for dis-
crete frequency tuning. To improve the quality factor and
on-resistance of the switches, the transistor size should be
larger. However, large-size switches increase the equivalent
capacitance when the switch is off, and consequently would
limit the tuning range of the VCO.
For a given supply current and oscillation frequency,
the value of the inductor must be increased to enhance the
voltage swing and hence decrease the relative phase noise.
Since the achieved phase noise is often better than what is
required, further reducing the power consumption is a key
optimization strategy. Therefore, increasing the inductance
while keeping the quality factor of the tank high, will give
the benefit of lowering the power consumption as much as the
phase noise performance is acceptable.
The metal-oxide-metal (MOM) capacitors offer less tem-
perature variation, and high-quality factor compared to MOS
capacitors. The custom-made MOM capacitors are stacked
from metal 4 to 6 (see Fig. 11). The weights of the capacitors
inside the capacitor bank are 1, 2, 3, 4, 8, 16, 32, and
64, in which one redundant bit with the weight of three is
considered to eliminate any blind zone inside the frequency
range.
Parasitic inductance and resistance of the VCO routing
lowers the quality factor of the tank inductance and degrades
the phase noise performance of the VCO. As shown in Fig. 11,
the top plate of the capacitors is paralleled using metal 6. The
parallelization lowers the parasitic inductance and resistance
of the VCO routing. Besides, the bottom plate connections
of the capacitors using metal 5 carry the opposite current of
the top plate layer, thereby subtracting the mutual inductance
from self-inductance. Moreover, the main branch of the routing
from the inductor to different parts of the VCO is connected
through the via and wide metal line, that ties all parasitic effect
in parallel. It will give the benefit to have linear frequency
steps by the capacitor banks as described in [21].
B. PA and SPDT
Fig. 12 indicates the proposed class-D PA with the SPDT
circuit. The class-D PA is an alternative that is simpler and
requires less passive element than a differential topology or
other classes and suitable for transmitting the nominal output
HEJAZI et al.: 2.4 GHz POWER Rx EMBEDDED WITH LOW-POWER Tx AND PCE OF 53.8%
Fig. 11. (a) Schematic of the proposed VCO. (b) Layout pattern of the capacitor bank for minimizing parasitic inductance.
Fig. 12. Circuit of the proposed class-D PA and SPDT.
power levels. The PA consists of 32 PA units and can satisfy
the wide range of output power from −10 to 10 dBm. When
more units are active, the overall on-resistance is smaller and
the output power is increased. The class-E PA employs an
inductor at the drain of switching MOSFET, which demands a
high voltage MOSFET. The high voltage MOSFET has a larger
on-resistance compared to low voltage devices. Therefore, con-
sidering the efficiency and area, a class-D PA is implemented.
The internal matching network matches the output impedance
of the PA and suppresses higher-order harmonics.
As depicted in Fig. 12, the SPDT circuit is realized through
the body floating technique and pull-down switches to improve
the insertion loss and isolation. By using the body-floating
technique, the body of the transistors is connected to the
ground with big resistors. Since the resistance connected to
the ground is very high compared to the on-resistance of
the switch, still the input impedance will be the same as the
on-resistance of the transistor. The ratio of the transistors in
series and shunt branches influences the performance of the
insertion loss. To achieve low insertion loss and moderate
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4321
isolation, a large size of the transistors for the series path
and small size of transistors for the shunt branch are needed,
which has been discussed in detail in [22].
V. E XPERIMENTAL R ESULTS
The measurement environment and the chip microphoto-
graph of the proposed TRx are presented in Fig. 13. The chip
is implemented in a 180 nm CMOS process with a die size
of 2.3 mm × 5 mm. As shown, the measurement environment
of the TRx includes two boards of the designed architecture in
which one board is connected to the power supply to transmit
the power and another board is connected to the cell phone
as Rx to be charged remotely. The measurement environment
also contains two antennas, a personal computer (PC), an serial
peripheral interface (SPI) controller, a spectrum analyzer to
measure the PLL, the network analyzer to check the matching
network, and the cable. Fig. 14 indicates the top simulation
result of the Rx. After turning on the BGR and LDO, when
the LDO voltage is set to 1.8 V, the dc-dc high side voltage
(HH) becomes high, and the output of the RF-dc converter
rises. The output voltage of the dc-dc is boosted to 3 V when
the output voltage of the RF-dc is settled to 980 mV.
Fig. 15 shows the measured S-parameter and the efficiency
of the RF-dc converter versus the RF input power level at
2.4 GHz. The peak PCE of 53.8% is measured at 0 dBm input
power level when the optimum internal matching network
is applied and 9–15% improvement is achieved compared
to those with a fixed matching network. Compared with the
post-simulation results, the measured efficiencies are reduced
by 10% due to parasitic effects and the manual welding
process.
Measured waveforms of the boost dc-dc converter are
illustrated in Fig. 16. When the input voltage is 1 V, the output
voltage is regulated to 3 V while the switching frequency is
2 MHz, the same as the simulated result.
The phase noise and the output spectrum of the VCO are
depicted in Fig. 17. The proposed VCO achieves the output
frequency tuning range of 2.1–3.1 GHz and the phase noise
4322 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 9, SEPTEMBER 2021

Fig. 15. Measured result of the RF-dc converter S-parameter and input power
versus efficiency and output voltage.
Fig. 13. Measurement environment and chip microphotograph of the
proposed TRx.

Fig. 14. Top simulation result of the proposed Rx path.

Fig. 16. Measured waveforms of the proposed boost dc-dc converter.

performance of −99.55 and −117.96 dBc/Hz at 100 kHz and
1 MHz offset frequencies from 2.4 GHz carrier frequency,
respectively. The VCO shows an 800 mV p-p swing and
consumes 0.7 mA current from the 1.8 V power supply. The
current consumption of the VCO could be decreased more; in
this case, it offers less p-p swing, and a buffer with a large size
and high current consumption is needed. It should be noted
that power consumption, tuning range, and phase noise are
related to each other. Therefore, the figure of merit (FoM) can
compare the deigned work with the other works fairly. The
FoM for the VCO is defined as follows: Fig. 17. Measured phase noise and frequency spectrum of the proposed
   VCO.
f0 FTR (%) PDC
FoM= PN−20 log +10 log
1 MHz 10 1 mW where PN, f 0 , and FTR indicate the phase noise, oscillation
(12) frequency, and tuning range, respectively. The proposed VCO

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HEJAZI et al.: 2.4 GHz POWER Rx EMBEDDED WITH LOW-POWER Tx AND PCE OF 53.8% 4323

Fig. 18. Measured output power of the Tx at 9.49 dBm.

Fig. 21. Measurement environment of the eight channels Rx with 16 beam-

forming antennas.

Fig. 19. Measured output power of the Tx versus the number of PA unit.

Fig. 22. Received power with respect to the number of antennas.

TABLE II
S UMMARY OF P ERFORMANCE C OMPARISON

Fig. 20. Insertion Loss and isolation of the SPDT.

achieves the FoM of −199 dBc/Hz with a high-frequency tun-

ing range and low-power consumption while having acceptable
phase noise performance.
Fig. 18 shows measured output spectrum characteris-
tics of the Tx when the output power is approximately
9.5 dBm. Fig. 19 illustrates the measured output power
of Tx with respect to the number of active class-D PA
unit cells. The maximum output power level of 10.3 dBm
is achieved when all the units of the PA are active.
Fig. 20 shows the simulated result of the SPDT. The inser-
tion loss and isolation of the SPDT are 0.37 and 32.1 dB, between Tx and Rx is 0◦ and 26.76◦ with respect to the number
respectively. of beamforming antennas.
In another measurement case, eight-channel Rx has been Table II summarizes the performance of the pro-
targeted with 16 beamforming antenna arrays with a total gain posed TRx and compares it with the recent works. The
of 25 dBm while the Rx and beacon Tx are located at a link works in [23]–[25] present RF energy harvesting sys-
distance of 2 m. As Fig. 21 shows, the cell phone and air tems and achieve excellent PCE and sensitivity at lower
buds can be charged remotely. Fig. 22 summarizes the received input power levels which are suitable for biomedical,
power by the Rx when the link distance is 2 m and the angle wearable/implementable systems, and RFID applications.

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4324 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 69, NO. 9, SEPTEMBER 2021
A minimum input signal is a characteristic of these systems
where charging capacitors or batteries take a considerable
amount of time at the sensitivity levels. Therefore, extending
the sensitivity of the energy harvesting systems to higher
power levels with high PCE would give the benefit for fast
charging of IoT/wearable devices.
The work proposed in [14] is suitable for wireless charging
applications while offers higher efficiency at 0 dBm input
power level at both 902 MHz and 2.45 GHz. The work
proposed in [26] achieves excellent efficiency while the oper-
ation frequency is 900 MHz. As the comparison table shows,
the proposed work utilizes the optimized architecture and
internal adaptive matching network and offers high efficiency
over a wide input power at 2.4 GHz.
VI. C ONCLUSION
A wireless battery charger system implemented in a
180 nm CMOS process is presented. The proposed architecture
achieved a sensitivity of −10 dBm and a maximum PCE
of 53.8% at 0 dBm input power level. The Tx is adapted with
variable output power from −10 to 10 dBm. Both Rx and Tx
by using SPDT, share the same antenna, and operate at the
same frequency of 2.4 GHz.
The Rx consumes 370 μA current when the rectified signal
range is from 0.5 to 2.9 V. The whole Tx consumes 4 mA
when the transmitter output power is set to 0 dBm. The
main application of this work is for wireless charging of
IoT/wearable devices such as smart-watches or bracelets.
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Arash Hejazi received the B.S. degree in electrical
and electronics engineering from the Islamic Azad
University of Urmia, Urmia, Iran, in 2013, and
the M.S. degree in electrical and communication
majoring in the system the field of digital signal
processing engineering from the Urmia Graduate
Institute, Urmia, in 2016. He is currently pursu-
ing the Ph.D. degree in electrical and electronics
engineering at the ICLab, Sungkyunkwan University,
Suwon, South Korea.
Since 2020, he has been a Senior Engineer with
Skaichips Company Ltd., Suwon. His research interests include CMOS
radio frequency (RF) transceivers, phase-locked loops (PLLs), delay-locked
loops (DLLs), RF switches, and time-to-digital converters for time-of-flight
applications.
HEJAZI et al.: 2.4 GHz POWER Rx EMBEDDED WITH LOW-POWER Tx AND PCE OF 53.8%
ByeongGi Jang received the B.S. degree from
the Department of Electronic Engineering, Chonbuk
National University, Jeonju, South Korea, in 2015,
where he is currently pursuing the joint Ph.D. and
M.S. degrees at the College of Information and Com-
munication Engineering, Sungkyunkwan University,
Suwon, South Korea.
His research interest includes power management
IC.
Reza E. Rad (Graduate Student Member, IEEE)
was born in Qazvin, Iran, in 1984. He received
the B.S. and M.S. degrees in electronics engineer-
ing from Qazvin Azad University (QIAU), Qazvin,
in 2009 and 2016, respectively. He is currently pur-
suing the Ph.D. degree at Sungkyunkwan University,
Suwon, South Korea.
He is currently a Research Engineer with
Skaichips Company Ltd., Suwon. His research inter-
est is the design of the radio frequency (RF) trans-
ceivers and their sub-blocks.
Jong Wan Jo (Student Member, IEEE) received
the B.S. degree from the Department of Electronic
Engineering, Cheongju University, Cheongju, South
Korea, in 2018, where he is currently pursuing
the joint M.S. and Ph.D. degrees at the College
of Information and Communication Engineering,
Sungkyunkwan University, Suwon, South Korea.
His research interests include wireless power trans-
fer systems and power management IC.
Behnam S. Rikan received the Ph.D. degree in elec-
tronic engineering from the School of Information
and Communication Engineering, Sungkyunkwan
University, Suwon, South Korea, in 2017.
He was a Post-Doctoral Researcher with the Uni-
versity of Oslo, Oslo, Norway, and an Analog
Design Engineer at Sony Nordic, Oslo. He is cur-
rently a Research Professor with Sungkyunkwan
University and a Senior ASIC Designer with
Skaichips, Suwon. His research interests include
analog to digital converters, analog and radio fre-
quency (RF) front-end CMOS circuit design, CMOS image sensors, and
sequential 3-D IC design.
YoungGun Pu received the B.S., M.S., and Ph.D.
degrees from the Department of Electronic Engi-
neering, Konkuk University, Seoul, South Korea,
in 2006, 2008, and 2012, respectively.
From 2012 to 2013, he served as a Senior Engineer
with the Modem RF Laboratory, DMC Research and
Development Center, Samsung Electronics, Suwon,
South Korea. From 2013 to 2019, he worked as a
Senior Engineer with WDT/Hivics, Pangyo, South
Korea. He is currently a Research Professor with
Sungkyunkwan University, Seoul. His research inter-
est is focused on high-speed interface, CMOS fully integrated frequency
synthesizers, oscillators, and radio frequency (RF) transceivers.
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4325
Sang-Sun Yoo (Member, IEEE) received the B.S.
degree from Dongguk University, Seoul, South
Korea, in 2004, and the joint M.S. and Ph.D. degrees
from the Korea Advanced Institute of Science
and Technology (KAIST), Daejeon, South Korea,
in 2012.
He worked with the System LSI Division, Sam-
sung Electronics, from 2012 to 2015, where he
focused on all-digital phase-locked loop (ADPLL)
for 3/4G mobile applications as a Senior Design
Engineer. From 2015 to 2016, he was a Research
Assistant Professor with KAIST and Sungkyunkwan Universities, Suwon,
South Korea. Since 2017, he has been with the Department of Smart Automo-
bile, Pyeongtaek University, Pyeongtaek-si, South Korea, where he is currently
an Assistant Professor. His research interests include radio frequency (RF)
systems for mobile communications, reconfigurable RFICs, automotive ICs,
ADPLL, RF identification (RFID), and sensor communications.
Keum Cheol Hwang (Senior Member, IEEE)
received the B.S. degree in electronics engineer-
ing from Pusan National University, Busan, South
Korea, in 2001, and the M.S. and Ph.D. degrees
in electrical and electronic engineering from the
Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, South Korea, in 2003 and 2006,
respectively.
From 2006 to 2008, he was a Senior Research
Engineer with Samsung Thales, Yongin, South
Korea, where he was involved with the development
of various antennas, including multiband fractal antennas for communication
systems and the Cassegrain reflector antenna and slotted waveguide arrays
for tracking radars. He was an Associate Professor with the Division of
Electronics and Electrical Engineering, Dongguk University, Seoul, South
Korea, from 2008 to 2014. In 2015, he joined the Department of Electronic
and Electrical Engineering, Sungkyunkwan University, Suwon, South Korea,
where he is currently an Associate Professor. His research interests include
advanced electromagnetic scattering and radiation theory and applications, the
design of multiband/broadband antennas and radar antennas, and optimization
algorithms for electromagnetic applications.
Prof. Hwang is a Life Member of the Korean Institute of Electromagnetic
Engineering and Science (KIEES) and a member of the Institute of Electron-
ics, Information, and Communication Engineers (IEICE).
Youngoo Yang (Senior Member, IEEE) was born
in Hamyang, South Korea, in 1969. He received the
Ph.D. degree in electrical and electronic engineering
from the Pohang University of Science and Technol-
ogy, Pohang, South Korea, in 2002.
From 2002 to 2005, he was with Skyworks Solu-
tions, Inc., Newbury Park, CA, USA, where he
designed power amplifiers for various cellular hand-
sets. Since 2005, he has been with the School
of Information and Communication Engineering,
Sungkyunkwan University, Suwon, South Korea,
where he is currently a Professor. His current research interests include
radio frequency (RF)/mm-wave power amplifiers, RF transmitters, and dc-dc
converters.
Kang-Yoon Lee (Senior Member, IEEE) received
the B.S., M.S., and Ph.D. degrees from the School
of Electrical Engineering, Seoul National Univer-
sity, Seoul, South Korea, in 1996, 1998, and 2003,
respectively.
From 2003 to 2005, he was with GCT Semicon-
ductor Inc., San Jose, CA, USA, where he was
the Manager of the Analog Division and worked
on the design of CMOS frequency synthesizer
for code division multiple access (CDMA)/personal
communication service (PCS)/personal digital cel-
lular (PDC) and single-chip CMOS radio frequency (RF) chipsets for
wideband-CDMA (W-CDMA), wireless local area network (WLAN), and
personal handy-phone system (PHS). From 2005 to 2011, he was an Associate
Professor with the Department of Electronics Engineering, Konkuk University,
Seoul. Since 2012, he has been with the College of Information and Commu-
nication Engineering, Sungkyunkwan University, Suwon, South Korea, where
he is currently a Professor. His research interests include the implementation of
power integrated circuits, CMOS RF transceivers, analog integrated circuits,
and analog/digital mixed-mode very large scale integration (VLSI) system
design.