E

E , Dd
h &
E /
E
& E , Dd
E , D d , Dd
• E E

• &
s
• / DK & d / s
VDS VDS
200
s s
180
- + - +
/
160 s s
+ 140
0V
s s
Gate Gate 120
Source P-GaN Drain Source P-GaN Drain
AlGaN Barrier Layer AlGaN Barrier Layer 100
s s
GaN Buffer Layers
2DEG Channel
GaN Buffer Layers 2DEG Channel 80
60
Si substrate Si substrate 40
s s
20
0
s s
0 5 10 15 20
Substrate Substrate

E
 , Dd
D d Drain
§ d
§ s /
§ / RG,ext Gate RG,intCGD
§ Z CDS
CGS

§ D > >
CISS = CGD+CGS
§ , s s Source
§ > s s

s E E
> D d / d / D d
E , Dd
§ D s
§ E D s s s s
§ E WE d
s s s s

E
Z

Gate GaN E-HEMT MOSFET Si IGBT

-G4 X / [X

A
RDS(ON)
ON

ON RDS(ON)

B
C VTH+VGS(OFF)
OFF

RDS(REV)

§ No body diode，but 2DEG can conduct in 3rd quadrant – No need for anti-parallel diode
§ When gate is OFF (during dead time)， 2DEG exhibits like a diode with VF= Vth+ VGS(off)
§ Reduce dead time loss: 1) minimize dead time; 2) Use smaller or avoid negative VGS if possible
E
Z
Reverse Recovery charge QRR:
§ GaN has zero QRR making it suitable for half bridge hard switching – Replace IGBT
§ Si MOSFET can’t be used for any half bridge hard-switch circuit due to QRR
§ Excellent reverse recovery of GaN enables new topologies such as bridgeless totem pole PFC

.GRL HXOJM [XT UT 90 59,+: .GRL HXOJM [XT UT -G4 + .+ :

E E :
Snappy recovery : s
1. High dI RR/dt,
D d parasitic ringing
2. Body diode
> : D s
ruggedness Qoss Loss only:
1. Much lower turn-on loss
2. No snappy recovery and
uncontrolled high dIrr/dt
3. Clean waveforms
s

E
§ &
§ Z
§ ,
§ /

§ ,

§ & s
§ & s E s
VDS td(off) td(on) tr

VGSH
VGS_Q1 VGS_Q2

VGSL
PWM signal dead time td_pwm
Actual dead time
Td_actual ~= td_pwm - tdelay_skew - td(off) + td(on)
E
q

qW >

q d

E
 E DK & d s
§ E DK & d Z

GaN E-HEMT GS66508T

VDS=400V (650V/50mΩ) VDS=400V

Cree SiC C3M006509D (900V/ GaN E-HEMT SiC

65mΩ)

5.7ns
10ns
17ns (18V/ns)
4.5ns (90V/ns)

Vgs=12V/-3V (SiC) Vgs=12V/-3V (SiC)

Vgs=6V/-3V (GaN E-HEMT) Vgs=6V/-3V (GaN E-HEMT)

VGS

Double Pulse Test Hard Switch Turn-on

(VDS=400V, ID=15A, RG(ON)=10Ω)
Hard Switching Turn-off (VDS = 400V, ID = 15A, RG(OFF)=1Ω)

E
 E , Dd

§ , / s → Need to protect gate spikes from going above

§
t
§ K E
§ d s

§ s

E
 Z >

s s
W E
VDS VDS
LD
LD CGD
LG RG
CGD CDS
LG RG imiller CGS
CDS ROL
imiller CGS LCS
ROL
LCS VGS+_pk LS
LS VGS
VGS VGS-_pk
§ W § K
§ Z ZK>
§ > > § < s s
§ h s § Z ZK> >
§ s s > s s d,

E
§ &
s >
§ W s s s / Z
§ &
Z >
§ & ds
§
§ E s s
,
s E > DW E > DW

RGON CGD
s Gate
VO
Driver
GND RGOFF D1
CGS
Dclamp
LCS
s
+6V
s
s VDD
RGON
D
VO+ s
s Gate
RGOFF G s
Driver VO- DZ1 S
s
VEE -3V 3V3
D2
E
 D
§ E , Dd Gate
RGON
G
§ Z KE Z K&& Driver VO
GND S
RGOFF D1
§ Z
§ Z Z KE Z K&& ≥ Low Vf Schottky Diode

§ E D

§ d Z KE
§
§ d Z KE RGON D
§ d Z KE , , Gate VO+
G
Driver RGOFF
VO-
S
§ & Z KE Ω GND

§ d Z K&&
§ d Ω
§ W W
E
D
t
§ > LD
§ / > & LG RG CGD
§ CGS
§ E LCS
LS
t
§ & > > F B1
RG1
§ >
§ > W
Z=10-20

§ h > LCS

§ Z
§ d s
§ > LG RG1
3.3 RS1
§ h Ω D, 100-200pF CS1 LCS
>
§ Z Z &
E
,
,
§ E s
VCM
ICM
0V
§ D /K
CIO

§ D Dd/ Isolated DC/ ICM

/K VCC
DC D
§ h Dd/ RG_ON
G
§ / PWM Isolator Gate Driver RG_OFF
S
§ CIO
§ / D 0V ICM
0VGDH
High side floating ground VCM

§
§ s D
§ > ICM
§ :
t VCC CIO

Isolated DC/
DC

§ W
High side floating ground
E
 § s
§ t
§ E , Dd s s
§ > s s
§ , s s
§ W s
Can be over-charged to 7-9V
+6V
DBS
VDRVH s
VBUS+
h > K s s
0.6V CBOOT +9V LP2985IM5-6.1 +6V
R1
D IN OUT +6V VDRV
0VGDH RG_ON DB1
G GND C1
0V Gate Q1
PWM_H Isolator RG_OFF CB1
Driver S DB1
DZ1 C1
0V 0VGDH 5.8V
0VGDH
VOUT h 0V
0V 0VGDH
+9V +6V
-2 ~ -2.5V D - 1K
RG_ON G
Q2
VSD DB1 s
Gate DZ1 C1
PWM_L Driver RG_OFF +
S CB1 5.8V

GND 0V 0VGDH
E
Z E /
The following drivers have been verified by GaN Systems and are recommended for use with our GaN E-HEMTs：

Configurations Gate Driver/Controller IC Design resources

650V Half/Full Bridge: Si8271 – Single; Si827x Datasheet
Si8273/4/5 – HB/Dual Si8271 demo board (GS66508T)
1. DC/DC: LLC, PSFB, -GB (0-6V) or –AB (-3/+6V) IMS evaluation board User Guide
Sync Boost/Buck
2. AC/DC: Totem pole ADuM4121ARIZ (0-6V Drive) ADuM4121 Datasheet
PFC, Active Clamp ADuM4121BRIZ (-3/+6V Drive)
Flyback ACPL-P346 Datasheet
3. Inverter, motor drive ACPL-P346
ACPL-P346 Evaluation Board with
Use -4/+6V gate drive
GS66508T
80-100V Half/Full bridge LM5113(NRND): 100V, max 5MHz LM5113 Datasheet
LMG1205: 80V/5A HB Driver LMG1205 Datasheet
1. 48V DC/DC
2. 48V POL PE29101: 100V, 48V DC/DC, PE29100 Datasheet
3. Sync. Buck/Boost 33MHz PE20102 Datasheet
4. Class D Audio PE29102: 60V, Class D Audio, PE29102 Demo board (GS61004B)
5. Wireless Power WPT, 40MHz
Transfer UPI Semi GaN FET drivers: uP1966A GaN Driver
uP1966A: Dual-Channel GaN Ultra High Speed 80V HB Driver for
driver GaN Application
E
Z E /
Configurations Gate Driver/Controller IC Design resources
Low side non-isolated LM5114/UCC27511: Single LM5114 Datasheet
driver for 650V/100V GaN*: Channel, 4A, 5-6V drive UCC2751x Datasheet
UCC27611: w/ internal LDO (5V)
1. Flyback, Push-pull
uP1964 Datasheet
2. Forward uP1964: Internal LDO for 6V drive
3. Boost PFC
4. Secondary SR Other GaN IXD609SI: Single, 6V drive, high drive current (9A)
5. Class E P/A compatible FAN3122/TC4422: Single, 6V drive, high drive current (9A)
drivers FAN3223/4/5: Dual 4A, 6V drive, for push-pull or SR application
Sync Buck DC/DC (100V LTC7800: 60V, Sync. Step-Down LTC7800 Datasheet
GaN): Controller (up to 2.2MHz, w/
integrated GaN compatible drivers)
1. 48V-12V DC/DC
Secondary side NCP4305A: 5V gate drive clamp, NCP4305 Datasheet
Rectification (100V GaN): 1MHz max
1. High frequency LLC
SRK2001: Adaptive SR controller SRK2001 Datasheet
2. Flyback
for LLC, 5-6V drive for GaN,
500KHz max

[*] Low side non-isolated drivers can also be used on high side / half bridge configurations by combining with level-shift /
signal isolators, see page 29 for design example. E
q

qW >

q d

E
 s/ s
VDD: 5/9 or 12V depending on system Si8271-based isolated driver (0-6V drive) 6V LDO for tight VDRV regulation
power rail

Optional CM Choke for better noise

immunity against dv/dt

Choose isolated DC/DC PS1:

• 5/9/12V to 9V, 1W, 3kV isolation
• Low CIO preferred for dv/dt immunity Keep this loop
• Verified/Recommended P/N: routing as tight as
• RECOM R1S-xx09/HP possible
• Mornsun Fxx09XT-1WR2

PWM Input:
• 3.3V or 5V logic from controller
• Optional RC filter for noise filtering
• Consider driver w/ deglitcher (-IS1
suffix) for noisy environment

Enable:
Gate resistors:
• Direct tie to VDDI if not used
Isolation 1. Turn-on RGATE R2: typ. 10-20Ω
• Recommend filter cap (100nF) close
2. Turn-off RGATE R3: typ. 1-2 Ω
to EN pin to prevent false triggering
Recommended for high-frequency ZVS application E
 s/
Si8271-based isolated gate driver (-3/+6V drive)
• Lower risk of cross-conduction
and gate oscillation, faster
turn-off (lower switching loss)
• Higher reverse conduction
loss
• Recommended for hard-
switching or high power
applications

DZ1 and R2 divide 9V into -6V and

+3v gate bias. The mid-point is
used as a ground 0V which should
be connected to the SS of GaN
device

• Place bypass cap C7/C8 close

to U1 VDD/GND
• Keep loop between U1 and Q1
Gate/SS as tight as possible
• Higher UVLO driver can be used

E
 ,
Recommended for low cost high frequency soft switch half bridge circuit (ACF, LLC etc)
DB1 GS66504B
SI8273
Use fast recovery low CJ diode for
Bootstrap:
• C3D1P7060Q
• UFM15PL
• ES1J

>> s ,

E
K s
ADuM4121ARZ-based isolated gate driver for GaN HEMT (0-6V drive)

E
K s
Isolated gate driver based on ACPL-P346 (-4/6V)

,
E s , Dd Ω d
W> W

W> W Z ZD
E
 s E W
U1
J2 6V REG
1 9V_EXT 1 5
IN OUT VCC_6V

A98235
2
C1
1.0 µF
0603
2

3
GND
4
C2
2.2 µF
0603
R17
DNI
0603
• 80V HB driver for GaN
ON_OFF BYPASS R18

• Support 6V gate drive

C3
10 nF DNI
0603 0603 TPSMD1
5017 CON1
575-8
VCC_6V
R23
D1
BAS70LP-7
R2
VIN+
BANANA JACK
1
• 48V DC/DC application
HSB

DNI
R24
0
0603 C7
0.10 µF
0603 CR1
C17
1 µF
100V
C16
1 µF
100V
C15
1 µF
100V
C13

(DNI)
C12

(DNI)
C11

(DNI)
C10

(DNI)
CON2
575-8
• High frequency (>5MHz)
• Dead time adjustable
0 CZRU52C6V2 (DNI) BANANA JACK

VIN- 1
VDDsy nc

JP4
VCC_6V
HSS
• Small low inductance Pkg
TSW-103-07-G-S
HDR_1X3_0.100"_VT TPSMD2
1 C9 5017
2 0.10 µF
3

U4
0603
Q1
PE29101
15

GS61008P DS

1
PE29101
D
VDD

3
HSB
G

6 R8 4.7 OHM 2 TPSMD3

HSGpu HS1 5017
R9 1
S

1 CON3
HSGpd

4
575-8

3
2 BANANA JACK
8 HSS L1
IN 14 3.3uH ±20% VOUT+ 1
LSB Q2
R5 EN 7 9 R10 4.7 OHM GS61008P DS

1
PR1 DNI EN LSGpu R14
R21 20K R11 1
PROBE 0402 16 12 D

DNI
RDHL LSGpd
Vddsync

0402 R22 20K 0603 C18 C19 C20 C21 C22 C23
5 13 PR4 D2 1.0 µF 1.0 µF 22 µF 22 µF 22 µF (DNI)
GND

LSO

RDLH LSS 2
G

PROBE 0603 0603 1206 1206 1206

0402 BAS70LP-7B (DNI)
CCW

CCW

HS1 C24 CON4

1

R12 DNI 575-8

11

10

500K
4

0603 BANANA JACK

3

2 2 R13
WIPER WIPER 500K VOUT- 1
VDDsy nc
R6 R7
CW

CW
3

DNI DNI
0402 0402
R1
T1 DNI TPSMD4
0603 5017
R4
DNI
0603

JP3 VCC_6V
TSW-103-07-G-S U3
HDR_1X3_0.100"_VT NC7S08P5XCT
1 1 5
2 IN A VCC
3 R3 2
10K IN B
0603 3 4
GND OUT Y
C28 C8
1.0 µF DNI
0603 0603

http://www.psemi.com/newsroom/new-products/666336-pe29100-gan-fet-driver

E
 s E W
PE29102 - 60V Half Bridge GaN driver, optimized for high frequency applications:
• Class D Audio, DC/DC, wireless power charging

GS61004B-EVBCD

100V GaN E-HEMT Full Bridge Evaluation

Board, optimized for Class D Amplifiers

For more details on the GS61004B-EVBCD evaluation board, visit: http://gansystems.com/design-center/evaluation-boards/

E
E E
• For single-ended applications (Class E, Flyback, Push-pull etc), or
• Used to adapt MOSFET gate drive bias to 5-6V drive for GaN (low or high side)
LM5114 low side driver
9-12V Aux power uP1964 GaN Driver VIN ADJ

LDO LDO

• integrated regulator LDO5

5V
UVLO
DRV
VDRV

GND OUTH

for 6V bias PWM OUTL

• 5V LDO PWMB GND

VDD_RTN

VDD_RTN
VDD_RTN

From controller logic signal (3.3/5V) or

MOSFET driver output (up to 14V)
E
E E
Isolated GaN driver for high side / half bridge using low side driver + signal isolator or HB driver
• Overcome frequency and drive performance limit of previous isolated driver solution
• Adapt to existing controllers/half bridge driver (ensure the driver is capable of handling high dv/dt)
• Improved gate drive loop by locating LS driver close to GaN
5V for isolators

5/9/12V

Place U4 close to
Q1 and keep the
loop tight

Isolation
E
q

qW >

q d

E
E / E y

:XGJO OUTGR 7,4 OX UTJ /TTU G O VGIQGMOTM LUX NOMN V J -G4 J OI

• R XG RU] OTJ[I GTI NOMN LX W[ TI ]O INOTM
• 4 GX INOV IGR SH JJ J VGIQGMOTM
• 4U ]OX HUTJOTM NOMN X ROGHORO
• X :+ SG IN U ：: SV I IR X ROGHORO
• 2U] N XSGR X O GTI Θ0

500
TO-247
400

Vds_Si / V
300

200
GaNPX® package
Ls = ~10-15nH 100

G -0
3.02 3.04 3.06 3.08 3.1 3.12 3.14 3.16 3.18 3.2
D
S Time/uSecs 20nSecs/div

• High dV/dt
• Low VDS overshoot
• Better EMI LSource<0.2nH

+SH JJ J E y VGIQGM A C -G4 o VGIQGM VG J NX / URJ X PUOT X ROGHORO

IUTJO OUT： 2G X SS ， U OTT X IUVV X GTJ U U[ X IUVV X。
E
W >
LP1
E y
LD1
• E y W CGD_ext1
LG1 RG1
• E y d d Gate
Driver
Q1

• d CISO LM1 LCS1

LG2
LLoop
LS1
D 0V
CDC_LINK
> LD2
CGD_ext2
> LG3 RG1
Gate Q2
W > > Driver
LM1 LCS2
LG4
/ / K LS2
0V LP2

E
 E y
•
•
• W W
DRAIN
s Ω
GS66508B

SOURCE

G SS

d GATE DRIVER Thermal vias

s Ω s Ω
DRAIN

GS66504B

G SOURCE

Gate Return Main Current Flow

< W E
 E y W

•
• h
• d W

W s Ω
DRAIN
d

Gate Thermal Pad (connect

to Source)
SS

Gate Return SOURCE

E
>
Non-isolated control
ground 0V
1 h
>
W DRAIN

GS66508B
5
4
2 D down loop (Gate→R3 →
U1 → C2 →GS_RTN, locate U1 and C2
GD_RTN
SOURCE
VDD_6V
Gate Kelvin
C1 Source
3
3 D R2
Si8271 1 Main current flow
R3 R4
2

4 / C2
GD_RTN
Mid/bottom layer VEE_-3V

VDD

/ C1 DRAIN1
5 PWM_IN R1 1
U1
8 1uF
GD_RTN
1
VI VDD
10 2 7 R2 GATE 2 Q1
VCC_+5V VDDI VO+
GD_RTN
Dd/
10 R3 GS66508B
3 6 3
C3 GNDI VO- R4

4
1uF ENA 4 5 2 10k
EN GNDA VEE
SI8271AB-IS C2 PGND
1uF
0V
GD_RTN

E
> d

1 E y d

DRAIN
2 (bot side)

3 h
GD_RTN

C1
4 h GS66508T
Gate R2 (bot side) 4
Driver Gate
VDD R3 G Source G
C1 DRAIN1
U1 GD_RTN
1

R1 1 8 1uF
PWM_IN
VI VDD
Q1
1
C2
42

10 2 7 R2 GATE
VCC_+5V VDDI VO+ GS66508T
3 6 10 R3
C3 GNDI VO- R4 3
3

1uF ENA 4 5 2 10k

EN GNDA VEE GD_RTN
SI8271AB-IS C2
Main
0V
1uF current flow
GD_RTN
2

E
> d d

Keep out area: Avoid placing traces or vias on the top layer
of the PCB, directly underneath the top-side cooled
package. This is to prevent potential electro-migration and
solder mask isolation issues during high temperature
or/and voltage operation.
Symmetrical dual gates are provided for flexible layout and
easy paralleling. Either gate drive can be used. If the
second gate is note used, it should be left floating.
A separate Source Sense pin is not provided on our top-
side products because of the ultra-low inductance of our
E y packaging. The Source Sense pin functionality can
be implemented by routing a Kelvin connection at the side
of the Source pad. This can be done at either side of the
source pad for layout optimization.

E
> ,

, ,
> h W K
• Z > W GaN E-HEMTs
Decoupling
Caps GaN E-HEMTs
• h PGND
TOP LAYER

h D D>
PGND VSW VIN+
• PGND
LAYER 2
PGND VIN+
TOP LAYER

E LAYER 3
Layer 2
LAYER 4 VSW

• h
Z > PGND

Gate VIN+
• > VIN+
Driver

VSW
• h Gate
Driver VSW PGND

Gate
Driver
Gate
Driver PGND

E
q

qW >

q d

E
 d ,

/ K
s
h
WtD ss s s s t
E
 s W >
E
s ,
E
s

s t s t

s >

d > D

E E

s t
s t

D >
E
§ s s / Z Ω Z Ω
KE K&&
s
/ />
s s
VDC+

LOUT
+ Q1
IL
VDS
400V DC VSW

Q2
VGL

E
s s / , d s s/ , d

> ,
/> />
s s s
s s
∆V=> W d
s
W
s

s
s s

E
§ d E E
, Dd t E , Dd

§ d W
E E y

§ d
s d
E y
E , Dd