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Electrical/Service REQUIREMENTS

FOR
FRU Fault Detection and Isolation

LCM Reference No: XCTV-090316


Document Version: 1.0
Date: Mar 15 2007

Name Signature Date

Prepared by: Electrical Service Committee

Reviewed by: Avi Argaman Signature on File 3/15/07

Reviewed by: Hung Wong Signature on File 3/18/07

Reviewed by: Jeff Rothman Signature on File 3/15/07

Reviewed by: Rich Vickery Signature on File 3/15/07

Reviewed by: Miki Klein Signature on File 3/15/07

Approved by: Gad Fraenkel Signature on File 3/15/07

Approved by: Charles Rooks Signature on File 3/15/07

THIS DOCUMENT CONTAINS PROPRIETARY AND CONFIDENTIAL INFORMATION OF PHILIPS MEDICAL SYSTEMS (CLEVELAND), INC. AND
THE CONTENT IS INTENDED FOR EXCLUSIVE USE BY AUTHORIZED, CURRENT PERSONNEL OF PHILIPS MEDICAL SYSTEMS. COPYING,
DISCLOSURE TO OTHERS, OR OTHER USE IS PROHIBITED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF PHILIPS MEDICAL
SYSTEMS' LAW DEPARTMENT. REPORT VIOLATIONS OF THIS REQUIREMENT TO THE PHILIPS MEDICAL SYSTEMS' LAW DEPARTMENT,
HIGHLAND HEIGHTS, OHIO.
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All rights reserved Template No.: XCTT 030 4004 Rev. A 03/04/2003
Requirements for Electrical/Service Design Document

Revision History

Revision Date Changed by: Reason for change


0.1 20 Nov 2006 Avi Argaman New document
0.2 Jan 10 2007 Gad Fraenkel
0.3 1 Mar 2007 Avi Argaman Including comments from srv prg and SE’s.
1.0 Mar 15 2007 Gad Fraenkel Releasing first Version

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Table of Contents
REVISION HISTORY........................................................................................................................................................... 2

1 INTRODUCTION .......................................................................................................................................................... 4
PURPOSE .............................................................................................................................................................................. 4
SCOPE ................................................................................................................................................................................... 4
1.1. OVERVIEW ................................................................................................................................................................ 6
2. GENERAL REQUIREMENTS .................................................................................................................................... 7
2.1. SERVICE MODE TESTS ............................................................................................................................................... 8
2.2. CT MODE TEST (BIST) ............................................................................................................................................. 8
3. DETAILED HARDWARE IMPLEMENTATION REQUIREMENTS ................................................................. 11

4. DETAILED TESTING REQUIREMENTS............................................................................................................... 13

5. SYSTEM CONFIGURATION.................................................................................................................................... 15

6. ELECTRICAL GUIDELINES FOR DESIGN FOR SERVICEABILITY ............................................................. 16

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Requirements for Electrical/Service Design Document

1 Introduction

Purpose
The purpose of this document is to provide list of guidelines and keys requirements that shall be taken into
consideration during the developments phase by electrical/electronic designers in order to achieve system
serviceability.

Scope
The scope of this document are to list electrical guidelines and keys requirements to be used in the design phase
of every electrical assembly in order to design CT product for serviceability.

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Definitions, Acronyms, and Abbreviations


MTTR – Mean Time to Repair.
System Serviceability – A characteristic of a given system, that is necessary in order to decrease the MTTR to
optimum level and to shorten scanner installation time.
FRU – Field Replaceable Unit.
ESD – Electrostatic Discharge.
FSE – Field Service Engineer.
CRC – Cyclic Round Check.
BER – Bit Error Rate.
POST – Power On Self Test.
BIST – Built In Self Test.
LED – Light Emitting Diode.
Off-line – Scanner is in Service login, patient scan is not taking place in this mode.
On-line – Scanner is in CT login, patient scan take place in this mode. .
Questra – Remote application.
SAAT – System Actionable Analysis Tool
PLD – Programmable logic device (FPGA, CPLD, CPM, Embedded processor ….).
COTS – Component Of The Shelf.
Fault Detection - The ability to detect any given fault in the specific subsystem.
Fault Isolation - The ability to Isolate the root-cause of the specific failure, could be FRU or S/W component.
I/O’s – Inputs and outputs.
Destructive test – A test that may change the status of the scanner from “ready to scan” into “need a recovery”.
Soft Reset – Is a command that target to a H/W or S/W part as FPGA/CPM and it initialize the state of the H/W
and S/W to “ready to scan” state in a very short time (not like hard reset).
Controllers – FPGA, CPM, PC (Host & Gantry), CIRS servers.
Scanner Idle state - Scanner is between scans.
TBD - To be define.

References
Category Document Titles Doc # Dated Rev
CT
products.

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1.1. Overview

This document contains list of guidelines in which all CT products designer should take into account in the
design phases in order to make the design serviceable.
The audiences of this document are the Electronics and System designers.
This document developed with the cooperation and support of the engineering and all the listed requirements in
this document were approved by the engineering.

This Document is organized in a manner, which progresses from general information towards specific functions,
interfaces, communication protocols and performance needed from the Tool.

To handle these functions, the Tool issues many tasks ([Keys]).


The electrical service design needs to withstand several performances in order to fulfill all the tasks [Keys] it is
responsible of.
Each task has its own [Key] which may either be linked to a references document or is a local [Key].
All Tool relevant keys from are detailed in this document and explained of how been achieved.
1.1.1 Requirements Terminology

The following terminology is used:

‘Shall’ Identifies a mandatory requirement.


‘Should’ Denotes a recommended requirement.
‘May’ Identifies a permissible requirement.

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2. General Requirements
Test Structure

2.a Service Mode Tests


2.1a1 On Demand Self Test
2.a.1.1 Off-line Diagnostics Test
2.a.1.2 I/O Test
2.a.1.3 Functional Test
2.a.2 Free Running Test
2.a.2.1 Online test
2.a.2.2 Status Test

2.b CT Mode Tests (BIST)


2.b.1Free Running Test
2.2.1.1 Online test
2.2.1.2 Status Test
2.b.2 Periodic Test
2.b.3 POST
2.2b3.1 Off-line Diagnostics Test
2.b.3.2 I/O Test
2.b.3.3 Functional Test

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Electrical Hardware FRUs:


Category-A FRU shall be signed as Cat-A FRU:
* Controller - Including Controller such as Embedded Processor, PC etc [Example, CIRS Server, DMS CPM]
Category-B FRU shall be signed as Cat-B FRU:
* Smart slave assembly – Including Logic that can run simple diagnostics monitoring tasks [Example: Cirs ACQ
TDMS Detector]
Category-C FRU shall be signed as Cat-C FRU:
* Dumb Slave assembly – FRU without communication to the out side world or monitoring capability [Example:
Motors, Zero RPM gate]
Category-D FRU shall be signed as Cat-D FRU:
* Cables.

2.1. Service Mode Tests


SER.[ Service Mode Tests]
{{
Used during special service mode for FRU Fault Detection and Isolation, including On Demand and Free Running tests.
The test should provide FRU level diagnostics with fault detection of 90% or higher and Isolation of 80% or
higher of the system under test.
}}
2.2. CT Mode Test (BIST)
SER.[ CT Mode Tests BIST)]
{{
Used during nominal operation (CT Mode) for FRU fault Detection and Isolation, including Free Running, Periodic and
Power On(POST) Tests.
The test should provide FRU level diagnostics with fault detection of no less than 80% and Isolation of 50% of
the system under test.
}}

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2.2.1 On Demand Self Test


Description:
When the scanner is in service login, i.e. off-line, the user (FSE) can run diagnostics test on his demand. The user requests
derive lower level requests called on demand self test.

SER.[ Service Mode Tests]

SER.[On Demand Self Test]


{{
Teats shall be used in Service Mode for FRU fault detection and isolation. The test includes Off-line Diagnostic, I/O and
Functional Tests.
}}

2.2.2 Free Running Self Test


Description:
When scanner is powered on, a set of tests are running free without any external intervention. This tests are matching to the
scanner state and different parameters may be tested in each states (before scan, while scan, after scan).
The free running self tests are non destructive test.
SER.[ Service Mode Tests]
SER.[ CT Mode Tests BIST)]

SER.[Free Running Self Test]


{{
Tests shall be used for FRU fault detection and isolation. Tests includes both On-line and Status tests used in both Service
Mode and CT Mode (BIST). Each deviation shall be reported to the system log files.
}}

2.2.3 Periodic Test


Description:
When scanner is powered on and in idle state, a set of tests are running free without any external intervention. These tests
called periodic and they are destructive test.

SER.[ CT Mode Tests BIST)]

SER.[Periodic Test]
{{
Initiated in idle mode between scans, short duration test that is repeated with defined gap between test completions to the
next start. The test can check another part of the design in each iteration. This test should be coordinate between all
subsystems since one system can affect the neighbors while running this test.
The maximum duration between clicking on the "Study" button until scan actually started to perform shall be define per
scanner.
}}
2.2.4 Power-On Self Test (POST)
Description:
While scanner is powered on a set of tests are running without any external intervention. These tests involve destructive and
non destructive routines and limited to TBD run time.

SER.[ CT Mode Tests BIST)]

SER[Power on Self Test]


{{
Power On Self Test (POST) – Including Off-line Diagnostic, I/O and Functional Tests. The test shall be used in CT
Mode for FRU fault detection and isolation.
}
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}
2.2.5 Offline Diagnostics Test
SER[Offline Diagnostics test]
{{
Offline Diagnostics Test is a set of programs that systematically testing each component (all of internal cells in the case of
IC such as Memory, Transceiver, Programmable device etc) and each connection within the FRU/Subassembly. In Case
that these programs can not test each separate device or signal onboard, an aggregate of component testing is an alternative
given that it provides sufficient tests able to determine if the FRU under testing is defective.
}}

2.2.6 I/O Test


SER[I/O Test]
{{
Set of programs that performs testing of I/O between subassemblies, It done initially by sensing the status of input while
assuming the counterpart is in idle mode and later by an combined test of activating line in the transmitting subassembly
and testing the status in the receiving subassembly.
}}
2.2.7 Functional Test
SER[Functional Tests]
{{
Injecting known Patterns in the input. Running a test that is almost functional identical to a scan and testing the output
results.
}}
2.2.8 Online test
SER[Online Test]
{{
Real Time constant continuous testing that is done by the hardware while the power is “on”, These are all the exceptions
and events that the hardware can identify, usually such cases are reported as events/interrupts to the Controller, Examples
are Communication lines CRC/Parity Memory devices Parity/CRC/ECC/Parity, Communication Signal loss, No Power and
any event that the hardware is monitoring.
}}

2.2.9 Operation Status Monitoring


SER[ Oper Status Mon]
{{
Testing parameters that are changing relatively slow enough. The Controller is monitoring the status without affecting the
scanner operation. Examples are Temperature, Motor operating current, Voltage Buffer size etc.

During certain normal operation, such as FRU temperature, # of Resend, rotation startup to speed, collimator blade moving,
Fan speed monitoring, the operation characteristics shall be monitored and compared with acceptable range. Any out of
range occurrence shall be logged and analyzed for potential system degradation or maintenance requirement. For example,
if the normal expected time to rev up rotor from 0 to 120RPM is exceeded, or fan speed is out of the normal range, this may
be an indication of immediate maintenance need or system degradation.
}}

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3. Detailed Hardware Implementation Requirements

3.1.1 Offline Diagnostics Hardware Implementation


SER[Power on Self Test]
SER.[On Demand Self Test]

SER[Off-line Diagnostics HW Implementation]


{{
• Each I/O and memory port (programmable device, memory and any IC including I/O port) shall be accessible for
write and read operation.
• Each internal FRU logic line/signal shall be tested, not including decoupling capacitor lines.
• Every FRU containing Frequency source (Oscillator) should have measures (i.e. counter) that can be compared
against another frequency source if possible.
• All FPGA internal functions should be tested.
• Every fast (>200MHz) channel using as Serializer / Deserializer (SERDES) should have an internal loop-back, It
may have also an external Loop-Back
}}

3.1.2 Operation Status Monitoring Hardware Implementation


SER.[Free Running Self Test]

SER[Operation Status Monitoring Hardware Implementation]


{{
• Each internal power supply, DC to DC converter and regulator voltage shall be accessible.
• Each external power supply voltage shall be accessible.
• Every FRU that have a potential temperature issue shall have temperature sensor accessible for testing.
• Every motion driver shall have accessible over current indication.
}}

3.1.3 Offline Diagnostics and Status Hardware Implementation


SER[Power on Self Test]
SER.[On Demand Self Test]
SER.[Free Running Self Test]

SER[Off-line Diagnostics and Status Hardware Implementation]


{{
• Each motion device shall have measurement device that can test the expected motion Vs the actual motion.
• Every resolver shall have secondary reference (such sin/cos Vs index/Zero_gate) to enable resolver fault isolation.
• Cat A & B FRU shall be designed to check its communication link error rate, i.e. count the number of the errors
(by HW or SW implementation).
• Cat A & B FRU should be designed to check its memory error rate, i.e. count the number of the errors (by HW or
SW implementation).
• Cat-A & B FRU shall have own non volatile memory to store the serial number, date code, parent FRU etc. This
information shall be accessible by SW.
• Cat-C FRU shall be design to provide independent feedback of “Work OK”. E.g. Fan shall provide tachometer
feedback motor/actuator shall provide encoder and/or index feedback etc.
• Flow sensors as air, water, oil, liquid coolant shall be added to the system and shall be accessible by SW.
• Cat-A & B FRU shall have assembly configuration accessible by SW, This circuitry shall not be implemented by
programmable device (Recommendation: using Pull Down Resistors).
• Cat-A & B FRU shall hold on the own programmable device the version and revision of the FRU. This
information shall be accessible by SW.

}}
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3.1.4 On-line Hardware Implementation


SER.[Free Running Self Test]

SER[On-line Tests]
{{
• Every serial communication channel output data packet shall be followed by CRC.
• Every serial communication channel input shall constantly test the presence of incoming idle communication.
• Every memory device shall have parity/CRC generation and Checking.
• Every FRU with memory correction mechanism shall test both single error and multi error faults.
• Every wide data bus shall have parity/CRC generation and Checking.
• Every bus access for setting control parameters shall be followed by read, verified and report operation.
• Every fast channel receiver shall have “Loss of signal” and “out of Sync” feedback signals.
• Every fast channel receiver fault shall be reported to S/W.
• Every main diagnostic Channel (i.e. between two Controllers) shall have the capability to transfer indication of an
error in this main Channel via an alternative channel.
}}

3.1.5 I/O Test Hardware Implementation


SER[Power on Self Test]
SER.[On Demand Self Test]

SER[I/O Test]
{{
• Cat- A & B FRU shall be designs to sense unconnected external Input (I/O) signal.
• Cat- A & B FRU shall be designs to toggle external Output (I/O) on demand.
• Any external I/O signal shall be activated by the transmitter side and tested by the receiver side during the test.
• Communication loses errors shall be reported by lit a LED on the destined FRU.
• Cat- A & B FRU should be designs to sense external output signal as a feedback.
}}

3.1.6 Functional Test Hardware Implementation


SER[Power on Self Test]
SER.[On Demand Self Test]

SER[Functional Test]
{{
• Cat- A & B FRU that is responsible for data processing shall be design to include a pattern Generator/Simulator in
the Input stage.
• Cat- A & B FRU that is responsible for data processing shall be design to include a pattern Checker in the output
stage.
}}

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3.1.7 Periodic Test Hardware Implementation


SER[Periodic Test]
{{

• Cat – A & B FRU shall support soft reset to enable fast exit from the periodic test (TBD) without the need for
processor reset and with the ability to stabilize defined state for the FRU.
• FRU Soft Reset response time shall not exceed 10 (TBD) milliseconds.
}}

4. Detailed Testing Requirements

4.1.1 Offline Diagnostics Testing


SER[Power on Self Test]
SER.[On Demand Self Test]

SER[Off-line Diagnostics Testing]


{{
• Each I/O and memory port (programmable device, memory and any IC including I/O Port) shall be tested during
this test.
• All counters and internal FPGA functions should be tested.
• Each memory Device shall be tested using patterns 55, AA.
• Each memory data an address bus shall be tested with walking ‘1’ pattern.
• Each internal FRU logic line/signal shall be tested, not including decoupling capacitor lines.
• Every frequency source (oscillator) frequency shall be tested and compared with external oscillator during this
test.
• Every Fast Channel (>200MHz) Loop-back test shall be tested.
}}

4.1.2 Operation Status Monitoring Testing


SER.[Free Running Self Test]

SER[Operation Status Monitoring testing]


{{
• Each internal power supply, DC to DC converter and regulator voltage value and limits shall be tested during this
test.
• Each external power supply voltage value and limits shall be tested during this test.
• Every temperature sensor value and limits shall be tested during this test.
• Every motion driver over current shall be tested during this test.
}}

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4.1.3 Offline Diagnostics and Status Testing


SER[Power on Self Test]
SER.[On Demand Self Test]
SER.[Free Running Self Test]

SER[Off-line Diagnostics and Status Testing]


{{
• Each motion device position and velocity shall be tested during this test. (expected Vs. Actual).
• Each - (air, water, oil, liquid coolant) measurement value and limits shall be tested during this test.
• Communication violation errors test (CRC/ECC) for Cat A & B FRU shall be performed.
• Memory violation error test (Parity/CRC/ECC) for Cat A & B FRU shall be performed.
• Electronic serial number (in NVRAM) shall be read and verified for Cat A & B FRU.
• All devices feedback shall be tested as fan Vs. tachometer, motor/actuator Vs. encoder/index/resolver,
Heater/Cooler V.S Temperature sensor etc.
• All critical flows- (air, water, oil, liquid coolant) shall be measured and verified in spec limits.
• Cat A & B FRU read and verify the H/W, F/W and S/W Version.
}}

4.1.4 On-line Testing


SER.[Free Running Self Test]

SER[On-line Tests]
{{
• Communication channels shall be tested to verify acceptable bit error rate.
• Communication channels live test shall be tested.
• Memory devices shall be tested to insure the read data is correct.
• Memory error correction shall be reported as warning to the S/W and shall be reported as error when correction is
not possible.
• Wide data bus violation shall be reported to the S/W.
• Fast channel receiver failures shall be reported to the S/W.
}}

4.1.5 I/O Testing


SER[Power on Self Test]
SER.[On Demand Self Test]

SER[I/O Test]
{{
• Cat A & B FRU unconnected external Input test shall be performed and reported to S/W.
• Internal I/O loopback test should be performed and reported to S/W.
}}

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4.1.6 Functional Testing


SER[Power on Self Test]
SER.[On Demand Self Test]

SER[Functional Test]
{{
Pattern injection test shall be performed and reported to the S/W.
}}

4.1.7 Periodic Testing


SER[Periodic Test]
{{
• Periodic test recovery time shall not exceed TBD milliseconds.
• Subassembly shall comply with all Interface definition with its neighbors subassembly when starting, Executing
and stopping its Periodic Test
• Subassembly may test another part of the H/W in each iteration.
• Periodic test may call any test except the Free running self test.
}}

5. System Configuration

5.1.1 System Configuration

SER[System Configuration]
{
• System shall be design to support fast configuration changes for all PLD’s including COTS as possible without
any manual intervention, i.e. no external programming cable or programmer shall be needed.
• System PLD’s shall be design to provide “Program Done” feedback as a data sanity check.
}}

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6. Electrical Guidelines for Design for Serviceability

6.1.1 Electrical Guidelines for Design for Serviceability


SER[Electrical Guidelines to design for serviceability]
{{
• FRU shall be designed to be carry & mounted by FSE, I.e. ESD protected.
• Physical connections between FRUs shall be designed to be minimal, i.e. less discreet lines, more parallel to
serial communication channel.
• LEDs shall be located in a way that the FSE shall need to open as less covers as possible, e.g. not on the
bottom of the boards or hidden behind any obstacle. If necessary to make clearance (window) in the object in
order to enable watching the LEDs.
• Replaceable fuses shall be located in a way that the FSE shall need to open as less covers as possible, e.g. not
on the bottom of the boards or hidden behind any obstacle. If necessary to make clearance (window) in the
object in order to enable watching the replaceable fuses.
• FRU COTS shall support same guidelines as proprietary FRU.
• Scanner shall be designed to reuse same FRU as possible, e.g. one CPM for all, one cable type for several
subsystems.
• Scanner shall be designed to enable swaps of same FRUs, e.g. Module swaps, cable swaps.
• FRU and scanner shall be design to provide test points to easily measure power level
• Neither of the tests should change any state machine that can cause an interference with the user work, cause
an unacceptable performance decrease or damage\change any other machine functionality.
}}

Digitally signed by Bob McFeely


Reason: This Document is
Released
Location: Cleveland, Oh 44143
Date: 2007.03.19 09:05:57 -04'00'

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